System and method for accelerating data search on database storage systems

Abstract

Embodiments of the present disclosure provide a system for accelerating data search for a database storage system. The system includes a host device including a database storage engine, and a memory system including a controller and a memory device, the memory device including a plurality of pages storing a number of records. The controller includes a page processing accelerator configured to, in response to a filtered read command, read a number of pages of the plurality of pages, filter a particular page among the number of pages based on a column-wise search condition, the filtered page including entries satisfying the column-wise search condition, and communicate information about the filtered page to the host device.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a data search scheme for a database storage system. Background Technology

[0002] The computing environment paradigm has evolved into ubiquitous computing systems that can be used anytime, anywhere. Consequently, the use of portable electronic devices such as mobile phones, digital cameras, and laptops has increased rapidly. These portable electronic devices typically use memory systems with memory devices (i.e., data storage devices). Data storage devices serve as either the main memory or auxiliary memory devices in portable electronic devices.

[0003] Because memory devices have no moving parts, memory systems using memory devices offer excellent stability, durability, high data access speeds, and low power consumption. Examples of memory systems with these advantages include Universal Serial Bus (USB) memory devices, memory cards with various interfaces such as Universal Flash Memory (UFS), and solid-state drives (SSDs). Memory systems can be used in database storage systems. Summary of the Invention

[0004] The present invention includes a system and method for accelerating data retrieval in a database storage system.

[0005] In one aspect of the invention, a system includes: a host device including a database storage engine; and a memory system including a controller and a memory device including multiple pages storing a plurality of records. The controller includes a page processing accelerator configured to: read a plurality of pages from the plurality of pages in response to a filtered read command; filter a specific page from the plurality of pages based on a column-wide search condition, the filtered page including entries that satisfy the column-wide search condition; and transmit information about the filtered page to the host device.

[0006] In another aspect of the invention, a method for operating a system including a host device and a memory system, the host device including a database storage engine, the memory system including a controller and a memory device including multiple pages storing a plurality of records, the method comprising: configuring a page processing accelerator in the controller; reading a plurality of pages from the plurality of pages by the page processing accelerator in response to a filtered read command; filtering a specific page from the plurality of pages by the page processing accelerator based on a column full search condition, the filtered page including entries satisfying the column full search condition; and transmitting information about the filtered page to the host device by the controller.

[0007] Additional aspects of the invention will become apparent from the following description. Attached Figure Description

[0008] Figure 1 This is a block diagram illustrating a data processing system according to an embodiment of the present invention.

[0009] Figure 2 This is a block diagram illustrating a memory system according to an embodiment of the present invention.

[0010] Figure 3 This is a circuit diagram illustrating a memory block of a memory device according to an embodiment of the present invention.

[0011] Figure 4 This is a diagram illustrating the state distribution of different types of cells in a memory device according to an embodiment of the present invention.

[0012] Figure 5A This is a diagram illustrating an example of encoding for a multi-layer cell (MLC) according to an embodiment of the present invention.

[0013] Figure 5B This is a diagram illustrating the state distribution of pages in a multi-layer cell (MLC) according to an embodiment of the present invention.

[0014] Figure 6A This is a diagram illustrating an example of Gray coding for a three-layer cell (TLC) according to an embodiment of the present invention.

[0015] Figure 6B This is a diagram illustrating the state distribution of pages in a three-layer cell (TLC) according to an embodiment of the present invention.

[0016] Figure 7A A database storage system according to an embodiment of the present invention is illustrated schematically.

[0017] Figure 7B A page of a storage device in a database storage system is schematically shown according to an embodiment of the present invention, which maps data records to data records.

[0018] Figure 8 This is a diagram illustrating a database storage system according to an embodiment of the present invention.

[0019] Figure 9 A page of a storage device in a database storage system is schematically shown according to an embodiment of the present invention, which maps data records to data records.

[0020] Figure 10 This is a flowchart illustrating a method for operating a memory system to accelerate database searches on a database storage system according to an embodiment of the present invention.

[0021] Figure 11 This illustrates the sequence of operations of the memory system according to an embodiment of the present invention.

[0022] Figure 12 This is a diagram illustrating a database storage system according to an embodiment of the present invention.

[0023] Figure 13 This illustrates the Partition Attributes Across (PAX) page according to an embodiment of the present invention. Detailed Implementation

[0024] Various embodiments of the invention are described in more detail below with reference to the accompanying drawings. However, the invention may be implemented in different forms and therefore should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure thorough and complete, and to fully convey the scope of the invention to those skilled in the art. Furthermore, references herein to “embodiment,” “another embodiment,” etc., are not necessarily directed to only one embodiment, and different references to any such phrases are not necessarily directed to the same embodiment. The term “embodiment” as used herein does not necessarily refer to all embodiments. Throughout this disclosure, the same reference numerals refer to the same parts in the drawings and embodiments of the invention.

[0025] This invention can be implemented in many ways, including: processes; apparatus; systems; computer program products implemented on computer-readable storage media; and / or processors, such as processors adapted to execute instructions stored on and / or provided by memory linked to and / or linked to the processor. In this specification, these embodiments or any other forms in which the invention may take may be referred to as techniques. Generally, the order of operation of the disclosed processes can be varied within the scope of this invention. Unless otherwise stated, components described as suitable for performing a task, such as processors or memory, may be implemented as general-purpose components temporarily configured to perform that task at a given time or manufactured as dedicated components to perform that task. As used herein, the term "processor," etc., refers to one or more means, circuits, and / or processing cores suitable for processing data such as computer program instructions.

[0026] The methods, processes, and / or operations described herein can be executed by code or instructions to be run by a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device can be those described herein or those other than the elements described herein. Because the algorithm (or operation of the computer, processor, controller, or other signal processing device) upon which the method is based is described in detail, the code or instructions for implementing the methods can transform a computer, processor, controller, or other signal processing device into a dedicated processor for executing the methods herein.

[0027] When implemented at least in part in software, controllers, processors, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, and other signal generation and signal processing functions may include, for example, memory or other storage devices for storing code or instructions to be executed by, for example, a computer, processor, microprocessor, controller, or other signal processing device.

[0028] The following provides a detailed description of embodiments of the invention, along with accompanying drawings illustrating various aspects of the invention. The invention is described in conjunction with these embodiments, but is not limited to any particular embodiment. The scope of the invention is defined only by the claims. The invention encompasses many alternatives, modifications, and equivalents within the scope of the claims. Numerous specific details are set forth in the following description to provide a thorough understanding of the invention. These details are provided for illustrative purposes; the invention may be practiced without some or all of these specific details. For clarity, technical materials known in the art related to the invention have not been described in detail so as not to unnecessarily obscure the invention.

[0029] Figure 1 This is a block diagram illustrating a data processing system 2 according to an embodiment of the present invention.

[0030] Reference Figure 1 The data processing system 2 may include a host device 5 and a memory system 10. The memory system 10 may receive requests from the host device 5 and operate in response to the received requests. For example, the memory system 10 may store data to be accessed by the host device 5.

[0031] The host device 5 can be implemented using any of a variety of electronic devices. In various embodiments, the host device 5 may include electronic devices such as: a desktop computer, a workstation, a 3D television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, and / or a digital video recorder and a digital video player. In various embodiments, the host device 5 may include portable electronic devices such as: a mobile phone, a smartphone, an e-book reader, an MP3 player, a portable multimedia player (PMP), and / or a portable game console.

[0032] The memory system 10 can be implemented using any of a variety of storage devices such as solid-state drives (SSDs) and memory cards. In various embodiments, the memory system 10 can be configured as a component of a variety of electronic devices such as: computers, ultra-mobile personal computers (PCs) (UMPCs), workstations, netbook computers, personal digital assistants (PDAs), portable computers, network tablet PCs, wireless phones, mobile phones, smartphones, e-book readers, portable multimedia players (PMPs), portable gaming devices, navigation devices, black boxes, digital cameras, digital multimedia broadcasting (DMB) players, 3D televisions, smart televisions, digital audio recorders, digital audio players, digital picture recorders, digital picture players, digital video recorders, digital video players, data center storage devices, devices capable of receiving and transmitting information in a wireless environment, radio frequency identification (RFID) devices, and a variety of electronic devices for home networks, a variety of electronic devices for computer networks, a variety of electronic devices for telematics networks, or a variety of components for computing systems.

[0033] The memory system 10 may include a controller 100 and a memory device 200. The controller 100 can control all operations of the memory device 200.

[0034] The memory device 200 can perform one or more erase, program, and read operations under the control of the controller 100. The memory device 200 can receive commands (CMD), addresses (ADDR), and data (DATA) via input / output lines. The memory device 200 can receive power (PWR) via power lines and control signals (CTRL) via control lines. Depending on the design and configuration of the memory system 10, the control signal CTRL may include command latch enable signals, address latch enable signals, chip enable signals, write enable signals, read enable signals, and other operation signals.

[0035] The controller 100 and the memory device 200 can be integrated into a single semiconductor device such as a solid-state drive (SSD). The SSD may include a storage device for storing data therein. When the memory system 10 is used in an SSD, a host device (e.g., ...) is coupled to the memory system 10. Figure 1 The operating speed of the host device 5) can be significantly improved.

[0036] The controller 100 and memory device 200 can be integrated into a single semiconductor device such as a memory card. For example, the controller 100 and memory device 200 can be integrated to configure PC cards, compact flash memory (CF) cards, smart media (SM) cards, memory sticks, multimedia cards (MMC), miniature multimedia cards (RS-MMC), micro-sized versions of MMC (micro MMC), secure digital cards (SD cards), mini secure digital cards (mini SD cards), micro secure digital cards (micro SD cards), high-capacity secure digital cards (SDHC), and / or universal flash memory (UFS).

[0037] Figure 2 This is a block diagram illustrating a memory system according to an embodiment of the present invention. For example, Figure 2 The memory system can be described Figure 1 The memory system 10 shown.

[0038] Reference Figure 2 The memory system 10 may include a controller 100 and a memory device 200. The memory system 10 can respond to input from a host device (e.g., Figure 1 The host device 5) operates upon request and, in particular, stores data to be accessed by the host device.

[0039] The memory device 200 can store data to be accessed by the host device.

[0040] The memory device 200 may be implemented using volatile memory devices such as dynamic random access memory (DRAM) and / or static random access memory (SRAM) or non-volatile memory devices such as read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric random access memory (FRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM) and / or resistive RAM (RRAM).

[0041] The controller 100 can control the storage of data in the memory device 200. For example, the controller 100 can control the memory device 200 in response to a request from the host device. The controller 100 can provide data read from the memory device 200 to the host device, and can store data provided from the host device into the memory device 200.

[0042] The controller 100 may include a storage device 110, a control component 120, an error correction code (ECC) component 130, a host interface (I / F) 140, and a memory interface (I / F) 150 connected via a bus 160. The control component 120 may be implemented as a processor such as a central processing unit (CPU).

[0043] Storage device 110 can be used as working memory for memory system 10 and controller 100, and stores data for driving memory system 10 and controller 100. When controller 100 controls the operation of memory device 200, storage device 110 can store data used by controller 100 and memory device 200 for operations such as read operations, write operations, programming operations and erase operations.

[0044] Storage device 110 may be implemented using volatile memory such as static random access memory (SRAM) or dynamic random access memory (DRAM). As described above, storage device 110 can store data used by the host device in storage device 200 for read and write operations. To store data, storage device 110 may include program memory, data memory, write buffer, read buffer, mapping buffer, etc.

[0045] Control component 120 can control the general operation of memory system 10 and control write or read operations on memory device 200 in response to write or read requests from host device. Control component 120 can drive firmware called Flash Translation Layer (FTL) to control the general operation of memory system 10. For example, FTL can perform operations such as logical-to-physical (L2P) mapping, wear leveling, garbage collection, and / or bad block handling. L2P mapping is called logical block addressing (LBA).

[0046] During a read operation, the ECC component 130 can detect and correct errors in the data read from the memory device 200. When the number of error bits is greater than or equal to the threshold number of correctable error bits, the ECC component 130 may not correct the error bits, but may instead output an error correction failure signal indicating that the correction of the error bits has failed.

[0047] In various embodiments, ECC component 130 may perform error correction operations based on coding modulation such as low-density parity-check (LDPC) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, turbo codes, turbo product codes (TPC), Reed-Solomon (RS) codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), or block-coded modulation (BCM). However, error correction is not limited to these techniques. Therefore, ECC component 130 may include any and all circuitry, systems, or devices suitable for error correction operations.

[0048] The host interface 140 can communicate with the host device through one or more of the following communication standards or interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), High-Speed ​​Peripheral Component Interconnect (PCI-e or PCIe), Small Computer System Interface (SCSI), Serial SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Enhanced Small Disk Interface (ESDI), and Electronic Integrated Drive (IDE).

[0049] Memory interface 150 provides an interface between controller 100 and memory device 200, allowing controller 100 to control memory device 200 in response to requests from host device. Memory interface 150 can generate control signals for memory device 200 and process data under the control of control component 120. When memory device 200 is flash memory such as NAND flash memory, memory interface 150 can generate control signals for memory and process data under the control of control component 120.

[0050] Memory device 200 may include a memory cell array 210, control circuitry 220, voltage generation circuitry 230, row decoder 240, page buffer 250 (which may be in the form of a page buffer array), column decoder 260, and input / output (I / O) circuitry 270. The memory cell array 210 may include multiple memory blocks 211 capable of storing data. The voltage generation circuitry 230, row decoder 240, page buffer array 250, column decoder 260, and I / O circuitry 270 may form peripheral circuitry for the memory cell array 210. The peripheral circuitry may perform programming, reading, or erasing operations on the memory cell array 210. The control circuitry 220 may control the peripheral circuitry.

[0051] The voltage generation circuit 230 can generate operating voltages of various levels. For example, in an erase operation, the voltage generation circuit 230 can generate operating voltages of various levels, such as erase voltage and pass voltage.

[0052] The line decoder 240 can communicate electrically with the voltage generation circuit 230 and a plurality of memory blocks 211. The line decoder 240 can select at least one memory block among the plurality of memory blocks 211 in response to a line address generated by the control circuit 220, and transmit the operating voltage supplied from the voltage generation circuit 230 to the selected memory block.

[0053] Page buffer 250 can be accessed via bit line BL ( Figure 3 (As shown in the diagram) is connected to the memory cell array 210. The page buffer 250 can precharge the bit line BL with a positive voltage in response to a page buffer control signal generated by the control circuit 220, transfer data to and receive data from the selected memory block during programming and reading operations, or temporarily store the transferred data.

[0054] The column decoder 260 can transmit data to and receive data from the page buffer 250, and can also transmit data to and receive data from the input / output circuit 270.

[0055] Input / output circuit 270 can input from external devices (e.g., Figure 1 The controller 100 receives commands and addresses and transmits them to the control circuit 220, which transmits data from external devices to the column decoder 260, or outputs data from the column decoder 260 to external devices.

[0056] The control circuit 220 can control the peripheral circuits in response to commands and addresses.

[0057] Figure 3 This is a circuit diagram illustrating a memory block of a memory device according to an embodiment of the present invention. For example, Figure 3 The storage block can be Figure 2 Any one of the storage blocks 211 in the memory cell array 210 shown.

[0058] Reference Figure 3 Storage block 211 may include multiple word lines WL0 to WLn-1, drain select line DSL, and source select line SSL connected to line decoder 240. These lines may be arranged in parallel with multiple word lines between DSL and SSL.

[0059] The memory block 211 may further include multiple cell strings 221 respectively connected to bit lines BL0 to BLm-1. Each column of cell strings may include one or more drain-select transistors (DSTs) and one or more source-select transistors (SSTs). In the illustrated embodiment, each cell string has one DST and one SST. In the cell string, multiple memory cells or memory cell transistors MC0 to MCn-1 may be connected in series between the drain-select transistors (DSTs) and source-select transistors (SSTs). Each of the memory cells may be formed as a multi-level cell. For example, each of the memory cells may be formed as a single-level cell (SLC) storing 1 bit of data. Each of the memory cells may be formed as a multi-level cell (MLC) storing 2 bits of data. Each of the memory cells may be formed as a three-level cell (TLC) storing 3 bits of data. Each of the memory cells may be formed as a four-level cell (QLC) storing 4 bits of data.

[0060] The source of each SST in a cell string can be connected to the common source line CSL, and the drain of each DST can be connected to the corresponding bit line. The gate of an SST in a cell string can be connected to SSL, and the gate of a DST in a cell string can be connected to DSL. The gates of memory cells spanning cell strings can be connected to the corresponding word lines. That is, the gate of memory cell MC0 is connected to the corresponding word line WL0, the gate of memory cell MC1 is connected to the corresponding word line WL1, and so on. A group of memory cells connected to a specific word line can be called a physical page. Therefore, the number of physical pages in memory block 211 can correspond to the number of word lines.

[0061] Page buffer array 250 may include multiple page buffers 251 connected to bit lines BL0 to BLm-1. Page buffers 251 may operate in response to page buffer control signals. For example, during a read operation or a verification operation, page buffers 251 may temporarily store data received through bit lines BL0 to BLm-1 or sense the voltage or current of the bit lines.

[0062] In some embodiments, memory block 211 may include NAND flash memory cells. However, memory block 211 is not limited to this cell type, but may include NOR flash memory cells. Memory cell array 210 may be implemented as a hybrid flash memory combining two or more types of memory cells, or as a 1-NAND flash memory with the controller embedded within the memory chip.

[0063] Figure 4 This is a diagram illustrating the state distribution or programming voltage (PV) level distribution of different types of cells in a memory device according to an embodiment of the present invention.

[0064] Reference Figure 4 Each memory cell can be implemented using a specific type of cell, such as a single-level cell (SLC) for storing 1 bit of data, a multi-level cell (MLC) for storing 2 bits of data, a three-level cell (TLC) for storing 3 bits of data, or a four-level cell (QLC) for storing 4 bits of data. Typically, all memory cells in a particular memory device are of the same type, but this is not required.

[0065] An SLC can include two states, P0 and P1. P0 can represent the erase state, and P1 can represent the programmable state. Because an SLC can be set to one of two different states, each SLC can be programmed or store one bit according to a set encoding method. An MLC can include four states, P0, P1, P2, and P3. Among these states, P0 can represent the erase state, and P1 through P3 can represent the programmable state. Because an MLC can be set to one of four different states, each MLC can be programmed or store two bits according to a set encoding method. A TLC can include eight states, P0 through P7. Among these states, P0 can represent the erase state, and P1 through P7 can represent the programmable state. Because a TLC can be set to one of eight different states, each TLC can be programmed or store three bits according to a set encoding method. A QLC can include 16 states, P0 through P15. Among these states, P0 can represent the erase state, and P1 through P15 can represent the programmable state. Because a QLC can be set to one of sixteen different states, each QLC can be programmed or store four bits according to the set encoding method.

[0066] Re-reference Figure 2 and Figure 3 The memory device 200 may include a plurality of memory cells (e.g., NAND flash memory cells). The memory cells are arranged as follows: Figure 3The diagram shows an array arrangement of rows and columns. Cells in each row are connected to word lines (e.g., WL0), while cells in each column are connected to bit lines (e.g., BL0). These word lines and bit lines are used for read and write operations. During a write operation, when a word line is asserted, the data to be written ("1" or "0") is provided to the bit line. During a read operation, the word line is asserted again, and the threshold voltage for each cell can then be obtained from the bit line. Several pages can share a memory cell belonging to (i.e., connected to) the same word line. When the memory cell is implemented using MLC, the several pages include a most significant bit (MSB) page and a least significant bit (LSB) page. When the memory cell is implemented using TLC, the several pages include an MSB page, a middle significant bit (CSB) page, and an LSB page. When the memory cell is implemented using QLC, the several pages include an MSB page, a middle most significant bit (CMSB) page, a middle least significant bit (CLSB) page, and an LSB page. Encoding schemes (e.g., Gray encoding) can be used to program memory cells in order to increase the capacity of a memory system 10 such as an SSD.

[0067] Figure 5A This is a diagram illustrating an example of encoding for a multi-layer cell (MLC) according to an embodiment of the present invention.

[0068] Reference Figure 5A The MLC can be programmed using a specified type of encoding. The MLC can have four programming states: erase state E (or PV0) and first programming states PV1 through third programming states PV3. Erase state E (or PV0) can correspond to "11". First programming state PV1 can correspond to "10". Second programming state PV2 can correspond to "00". Third programming state PV3 can correspond to "01".

[0069] In MLC, such as Figure 5B As shown, there are two types of pages: LSB pages and MSB pages. One or two thresholds can be applied to retrieve data from the MLC. For MSB pages, the single threshold is VT1. VT1 distinguishes between the first programming state PV1 and the second programming state PV2. For LSB pages, the two thresholds are threshold VT0 and threshold VT2. VT0 distinguishes between the erase state E and the first programming state PV1. VT2 distinguishes between the second programming state PV2 and the third programming state PV3.

[0070] Figure 6A This is a diagram illustrating an example of Gray coding for a three-layer cell (TLC) according to an embodiment of the present invention.

[0071] Reference Figure 6AGray coding can be used to program a TLC. A TLC can have eight programming states, including an erase state E (or PV0) and first programming states PV1 through seventh programming states PV7. Eraser state E (or PV0) can correspond to "111". First programming state PV1 can correspond to "011". Second programming state PV2 can correspond to "001". Third programming state PV3 can correspond to "000". Fourth programming state PV4 can correspond to "010". Fifth programming state PV5 can correspond to "110". Sixth programming state PV6 can correspond to "100". Seventh programming state PV7 can correspond to "101".

[0072] In TLC, such as Figure 6B As shown, there are three types of pages: LSB pages, CSB pages, and MSB pages. Two or three thresholds can be applied to retrieve data from the TLC. For MSB pages, the two thresholds include threshold VT0, which distinguishes between erase state E and first programming state PV1, and threshold VT4, which distinguishes between fourth programming state PV4 and fifth programming state PV5. For CSB pages, the three thresholds include VT1, VT3, and VT5. VT1 distinguishes between first programming state PV1 and second programming state PV2. VT3 distinguishes between third programming state PV3 and fourth programming state PV4. VT5 distinguishes between fifth programming state PV5 and sixth programming state PV6. For LSB pages, the two thresholds include VT2 and VT6. VT2 distinguishes between second programming state PV2 and third programming state PV3. VT6 distinguishes between sixth programming state PV6 and seventh programming state PV7.

[0073] As described above, the host device 5 can be connected to the memory system 10 to configure the data processing system 2. Furthermore, the host device 5 can be configured as follows: Figure 7A The database storage system (or database system, database management system) shown. A database system can use files to store data. Each file can be a set of database records, and each record can be a set of fields.

[0074] Reference Figure 7A The host device 5 may include a database engine (or database storage engine) 710. The database storage engine 710 may be optimized for input and output (I / O) performance. A common I / O optimization method is to map database records to pages in a memory system (or storage device) (e.g., an SSD). Figure 7BAs shown, N database records can be mapped to N pages. In other words, the database records of the database table are aligned with pages (e.g., NAND pages) in the SSD's storage device. Aligning or mapping database record fields to a single page allows access to all record fields within that page, eliminating the need to read multiple NAND pages to reconstruct a single database record. The arrangement of database attributes within each NAND page can be implemented using various methods. Mapping can be done in a way that minimizes the storage overhead for each stored data record. Two examples of this file organization include the N-ary Storage Model (NSM) and the Peripartition Attribute (PAX). Both database storage file formats are aligned with SSD pages. That is, pages can be in NSM or PAX format.

[0075] Database storage engine 710 can utilize specialized indexed data structures for efficient database record retrieval. Improved data retrieval speed can be achieved by leveraging indexed data structures, such as database column indexes. A database index is a data structure that improves the speed of data retrieval operations on a database table at the cost of additional write and storage space for maintaining the index data structure. Indexes can be used to quickly locate data without searching every row in the database table every time it is accessed. Indexes can be created using one or more columns of a database table, thus providing a foundation for fast random lookups and efficient access to ordered records.

[0076] Indexing all database columns may not always be feasible or necessary. When retrieving database entries without indexing columns, a full search should be performed across all database columns. This means that a subset of database table entries mapped to an SSD page will be read from the SSD into local cache memory, and that subset of database table entries will be searched for entries matching the lookup constraints. If no record matching the lookup constraints is found within the SSD page, the entire page is discarded from memory, and the freed-up memory is reclaimed for the newly read page.

[0077] While database indexes significantly improve data retrieval, column indexing should be done prudently. Redundant indexes degrade performance due to the additional storage space required for index maintenance, continuous index swapping between volatile memory and storage devices (when the index cannot be fully utilized by main memory), and increased database operation runtime. Database operation runtime can increase due to the extra operations required for index maintenance during update, delete, and insert entries. Furthermore, index maintenance associated with additional writes to persistent storage media can wear down storage devices (e.g., NAND). Therefore, not all columns should be indexed.

[0078] Therefore, if database record retrieval is constrained by unindexed columns, a full search should be performed on those unindexed columns. A full column search means reading the database table into the memory of the database storage engine 710. The database storage engine 710 can then search for records matching the query criteria within the pages loaded into memory. Pages that do not contain records matching the search criteria can be discarded from memory. A full search can be a resource-intensive task that consumes both CPU and volatile memory. The speed of a full search by the database storage engine 710 may be constrained by the availability of temporary memory used to store the read NAND pages and the CPU time spent on the full column search.

[0079] Therefore, embodiments of the present invention provide a system and method for accelerating data retrieval in a database storage system. Embodiments may provide an embedded, reconfigurable SSD hardware accelerator capable of enabling in-sSD database page filtering to find pages that meet column-wide search criteria. Thus, embodiments can offload host resources (e.g., RAM and CPU resources) and speed up the entire data retrieval process.

[0080] Figure 8 This is a diagram illustrating a database storage system according to an embodiment of the present invention.

[0081] Reference Figure 8 The database storage system may include a host device 5 and a memory system (or storage device), the memory system being coupled to the host device 5 and including a controller 100 and a memory device 200. The memory system may be coupled to the host device 5 and may communicate with the host device 5 via one or more of various communication standards or interfaces (or protocols). In some embodiments, the memory system may be a solid-state drive (SSD). In this embodiment, the controller 100 may be an SSD controller, and the memory device 200 may be NAND flash memory.

[0082] The host device 5 may include a data storage engine 710, an input and output (I / O) controller 720, and a memory (i.e., host memory) 730. The I / O controller 720 can control the interface with the controller 100 of the memory system.

[0083] The controller 100 may include a host interface layer (HIL) 810, a flash translation layer (FTL) and a flash interface layer (FIL) 820, and memory (i.e., SSD controller memory) 830. HIL 810 may correspond to... Figure 2 The host interface 140 in the FTL can correspond to... Figure 2 Control component 120 in the FTL. FTL can correspond to... Figure 2The memory interface 150 in the memory 830 can correspond to... Figure 2 Storage device 110 in the middle.

[0084] Furthermore, the controller 100 may include a page processing accelerator (PPA) 840 and a cache memory 850 within the PPA. The operation and function of the PPA 840 and the cache memory 850 are described in detail below.

[0085] Database storage engine 710 can process pages loaded from NAND memory device 200 into memory 730. Page processing can be a computationally intensive task performed by a general-purpose CPU. When a searched database record is not found in a loaded page, the entire page can be discarded. In some embodiments, the SSD's initial filtering includes pages containing records that match database search criteria (e.g., pages with NSM or PAX formats). In this way, the SSD prevents database storage engine 710 from processing pages that do not contain records that meet the database search criteria. According to the SSD of the present invention, namely a database search hardware-accelerated SSD, CPU time and memory consumption of database storage engine 710 can be saved by delegating the corresponding page processing and filtering operations to a dedicated reconfigurable SSD page processing accelerator (PPA) 840.

[0086] The PPA 840 can be integrated into the data path between the HIL 810 and FTL 820. The page processing hardware accelerator 840 can process pages read from NAND 200 by the FIL 820 and filter received pages according to a column-wide search criterion. Furthermore, the PPA 840 can signal to the HIL 810 whether the processed page should be transmitted to the host device 5. Figure 8 In the example shown, a single SSD may include a single PPA 840. However, a single SSD may include a large number of independent page processing accelerators to achieve higher processing parallelism, which makes a large number of independent page processing accelerators more efficient than a general-purpose central processing unit (CPU) for algorithms that process large blocks of data in parallel.

[0087] HIL 810 supports configuration of PPA 840 and custom read commands via the host interface protocol. Before performing a full column search, database storage engine 710 can configure PPA 840 to correspond to the database page storage format. PPA 840 can be configured via predefined commands (e.g., SSD vendor-specific commands). After configuring the PPA page format, a full column search task on the database table can be submitted using an SSD vendor-specific read command known as a filtered read command (FRC).

[0088] In some embodiments, the filtered read command may include the following parameters: full column search criteria (or constraints, conditions), a set of page identifiers (IDs) to be searched, and a destination address of a memory in the host device for transmitting pages that include records matching the full column search criteria.

[0089] The host device 5 can issue a filtered read command to the SSD controller 100, requesting the SSD controller 100 to read a specific page from the NAND memory device 200. In response, the PPA 840 of the SSD controller 100 can filter the pages to be read according to a column-full search criterion. The SSD controller 100 can transfer one or more pages containing database entries that match the column-full search criteria to a destination location (address) in the host memory 730. NAND pages that do not contain database records that meet the search criteria can be discarded from the SSD controller memory 830 without being transferred to the host device 5. The completion of the column-full search task of the PPA 840 can be transmitted to the host device 5 via a setting command called a filtered read completion status command.

[0090] Figure 9 This is a diagram illustrating a page of a storage device in a database storage system that maps data records to data records according to an embodiment of the present invention.

[0091] Reference Figure 9 Database storage systems can store records in files, which are divided into fixed-size units called pages. Pages in a database storage system can be aligned within NAND pages. For example, a record corresponding to logical page Page0 can be mapped to physical page Page0 of storage block Y, and a record corresponding to logical page Page1 can be mapped to physical page Page1 of storage block X. Pages can be organized in a way that minimizes the storage overhead (operations and storage space) for each stored data record. Examples of such page organization, as mentioned above, include the N-ary storage model (NSM) and the cross-partition attribute (PAX) format.

[0092] Return to reference Figure 8The host interface layer 810 can support the configuration and custom read commands for the Page Processing Accelerator (PPA) 840, i.e., filtered read commands. The PPA 840 can be adapted to the appropriate page storage format (e.g., NSM or PAX) using SSD vendor-specific commands. These commands can write to and read from the configured PPA address space. The configuration of the PPA 840 is flexible enough to reconfigure it to a desired page storage layout. The page storage layout can be consistent throughout the database storage system; therefore, the PPA 840 can be configured only once. After the initial PPA page layout configuration is complete, a full column search task can be submitted without additional PPA configuration overhead. The full column search task can be submitted to the PPA 840 using SSD vendor-specific read commands (i.e., filtered read commands). The PPA 840 can read NAND pages, parse them according to the page format (or layout), deserialize record fields, and determine records that meet the full column search criteria based on the filtered read commands. After the filtered read command is processed, the SSD controller 100 can notify the host device 5 by sending a corresponding completion status command.

[0093] Figure 10 This is a flowchart illustrating a method 1000 for operating a memory system to accelerate database searches in a database storage system according to an embodiment of the present invention.

[0094] Reference Figure 10 Method 1000 can be comprised of, including Figure 8 The SSD controller 100 of the PPA 840 is used for control. In operation 1010, the SSD controller 100 can receive a configuration command (e.g., a filtered read command) from the host device 5. In operation 1020, the SSD controller 100 can read several pages from a plurality of pages of the memory device 200 in response to the filtered read command. In operation 1030, the SSD controller 100 can filter a specific page from the plurality of pages based on a column full search condition included in the configuration command. The filtered pages can include entries that satisfy the column full search condition. In operation 1040, the SSD controller 100 can transmit information about the filtered pages to the host device 200.

[0095] Figure 11 The diagram illustrates the sequence of operations for a memory system according to an embodiment of the invention. This sequence can be controlled by an SSD controller 100 including a PPA 840.

[0096] Reference Figure 11The host device 5 can transmit (issue) filtered read commands to the SSD controller 100 (1102). The HIL 810 can receive and identify the filtered read commands and add them to the run queue (not shown). The HIL 810 can allocate resources for running the filtered read commands and start running the filtered read commands (1104).

[0097] FIL 820 can read pages from NAND memory device 200 and write the read pages to SSD controller memory 830 (1106, 1108, 1110) based on filtered read commands. The read pages can correspond to the page ID specified in the filtered read command. FIL 820 can then notify PPA 840 that the corresponding page has been transferred to memory 830 and is ready to be processed (1112).

[0098] PPA 840 can retrieve task parameters corresponding to the page ID read by FIL 820. In some embodiments, the task parameters include the configuration of PPA 840 and column full search conditions. In other words, PPA 840 can transmit a command (1114) to HIL 810 for retrieving task parameters, and HIL 810 can return the task parameters to PPA 840 (1116).

[0099] PPA840 can read pages from SSD controller memory 830 and find records (1118) that match (or satisfy the column full search constraint) within the read pages.

[0100] PPA 840 can transmit the ID (1120) of the page in which the record entries satisfy the column full search condition to HIL 810. HIL 810 can then transfer the page transmitted by PPA 840, i.e., the page in which the record entries satisfy the column full search condition, from SSD controller memory 830 to host device 5 (1122). After the transfer, HIL 810 can release the memory area of ​​SSD controller memory 830 allocated to that page.

[0101] The same operation can be performed on another page. That is, operations 1152 to 1166, corresponding to operations 1108 to 1122, can be performed. These operations can be performed until all N pages have been processed. These operations are performed based on a page read from the NAND memory device 200 in response to each read access of FIL 820.

[0102] Optionally, in response to each read access of FIL 820, two or more pages are read from the NAND memory device 200. This embodiment can be represented by the following equation: Where N is the total number of pages to be read, K represents the number of FIL accesses to NAND required to read N pages, and f i This indicates the number of pages read from NAND during each FIL read access.

[0103] As described above, the SSD controller 100 can read several pages based on a filtered read command, filtering the pages to include records that satisfy the full column search criteria, and then transmit the filtered pages to the host device 5. The PPA 840 can discard the remaining pages among the filtered pages. The HIL 810 can transmit pages containing database entries matching the search criteria to the host memory 730 based on the destination address in the filtered read command. While the pages based on the filtered read command are being processed, the HIL 810 can send a command completion notification and / or command completion status (1168) to the host device 5.

[0104] Reference Figure 12 and Figure 13 Describe an example of a database storage system.

[0105] Figure 12 This is a diagram illustrating a database storage system according to an embodiment of the present invention.

[0106] Reference Figure 12 Database storage systems may include, for example, Figure 8 The host device 5 shown includes a memory system comprising an SSD controller 100 and a memory device 200. The memory system may be a hardware-accelerated database search SSD with high-speed non-volatile memory (NVMe) via a high-speed peripheral component interconnect (PCIe) interface. That is, the host interface layer (HIL) 810 of the SSD controller 100 may support NVMe over PCIe. On the host device 5 side, the database storage system may be connected to the SSD controller 100 via an I / O controller 720, which is an NVMe I / O controller via a PCIe interface. The database storage engine 710 may issue NVMe commands to the SSD controller 100. The SSD may support vendor-specific commands, such as setting / getting PPA configuration attributes and filtered read commands. The database storage system may be aware of the database files mapped to the underlying SSD pages (i.e., NAND pages).

[0107] Before issuing a filtered read command, the database storage engine 710 can configure the page processing accelerator (PPA) 840 to the database page layout format used. The database storage system can use page layout formats such as NSM and PAX. PAX format pages, such as... Figure 13 As shown. Below is a brief description of the PAX format layout. A more detailed description of PAX can be found in the following literature: Anastassia Ailamaki, David J. DeWitt and Mark D. Hill, “DataPage Layouts for Relational Databases on Deep Memory Hierarchies”, VLDB 11, 198-215 (2002), which is incorporated herein by reference in its entirety.

[0108] PAX can divide each page into several mini-pages (e.g., n mini-pages) to store relations with a degree of n (i.e., n attributes). The value of the first attribute is then stored in the first mini-page, the value of the second attribute in the second mini-page, and so on. Each page begins with a header containing an offset from the beginning of each mini-page. This header information is distributed across the entire mini-page.

[0109] Reference Figure 13 A PAX page may include a page header 1310 and several minipages 1320 to 1340. The minipages may include two F minipages 1320 and 1340 and one V minipage 1330. Fixed-length attribute values ​​may be stored in the F minipages 1320 and 1340. At the end of each F minipage, there is an existence bit vector for one entry per record, representing nullable values ​​for nullable attributes. Variable-length attribute values ​​may be stored in the V minipage 1330. The V minipage 1330 may be slotted, having pointers to the ends of each value. Null values ​​may be represented by null pointers.

[0110] Each newly allocated page may include a page header 1310 and multiple minipages 1320 to 1340 of equal degree to the relation. The page header 1310 may include the number of attributes, attribute size (for fixed-length attributes), offset from the beginning of the minipage, the current number of records on the page, and the total available space. Figure 13 The example of the PAX page corresponds to the employee's service hours in Table 1 below:

[0111] Table 1:

[0112] Employee ID Name Service Hours 5621 Mike 6 1452 Isabella 8

[0113] Table 1 shows the deserialization process... Figure 13The PAX page already contains two records. There are two F mini-pages, one at 1320 for the employee ID attribute and the other at 1340 for the length of the employment attribute. The name attribute is a variable-length string, so it is stored in V mini-page 1330. At the end of each V mini-page, there is an offset to the end of each variable-length value.

[0114] Return to reference Figure 12 The PPA 840 can be configured to properly deserialize PAX pages. After initial configuration of the PPA 840 for accelerating database searches, the SSD may be ready to receive and run full column search tasks. Full column search tasks can be submitted via NVMe vendor-defined commands known as filtered read commands. This can be based on... Figure 11 The FRC runtime process is used to execute the batch PPA page processing flow.

[0115] The PPA 840 can process a single page using the following workflow:

[0116] (1) For the next page to be processed, PPA 840 can retrieve the full column search task parameters from the NVMe command submission queue of HIL 810.

[0117] (2) After retrieving the full column search task parameters, the PPA 840 can read the page into the internal cache memory 850.

[0118] (3) PPA 840 can deserialize rows and columns within the currently processed page based on page header information and PPA configuration. The page header may include information sufficient to navigate between table rows and columns within the page.

[0119] (4) The deserialized rows and columns can be stored in the PPA cache memory 850. The PPA 840 can perform searches on the table columns constrained in the search query. The PPA 840 can quickly access the deserialized table data located in the cache memory 850 and perform comparison operations on each column entry according to the column data type.

[0120] (5) Table records that meet the search criteria can be copied to an area of ​​the cache memory 850 reserved for storing search results. The PPA 840 can notify the HIL 810 after each page search task is completed. The notification may include information about the records found within the page that meet the search criteria, and the location of the records found in the cache memory 850. If no record is found, the notification may include a corresponding status code.

[0121] Based on the notification status received from PPA 840, HIL 810 can send a page containing records that meet the search criteria to host device 5. After completing the search operation on all pages according to the filtered read command, HIL 810 can issue an FRC NVMe command completion status to notify host device 5 that FRC is complete. At this point, the SSD can return only the page containing records that meet the search criteria to the database storage system, i.e., to database storage engine 710.

[0122] Therefore, embodiments of the present invention provide a system for accelerating data retrieval in a database storage system. The storage system (i.e., SSD) can read several pages based on filtered read commands, filtering the pages to include records that satisfy the full column search condition, and then transmit the filtered pages to the host device. Thus, embodiments of the present invention can free up resources (i.e., CPU and memory) of the database storage system (i.e., the host device) and accelerate the full column search.

[0123] While the foregoing embodiments have been shown and described in considerable detail for clarity and understanding, the invention is not limited to the details provided. As will be understood by those skilled in the art based on the foregoing disclosure, many alternative ways of carrying out the invention exist. Therefore, the disclosed embodiments are illustrative and not restrictive. The invention is intended to cover all modifications falling within the scope of the claims. Furthermore, embodiments may be combined to form additional embodiments.

Claims

1. A system comprising: a host device including a database storage engine; and a memory system including a controller and a memory device, the memory device including a plurality of pages storing a number of records, wherein the controller includes a page processing accelerator to: read, in response to a filtered read command, a number of pages of the plurality of pages; filter pages among the number of pages based on a column- wise search condition, filtered pages including entries satisfying the column- wise search condition; and transfer information about the filtered pages to the host device.

2. The system of claim 1, wherein the filtered read command includes the column- wise search condition and a set of page identifiers (IDs) corresponding to the number of pages for searching.

3. The system of claim 2, wherein the host device further includes a host memory, and the filtered read command further includes a destination address of the host memory to write data of the filtered pages.

4. The system of claim 1, wherein the controller sends a completion notification to the host device after completing the transfer of data of the filtered pages.

5. The system of claim 1, wherein the controller configures the page processing accelerator in response to the filtered read command.

6. The system of claim 1, wherein the controller includes: a host interface layer (HIL) to interface with the host device; a flash interface layer (FIL) to interface with the memory device; and a controller memory to store the number of pages.

7. The system of claim 1, wherein each of the plurality of pages stores one or more records among the number of records in a partition- across-x (PAX) format.

8. The system of claim 7, wherein the page processing accelerator de-serializes rows and columns within each of the number of pages according to page header information to generate a de-serialized table.

9. The system of claim 8, wherein the page processing accelerator determines whether each of column entries of the de-serialized table satisfies the column- wise search condition.

10. The system of claim 9, wherein the controller transfers information about the filtered pages to the host device, each filtered page including one or more column entries satisfying the column- wise search condition.

11. A method for operating a system including a host device and a memory system, the host device including a database storage engine, the memory system including a controller and a memory device, the memory device including a plurality of pages storing a number of records, the method comprising: configuring, in the controller, a page processing accelerator; reading, by the page processing accelerator, a number of pages of the plurality of pages in response to a filtered read command; filtering, by the page processing accelerator, pages among the number of pages based on a column- wise search condition, filtered pages including entries satisfying the column- wise search condition; and transferring, by the controller, information about the filtered pages to the host device. ​ ​ ​ transmitting, by the controller, information about the filtered pages to the host device.

12. The method of claim 11, wherein the filtered read command includes the column- wise search condition and a set of page identifiers (IDs) corresponding to the number of pages for searching.

13. The method of claim 12, wherein the filtered read command further includes a destination address of a host memory in the host device to write data of the filtered pages.

14. The method of claim 11, further comprising: sending a completion notification to the host device after completion of the transmission of data of the filtered pages.

15. The method of claim 11, wherein the page processing accelerator is configured in response to the filtered read command.

16. The method of claim 11, wherein the controller includes: a host interface layer (HIL) to interface with the host device; a flash interface layer (FIL) to interface with the memory device; and a controller memory to store the number of pages.

17. The method of claim 11, wherein each of the number of pages stores one or more records among the number of records in a partitioned attribute eXtended (PAX) format.

18. The method of claim 17, wherein filtering the pages among the number of pages based on the column-wise search condition includes: deserializing rows and columns within each of the number of pages according to page header information to generate a deserialized table.

19. The method of claim 18, wherein filtering the pages among the number of pages based on the column-wise search condition includes: determining whether each of column entries of the deserialized table satisfies the column-wise search condition.

20. The method of claim 19, wherein transmitting information about the filtered pages includes: transmitting information about the filtered pages to the host device, each filtered page including one or more column entries that satisfy the column-wise search condition. ​

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