A data lookup method, device and readable storage medium based on a lookup table

Abstract

Embodiments of the present application disclose a data lookup method and device based on a lookup table and a readable storage medium. Embodiments of the present application acquire an address lookup table, the address lookup table comprising a plurality of indexes; determine a first index in the plurality of indexes of the address lookup table, read candidate data corresponding to the first index from a memory to a first cache according to a memory address of the first index, the candidate data being data corresponding to an index range of the first index; determine first target data corresponding to the first index in the candidate data; determine an index set according to a position of the first index in the address lookup table, and read second target data corresponding to a second index in the candidate data of the first cache in response to a memory address of the second index being located in the index range. Through the above method, candidate data corresponding to a plurality of indexes can be read at a time, the number of times of accessing the memory when searching for target data is reduced, and the efficiency of searching for target data is improved.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and more specifically to a data lookup method, apparatus, and readable storage medium based on a lookup table. Background Technology

[0002] Look-up tables (LUTs) are a common data retrieval method in computer technology. Specifically, a data item corresponding to an index is read from memory based on an index, and then the corresponding data item is written to a destination address. In the above process, only one-to-one lookups can be performed. If it is necessary to find data corresponding to multiple indexes, multiple lookups are required. For example, to find data corresponding to 16 indexes, 16 lookups are required. Each lookup requires accessing memory, resulting in low lookup efficiency.

[0003] In summary, reducing the number of memory accesses during data retrieval and improving data retrieval efficiency are problems that need to be solved. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a data lookup method, apparatus and readable storage medium based on a lookup table, which can reduce the number of memory accesses during data lookup and improve data lookup efficiency.

[0005] In a first aspect, embodiments of the present invention provide a data lookup method based on a lookup table. The method includes: obtaining an address lookup table, the address lookup table including multiple indexes; determining a first index among the multiple indexes of the address lookup table, wherein the first index is an unlabeled index in the address lookup table; reading candidate data from memory into a first cache according to the memory address of the first index, the candidate data being data corresponding to the index range of the first index; determining a first target data corresponding to the first index among the candidate data; determining an index set according to the position of the first index in the address lookup table, wherein the index set includes a predetermined number of indexes among the multiple indexes of the address lookup table; and reading a second target data corresponding to the second index from the candidate data in the first cache in response to a memory address of a second index being located within the index range, wherein the second index is an unlabeled index in the index set.

[0006] Optionally, the method further includes:

[0007] Based on the position of the first index in the address lookup table, the first target data is saved to the first position of the second cache, wherein the first position corresponds to the position of the first index in the address lookup table;

[0008] Based on the position of the second index in the address lookup table, the second target data is saved to the second location of the second cache, wherein the second location corresponds to the position of the second index in the address lookup table.

[0009] Optionally, in response to the fact that the set amount of target data is stored in the first cache, the method further includes:

[0010] Write the set amount of target data to the corresponding destination address.

[0011] Optionally, the method further includes:

[0012] The first index and the second index are labeled, and the label is used to indicate that the target data corresponding to the index has been obtained.

[0013] Optionally, the method further includes:

[0014] A new first index is determined among the multiple indexes in the address lookup table, and the above steps are performed until all the multiple indexes in the address lookup table are marked.

[0015] Optionally, the index range corresponds to the bit width of the memory.

[0016] Optionally, the address lookup table is a matrix that includes the plurality of indexes.

[0017] Optionally, the method further includes:

[0018] When the number of indices in each row of the matrix is ​​less than the set number, the indices included in the index set are located in the same row of the matrix.

[0019] Secondly, embodiments of the present invention provide a data lookup device based on a lookup table.

[0020] The acquisition unit is used to acquire an address lookup table, which includes multiple indexes.

[0021] The acquisition unit is further configured to determine a first index among the plurality of indexes in the address lookup table, wherein the first index is an unmarked index in the address lookup table;

[0022] The reading unit is used to read candidate data from memory into the first cache according to the memory address of the first index, wherein the candidate data is the data corresponding to the index range of the first index;

[0023] A determining unit is configured to determine, from the candidate data, the first target data corresponding to the first index;

[0024] The acquisition unit is further configured to determine an index set based on the position of the first index in the address lookup table, wherein the index set includes a set number of indexes among the plurality of indexes in the address lookup table;

[0025] The determining unit is further configured to, in response to the memory address of the second index being located within the index range, read the second target data corresponding to the second index from the candidate data in the first cache, wherein the second index is an unlabeled index in the index set.

[0026] Optionally, the device further includes a caching unit, which saves the first target data to a first location of the second cache according to the position of the first index in the address lookup table, wherein the first location corresponds to the position of the first index in the address lookup table; and saves the second target data to a second location of the second cache according to the position of the second index in the address lookup table, wherein the second location corresponds to the position of the second index in the address lookup table.

[0027] Optionally, the device further includes a writing unit, and in response to the storage of the predetermined amount of target data in the first cache, the method further includes:

[0028] Write the set amount of target data to the corresponding destination address.

[0029] Optionally, the device further includes a labeling unit for labeling the first index and the second index, wherein the labeling is used to indicate that the target data corresponding to the index has been acquired.

[0030] Optionally, the acquisition unit is further configured to determine a new first index among the plurality of indexes in the address lookup table, and perform the above steps until all the plurality of indexes in the address lookup table are marked.

[0031] Optionally, the index range corresponds to the bit width of the memory.

[0032] Optionally, the address lookup table is a matrix that includes the plurality of indexes.

[0033] Optionally, in response to the number of indices in each row of the matrix being less than the set number, the indices included in the index set are located in the same row of the matrix.

[0034] Thirdly, embodiments of the present invention provide a computer program instruction that, when executed by a processor, implements the method as described in the first aspect or any one of the possible methods described in the first aspect.

[0035] Fourthly, embodiments of the present invention provide a computer-readable storage medium having stored thereon computer program instructions that, when executed by a processor, implement the method as described in the first aspect or any one of the possibilities of the first aspect.

[0036] Fifthly, embodiments of the present invention provide a chip including a memory and a processing core, the memory being used to store one or more computer program instructions, wherein the one or more computer program instructions are executed by the processing core to implement the method as described in the first aspect or any one of the possible methods of the first aspect.

[0037] Sixthly, embodiments of the present invention provide a board card, the board card including the chip described in the fifth aspect.

[0038] In a seventh aspect, embodiments of the present invention provide a server, the server including the board from the sixth aspect.

[0039] This invention provides an address lookup table, which includes multiple indexes. A first index is determined from among the multiple indexes in the address lookup table, wherein the first index is an unlabeled index in the address lookup table. Candidate data is read from memory into a first cache based on the memory address of the first index, wherein the candidate data is data corresponding to the index range of the first index. A first target data corresponding to the first index is determined from the candidate data. An index set is determined based on the position of the first index in the address lookup table, wherein the index set includes a predetermined number of indexes from among the multiple indexes in the address lookup table. In response to a second index whose memory address is within the index range, second target data corresponding to the second index is read from the candidate data in the first cache, wherein the second index is an unlabeled index in the index set. Through this method, candidate data corresponding to multiple indexes can be read from a first storage location at once and temporarily stored in a cache. When searching for target data corresponding to the second index, it is not necessary to access memory again; the target data corresponding to the second index can be directly obtained from the candidate data in the cache. This reduces the number of memory accesses during target data search and improves the efficiency of target data search. Attached Figure Description

[0040] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0041] Figure 1 This is a schematic diagram of an index matrix and a destination matrix according to an embodiment of the present invention;

[0042] Figure 2This is a flowchart of a data lookup method based on a lookup table according to an embodiment of the present invention;

[0043] Figure 3 This is a schematic diagram of an index matrix according to an embodiment of the present invention;

[0044] Figure 4 This is a schematic diagram of a data list according to an embodiment of the present invention;

[0045] Figure 5 This is a flowchart of a data lookup method based on a lookup table according to an embodiment of the present invention;

[0046] Figure 6 This is a schematic diagram of a data list according to an embodiment of the present invention;

[0047] Figure 7 This is a schematic diagram of a data list according to an embodiment of the present invention;

[0048] Figure 8 This is a schematic diagram of a data list according to an embodiment of the present invention;

[0049] Figure 9 This is a flowchart of a data lookup method based on a lookup table according to an embodiment of the present invention;

[0050] Figure 10 This is a schematic diagram of an index matrix according to an embodiment of the present invention;

[0051] Figure 11 This is a flowchart of a data lookup method based on a lookup table according to an embodiment of the present invention;

[0052] Figure 12 This is a schematic diagram of a destination address according to an embodiment of the present invention;

[0053] Figure 13 This is a schematic diagram of a data relationship according to an embodiment of the present invention;

[0054] Figure 14 This is a schematic diagram of a data list according to an embodiment of the present invention;

[0055] Figure 15 This is a schematic diagram of an index matrix according to an embodiment of the present invention;

[0056] Figure 16 This is a schematic diagram of an address list according to an embodiment of the present invention;

[0057] Figure 17 This is a schematic diagram of a data list according to an embodiment of the present invention;

[0058] Figure 18 This is a schematic diagram of a data list according to an embodiment of the present invention;

[0059] Figure 19This is a schematic diagram of a data list according to an embodiment of the present invention;

[0060] Figure 20 This is a schematic diagram of a data list according to an embodiment of the present invention;

[0061] Figure 21 This is a schematic diagram of a data lookup device based on a lookup table according to an embodiment of the present invention. Detailed Implementation

[0062] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0063] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0064] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".

[0065] In the description disclosed in this invention, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description disclosed in this invention, unless otherwise stated, "a plurality of" means two or more.

[0066] Typically, in existing technologies, a lookup table (LUT) reads data corresponding to an index from memory based on an index, and then writes that data to a destination address, such as... Figure 1 As shown, assuming the index is matrix M1, which includes multiple indices such as a11, a12...1N, a21, a22...2N, etc., data corresponding to any index in M1 is read from memory and written to the destination address. Specifically, data c11 is read from memory based on index a11 and written to the corresponding position in the destination matrix M. Since only one-to-one lookup is possible, if data corresponding to multiple indices in matrix M1 needs to be searched, multiple reads from memory are required, resulting in a long execution cycle and low search efficiency.

[0067] In this embodiment of the invention, in order to reduce the number of memory accesses during data lookup and improve data lookup efficiency, a data lookup method based on a lookup table is proposed. This method can read candidate data corresponding to multiple indices from a first storage location at once and temporarily store the candidate data in a cache. When looking up the target data corresponding to the second index, it is not necessary to access memory again. The target data corresponding to the second index can be obtained directly from the candidate data in the cache, thereby reducing the number of memory accesses during target data lookup and improving target data lookup efficiency.

[0068] Figure 2 This is a flowchart of a data lookup method based on a lookup table according to an embodiment of the present invention. Figure 2 As shown, the specific steps include the following:

[0069] Step S200: Obtain the address lookup table, which includes multiple indexes.

[0070] Specifically, the address lookup table is as follows: Figure 3 As shown, there is a 4x4 matrix N1 containing 16 elements, each representing an index. These 16 elements are src1, src2, src3, src4, src5, src6, src7, src8, src9, src10, src11, src12, src13, src14, src15, and src16. The value of each element is a memory address. The memory addresses corresponding to each row index can be consecutive or non-consecutive. For example, the value of src1 is 0, meaning the memory address of src1 is 0; the value of src3 is e, meaning the memory address of src3 is e.

[0071] Step S201: Determine a first index among the plurality of indexes in the address lookup table, wherein the first index is an unmarked index in the address lookup table.

[0072] Specifically, an unlabeled index indicates that the target data corresponding to the index has not been retrieved, that is, the target data corresponding to the index has not yet been searched in memory.

[0073] In one possible implementation, the first index src1 is obtained in the matrix N1.

[0074] Step S202: Read candidate data from memory into the first cache according to the memory address of the first index, wherein the candidate data is the data corresponding to the index range of the first index.

[0075] In one possible implementation, memory addresses and data are stored in a list in the memory, with each address corresponding to a specific data location. For example, the list is as follows: Figure 4As shown, assuming memory addresses are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e, f, g, h, etc., where the data corresponding to memory address 0 is d0, memory address 1 is d1, memory address 2 is d2, memory address 3 is d3, memory address 4 is d4, memory address 5 is d5, memory address 6 is d6, memory address 7 is d7, memory address 8 is d8, memory address 9 is d9, memory address a is d10, memory address b is d11, memory address c is d12, memory address d is d13, memory address e is d14, memory address f is d15, memory address g is d16, memory address h is d17, and so on. Further details are omitted here.

[0076] For example, the memory address of the first index src1 is 0. The candidate data corresponding to the index range 0 to f of memory address 0 is retrieved from memory and stored in the first cache. That is, the 16 data d0 to d15 corresponding to the index range 0 to f are all retrieved as cache data and stored in the first cache.

[0077] The index range includes 16 memory addresses. Specifically, the number of index ranges is determined based on the memory bit width, and is not limited here. The larger the index range corresponding to each index, the fewer times it needs to be retrieved. The more contiguous the memory addresses corresponding to the indexes in the address lookup table, the more target data each index range includes. The specific reasons will be explained in subsequent detailed embodiments.

[0078] Step S203: Determine the first target data corresponding to the first index from the candidate data.

[0079] Specifically, the candidate data includes d0 to d15, the memory address of the first index src1 is 0, and the corresponding candidate data d0 is the first target data d0.

[0080] Step S204: Determine an index set based on the position of the first index in the address lookup table, wherein the index set includes a set number of indexes among the plurality of indexes in the address lookup table;

[0081] In this embodiment of the invention, by determining an index set, after obtaining candidate data for the index range corresponding to the first index, it is possible to determine at once whether the memory addresses of multiple indexes in the index set are within the index range corresponding to the first index. The index set generally includes a first index and multiple other indexes different from the first index. In an optional embodiment, these other multiple indexes are multiple consecutive indexes ordered after the first index in the address lookup table, or, these other multiple indexes are multiple consecutive indexes located before and after the first index in the address lookup table. Specifically, assuming the first index is src1, such as... Figure 3 In the matrix N1 shown, the other three indices in the same row as src1 are src2, src3, and src4. Therefore, the index set determined based on the first index src1 is {src1, src2, src3, src4}. In another embodiment, assuming the first index is src3, as... Figure 3 In the matrix N1 shown, src3 is src1, src2 and src4, src5 in the two ranges before and after src3 in matrix N1. Therefore, the index set determined by the first index src3 is {src1, src2, src3, src4, src5}.

[0082] Step S205: In response to the memory address of the second index being located within the index range, read the second target data corresponding to the second index from the candidate data in the first cache, wherein the second index is an unlabeled index in the index set.

[0083] In one possible implementation, after obtaining candidate data within the index range corresponding to the first index, it is determined whether an index exists in the index set whose memory address is within the index range corresponding to the first index. If such an index exists and is unmarked, it is designated as a second index, and the data of this second index can be directly retrieved from the candidate data without needing to read it from memory. Furthermore, there can be multiple second indices, meaning that the memory addresses of multiple indices in the index set are within the index range corresponding to the first index. According to embodiments of the present invention, multiple target data can be obtained at once through a single data read operation.

[0084] For example, the memory address of the first index src1 is 0, and the index range corresponding to the first index is from 0 to f. Assuming that the memory address e of src3 in the index set is in the index range from 0 to f, then src3 is the second index. The second target data d14 corresponding to the second index is read from the cached candidate data d0 to d15.

[0085] In this embodiment of the invention, based on the address lookup table, candidate data corresponding to the index range of the first index can be read from memory at once, and the candidate data can be temporarily stored in the cache. When searching for the target data corresponding to the second index according to the index set, it is not necessary to access memory again. The target data corresponding to the second index can be obtained directly from the candidate data in the cache. This reduces the number of times memory is accessed when searching for target data and improves the efficiency of target data search.

[0086] In this embodiment of the invention, the memory address exhibits spatial locality, meaning that if the data corresponding to a memory address is the target data, then the data corresponding to memory addresses within a certain range before and after that memory address is more likely to be the target data.

[0087] In one possible implementation, after step S205 described above, step S206 is included, as follows: Figure 5 As shown, Figure 5 This is a flowchart of a data lookup method based on a lookup table according to an embodiment of the present invention.

[0088] Step S206: According to the position of the first index in the address lookup table, save the first target data to the first position of the second cache, wherein the first position corresponds to the position of the first index in the address lookup table; according to the position of the second index in the address lookup table, save the second target data to the second position of the second cache, wherein the second position corresponds to the position of the second index in the address lookup table.

[0089] Specifically, such as Figure 6 As shown, it is necessary to find the target data corresponding to the index of the first row in matrix N1. The first target data corresponding to the first index src1 is determined to be d0. Based on the position of the first index src1 in matrix N1, the first target data d0 is saved to the first position of the second cache, i.e., the... Figure 6 In the first space.

[0090] Specifically, assuming d0 is stored in the cache, and the second target data is determined to be d14, d14 is stored in the second cache, such as... Figure 7 As shown, based on the position of the second index src3 in matrix N1, the second target data d14 is saved to the second position of the second cache, that is, the third space.

[0091] In one possible implementation, after completing the target data caching, steps S201 to S206 are executed again until the second cache contains the set amount of target data. For example, the memory address of the first index src2 is g, corresponding to the first target data d16; the memory address of the second index src4 is j, corresponding to the second target data d19; then... Figure 8 As shown, the four target data corresponding to the four indices of the first row of matrix N1 (i.e., the index set of src1) have been obtained and stored in the second cache.

[0092] In one possible implementation, after step S206 described above, step S207 is included, as follows: Figure 9 As shown, Figure 9 This is a flowchart of a data lookup method based on a lookup table according to an embodiment of the present invention.

[0093] Step S207: In response to the fact that the set amount of target data has been stored in the second cache, the method further includes:

[0094] Write the set amount of target data to the corresponding destination address.

[0095] Specifically, the destination addresses form the destination matrix N, such as... Figure 10 As shown, the positions of the target data written into the destination matrix N correspond one-to-one with the positions of matrix N1. For example, the memory address of the first index src1 is 0, corresponding to the first target data d0, and d0 is written to the destination address dst1 in the destination matrix N; the memory address of the second index src3 is e, corresponding to the first target data d14, and d14 is written to the destination address dst3 in the destination matrix N; the memory address of the first index src2 is g, corresponding to the first target data d16, and d16 is written to the destination address dst2 in the destination matrix N; the memory address of the second index src4 is j, corresponding to the second target data d19, and d19 is written to the destination address dst4 in the destination matrix N.

[0096] In one possible implementation, after step S207 described above, step S208 is included, as follows: Figure 11 As shown, Figure 11 This is a flowchart of a data lookup method based on a lookup table according to an embodiment of the present invention.

[0097] Step S208: Label the first index and the second index, wherein the label is used to indicate that the target data corresponding to the index has been obtained.

[0098] Specifically, in matrix N1, both the first index src1 and the second index src3 have obtained the corresponding target data. Therefore, in matrix N1, the first index src1 and the second index src3 are labeled. Optionally, the labeling symbol can be "hit," or other symbols can be used. This embodiment of the invention does not limit the specific labeling. Figure 12 As shown, the labeled index will not be used again when data is retrieved next time, and the search will continue to find the target data of the unlabeled index after the labeled address.

[0099] In one possible implementation, step S208 may also be executed after step S206. This embodiment of the invention does not limit the specific execution time.

[0100] In this embodiment of the invention, a new first index is determined among the plurality of indexes in the address lookup table, and the above steps are performed until all the plurality of indexes in the address lookup table are marked.

[0101] The following two specific embodiments provide a complete explanation of a data retrieval method based on a lookup table. Specific Implementation Example 1

[0103] Suppose that matrix N1 has 16 elements src1, src2, src3, src4, src5, src6, src7, src8, src9, src10, src11, src12, src13, src14, src15, and src16, where src1 corresponds to memory address 0, src2 to memory address g, src3 to memory address e, src4 to memory address j, src5 to memory address f, src6 to memory address m, and src7 to memory address w. This is only for illustrative purposes, and the memory addresses of the other elements will not be elaborated. The memory addresses in the memory list are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p, q, r, s, t, u, v, w, etc. The data corresponding to memory address 0 is d0, memory address 1 is d1, memory address 2 is d2, memory address 3 is d3, memory address 4 is d4, memory address 5 is d5, memory address 6 is d6, memory address 7 is d7, memory address 8 is d8, memory address 9 is d9, memory address a is d10, memory address b is d11, memory address c is d12, and memory address d is d13. The data corresponding to memory address e is d14, memory address f is d15, memory address g is d16, memory address h is d17, memory address i is d18, memory address j is d19, memory address k is d20, memory address l is d21, memory address m is d22, memory address n is d23, memory address o is d24, memory address p is d25, memory address q is d26, memory address r is d27, memory address s is d28, memory address t is d29, memory address u is d30, memory address v is d31, memory address w is d32, and so on.

[0104] At time T0, the memory address of the first index src1 is obtained as 0, and the corresponding index range is 0 to f. Data from memory addresses 0 to f is read from memory. The target data corresponding to src1 is d0. In this embodiment, it is assumed that the set quantity is 4, and the first index in matrix N1 consists of 4 consecutive indices, so the index set corresponding to the first index src1 is {src1, src2, src3, src4}. In another feasible embodiment, it is assumed that the set quantity is greater than 4, and based on the 4 indexes per row of matrix N1, to avoid reading data across rows, the index set corresponding to the first index src1 is also {src1, src2, src3, src4}. Since the memory address of index src3 in the index set corresponding to src1 is e, which covers the first index range 0 to f, the target data corresponding to src3 is determined to be d14. d0 and d14 are saved in the cache, and src1 and src3 are marked in matrix N1.

[0105] At time T1, if src2 is not labeled, it is determined that src2 is the new first index. The memory address of the src2 index is g, and its corresponding index range is g to v. Data from memory addresses g to v is read from memory. The target data corresponding to src2 is d16. The indices in the index set corresponding to src2 are located in the same row of the matrix, and the index set is {src2, src3, src4}. Since the memory address of the src4 index is j, which covers the index range g to v, the target data corresponding to src4 is d19. d16 and d19 are stored in the cache. At this time, the cache is full of 4 data items, so these 4 data items can be written together to the corresponding destination address. The cache stores the target data {d0, d16, d14, d19} corresponding to src1, src2, src3, and src4. These are written to the corresponding positions in the target address matrix N, and src2 and src4 are labeled in matrix N1.

[0106] Repeat the above steps until all index queries for matrix N1 have been completed.

[0107] In the above specific embodiments, the data relationships between matrix N, the list of memory addresses and data in memory, and matrix N1 are as follows: Figure 13 As shown. In this embodiment of the invention, the larger the index range corresponding to each index, the fewer times it needs to be retrieved; the more continuous the memory address values, the more target data each index range includes. Specific Implementation Example 2

[0109] The index and the corresponding data are read from memory based on the bit width. The specific value of the index can also be called the memory address. The bit width is determined according to the actual situation, and the size of the bit width determines the amount of data that can be retrieved from memory at one time.

[0110] Suppose that 32 bits of data can be retrieved from memory at once and cached. Specifically, for example... Figure 14 As shown, the memory addresses retrieved for the first time are 0, 1, ... 31; the corresponding data are d0, d1, ... d31. When retrieving data from memory again, the memory addresses can be 32, 33, ... 63, and the corresponding data are d32, d33, ... d63.

[0111] If the source matrix of the data to be obtained is an m×n matrix, that is, it includes m×n indices, such as Figure 15 As shown, it is necessary to read a total of m×n target data from memory according to the memory address corresponding to the index.

[0112] Assuming, Figure 15 In this context, n takes the value 9, and the memory addresses corresponding to each index are as follows: Figure 16 As shown, this illustrates the mapping relationship between indexes and memory addresses.

[0113] Under the above premise, the specific implementation process for obtaining the target data of the source matrix is ​​as follows:

[0114] First, using b11 as an index, the corresponding memory address is 3. Data from memory addresses 0-31 needs to be retrieved. Memory addresses 0-31 represent the index range corresponding to b11. In practical applications, data retrieval generally needs to be aligned with the memory bit width, i.e., retrieving data from index ranges such as 0-31, 32-63, 64-95, etc. Since 3 is within the range of 0-31, the index range corresponding to memory address 3 is 0-31. Therefore, when using b11 as an index, 32 data points corresponding to memory addresses 0-31 are retrieved at once. Specifically, the data retrieved is... Figure 17 The second row shown. Figure 17 In order to express the correspondence between memory addresses and data, two lines of data are displayed. However, in the actual process of retrieving data into the cache, only the second line of data is retrieved, and the first line of memory addresses is not retrieved.

[0115] In this embodiment of the invention, the number of data acquired each time can be 32, or it can be 16, 128, or other values, depending on the actual situation.

[0116] The 16 consecutive indices starting from b11 in the source matrix are the index set corresponding to b11, namely {b11, b12, ..., b16, b21, ..., b26}.

[0117] Then, within the range 0-31, it is determined whether the memory addresses corresponding to the 16 consecutive indices b11, b12, ..., b16, b21, ..., b26 in the source matrix exist. The memory addresses of the 12 indices b11, b12, b13, b18, b19, b20, b21, b22, b23, b24, b25, and b26 are found to be within this 0-31 range. These 12 indices are marked as "hit" in the source matrix, and the corresponding data is cached according to their positional relationship. The cached data list is as follows: Figure 18 As shown.

[0118] Then, following the index order in the source matrix, the index of the next unmarked hit is determined to be b14. Since the memory address of b14 is 37, 32 data points with memory addresses in the range of 32-63 are retrieved from memory, specifically as follows: Figure 19 As shown. The 16 consecutive indices starting from b14 in the source matrix are the index set corresponding to b14, namely {b14, b15, b16, ..., b29}.

[0119] Next, within the range of 32-63, determine the memory addresses corresponding to the 16 consecutive indices b14, b15, b16, ..., b29 in the source matrix. If the memory addresses of indices b14, b15, b16, and b17 fall within this range, mark these four indices as "hit" and cache the corresponding data based on their positional relationship. The cached data list is as follows: Figure 20 As shown.

[0120] Since 16 data points have already been acquired, and the maximum value of data that can be cached in the pre-set cache list is 16 (meaning the cache list is full), the 16 data points from the cached data list are written to the corresponding destination address all at once. Here, 16 is just a specific example and can be changed according to the actual situation. After writing the 16 data points to the destination address, the data list is cleared, and then the next unmarked index is identified again. Data reading and judgment are continued in the above manner until all m×n data points in the source matrix are read out.

[0121] In this embodiment of the invention, the process of determining the range of memory addresses for consecutive indices generally involves determining the consecutive indices within each row. If the width of the source matrix is ​​less than 16, the determination is performed on all data in a row each time. For example, if the source matrix width is 9 and the memory address of the first index in the first row is 3, then 32 data points in the memory address range of 0-31 are read, and it is determined which of the 9 indices in the first row fall within the 0-31 range. If only one index falls within the 0-31 range, data continues to be read, and it is determined which of the remaining 8 indices fall within the memory address range of the currently read data. If the width of the source matrix is ​​equal to or greater than 16, the determination is first made on which of the 16 indices fall within the memory address range of the currently read data. Then, it is further determined which of the remaining indices fall within the memory address range of the currently read data.

[0122] In one possible implementation, assuming the memory addresses corresponding to the indices are highly contiguous (e.g., completely contiguous), the width of each row index in the source matrix is ​​less than 16, and all data can be obtained from each row with a single data read; the width of each row index in the source matrix is ​​16×n, and all data can be obtained from each row with n data reads; the width of each row index in the source matrix is ​​16×n+m, and all data can be obtained from each row with n+1 data reads, where m is a positive integer less than n.

[0123] Figure 21 This is a schematic diagram of a data lookup device based on a lookup table according to an embodiment of the present invention. Figure 21 As shown, the device in this embodiment includes an acquisition unit 2101, a reading unit 2102, and a determination unit 2103.

[0124] The system includes an acquisition unit 2101, configured to acquire an address lookup table, which includes multiple indexes; the acquisition unit 2101 is further configured to determine a first index among the multiple indexes in the address lookup table, wherein the first index is an unmarked index in the address lookup table; a reading unit 2102, configured to read candidate data of the index range corresponding to the first index from a first storage location and cache it according to the memory address of the first index; a determination unit 2103, configured to determine a first target data corresponding to the first index from the candidate data; the acquisition unit 2101 is further configured to determine an index set according to the position of the first index in the address lookup table, wherein the index set includes a set number of indexes; the determination unit 2103 is further configured to, in response to the index set including a second index whose memory address is located in the index range corresponding to the first index, read a second target data corresponding to the second index from the candidate data in the cache, wherein the second index is an unmarked index among the multiple indexes that is ordered after the first index.

[0125] Optionally, the device further includes a caching unit, which saves the first target data to a first location of the second cache according to the position of the first index in the address lookup table, wherein the first location corresponds to the position of the first index in the address lookup table; and saves the second target data to a second location of the second cache according to the position of the second index in the address lookup table, wherein the second location corresponds to the position of the second index in the address lookup table.

[0126] Optionally, the device further includes a writing unit, and in response to the storage of the predetermined amount of target data in the first cache, the method further includes:

[0127] Write the set amount of target data to the corresponding destination address.

[0128] Optionally, the device further includes a labeling unit for labeling the first index and the second index, wherein the labeling is used to indicate that the target data corresponding to the index has been acquired.

[0129] Optionally, the acquisition unit is further configured to determine a new first index among the plurality of indexes in the address lookup table, and perform the above steps until all the plurality of indexes in the address lookup table are marked.

[0130] Optionally, the index range corresponds to the bit width of the memory.

[0131] Optionally, the address lookup table is a matrix that includes the plurality of indexes.

[0132] Optionally, in response to the number of indices in each row of the matrix being less than the set number, the indices included in the index set are located in the same row of the matrix.

[0133] Using the above method, candidate data corresponding to the index range of the first index can be read from memory at once and temporarily stored in the cache. When searching for the target data corresponding to the second index, it is not necessary to access memory again. The target data corresponding to the second index can be obtained directly from the candidate data in the cache. This reduces the number of times memory is accessed when searching for target data and improves the efficiency of target data search.

[0134] As those skilled in the art will recognize, various aspects of the embodiments of the present invention can be implemented as a system, method, or computer program product. Therefore, various aspects of the embodiments of the present invention can take the form of a completely hardware implementation, a completely software implementation (including firmware, resident software, microcode, etc.), or an implementation combining software and hardware aspects, which may generally be referred to herein as a "circuit," "module," or "system." Furthermore, various aspects of the embodiments of the present invention can take the form of a computer program product implemented in one or more computer-readable media having computer-readable program code implemented thereon.

[0135] Any combination of one or more computer-readable media can be used. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be, for example, (but not limited to) an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or apparatus, or any suitable combination thereof. More specific examples (not an exhaustive list) of computer-readable storage media will include: an electrical connection having one or more wires, a portable computer floppy disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable optical disc read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In the context of embodiments of the present invention, a computer-readable storage medium can be any tangible medium capable of containing or storing a program used by or in conjunction with an instruction execution system, device, or apparatus.

[0136] Computer-readable signal media may include propagated data signals having computer-readable program code implemented therein, such as in baseband or as part of a carrier wave. Such propagated signals may take any of a variety of forms, including, but not limited to, electromagnetic, optical, or any suitable combination thereof. A computer-readable signal medium may be any computer-readable medium that is not a computer-readable storage medium and can communicate, propagate, or transmit a program used by or in conjunction with an instruction execution system, device, or apparatus.

[0137] Program code implemented on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, fiber optic cable, RF, or any suitable combination thereof.

[0138] Computer program code for performing operations relating to various aspects of embodiments of the present invention can be written in any combination of one or more programming languages, including: object-oriented programming languages ​​such as Java, Smalltalk, C++, etc.; and conventional procedural programming languages ​​such as the "C" programming language or similar programming languages. The program code can be executed as a standalone software package entirely on the user's computer, partially on the user's computer, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (e.g., via the Internet provided by an Internet service provider).

[0139] The flowchart illustrations and / or block diagrams of the methods, apparatus (systems), and computer program products according to embodiments of the present invention describe various aspects of the embodiments of the present invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine such that the instructions (executed via the processor of the computer or other programmable data processing apparatus) create means for implementing the functions / actions specified in the flowchart and / or block diagram blocks or blocks.

[0140] These computer program instructions may also be stored in a computer-readable medium that can direct a computer, other programmable data processing apparatus or other means to operate in a particular manner, such that the instructions stored in the computer-readable medium produce an article of writing that includes instructions that implement the functions / actions specified in flowchart and / or block diagram blocks or blocks.

[0141] Computer program instructions may also be loaded onto a computer, other programmable data processing apparatus or other device to cause a series of operable steps to be performed on the computer, other programmable apparatus or other device to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide for implementing the functions / actions specified in flowchart and / or block diagram blocks or blocks.

[0142] This invention provides a computer program instruction that, when executed by a processor, implements the method described in any of the above embodiments.

[0143] This invention provides a computer-readable storage medium storing computer program instructions thereon, which, when executed by a processor, implement the methods described in any of the above embodiments.

[0144] This invention provides a chip including a memory and a processing core. The memory is used to store one or more computer program instructions, wherein the one or more computer program instructions are executed by the processing core to implement the method as described in any of the above embodiments.

[0145] This invention provides a board card that includes the aforementioned chip.

[0146] This invention provides a server that includes the aforementioned board.

[0147] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. For those skilled in the art, the present invention can be modified and varied in various ways. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of protection of the present invention.

Claims

1. A data retrieval method based on a lookup table, characterized in that, The method includes: Obtain the address lookup table, which includes multiple indexes; A first index is determined among the plurality of indexes in the address lookup table, wherein the first index is an unlabeled index in the address lookup table, and the unlabeled index indicates that the target data corresponding to the index has not been obtained; Based on the memory address of the first index, candidate data is read from memory into the first cache, wherein the candidate data is the data corresponding to the index range of the first index, and the index range corresponds to the bit width of the memory. The first target data corresponding to the first index is determined from the candidate data; An index set is determined based on the position of the first index in the address lookup table, wherein the index set includes a predetermined number of indexes among the plurality of indexes in the address lookup table, and the indexes in the index set are multiple consecutive indexes of the first index in the address lookup table; In response to the memory address of the second index being located within the index range, the second target data corresponding to the second index is read from the candidate data in the first cache, wherein the second index is an unlabeled index in the index set, and there are multiple second indexes, and multiple target data corresponding to the second indexes are obtained at once through a single data read operation; Based on the position of the first index in the address lookup table, the first target data is saved to a first position in the second cache, wherein the first position corresponds to the position of the first index in the address lookup table; based on the position of the second index in the address lookup table, the second target data is saved to a second position in the second cache, wherein the second position corresponds to the position of the second index in the address lookup table; in response to the second cache storing the set number of target data, the set number of target data is written to the corresponding destination address; wherein the address lookup table is a matrix including the plurality of indexes; in response to the number of indexes in each row of the matrix being less than the set number, the indexes included in the index set are located in the same row of the matrix.

2. The method as described in claim 1, characterized in that, The method also includes: The first index and the second index are labeled, and the label is used to indicate that the target data corresponding to the index has been obtained.

3. The method as described in claim 2, characterized in that, The method also includes: A new first index is determined among the plurality of indexes in the address lookup table, and the steps of claim 2 are performed until all the plurality of indexes in the address lookup table are marked.

4. A data lookup device based on a lookup table, characterized in that, The device includes: The acquisition unit is used to acquire an address lookup table, which includes multiple indexes. The acquisition unit is further configured to determine a first index among the plurality of indexes in the address lookup table, wherein the first index is an unlabeled index in the address lookup table, and the unlabeled index indicates that the target data corresponding to the index has not been acquired; The reading unit is configured to read candidate data from memory into a first cache according to the memory address of the first index, wherein the candidate data is data corresponding to the index range of the first index, and the index range corresponds to the bit width of the memory. A determining unit is configured to determine, from the candidate data, the first target data corresponding to the first index; The acquisition unit is further configured to determine an index set based on the position of the first index in the address lookup table, wherein the index set includes a set number of indexes among the plurality of indexes in the address lookup table, and the indexes in the index set are a plurality of consecutive indexes of the first index in the address lookup table; The determining unit is further configured to, in response to the memory address of the second index being located within the index range, read the second target data corresponding to the second index from the candidate data in the first cache, wherein the second index is an unlabeled index in the index set, and there are multiple second indexes, and multiple target data corresponding to the second indexes are obtained at once through a single data read operation; The device further includes a caching unit, which saves the first target data to a first location in a second cache according to the position of the first index in the address lookup table, wherein the first location corresponds to the position of the first index in the address lookup table; and saves the second target data to a second location in the second cache according to the position of the second index in the address lookup table, wherein the second location corresponds to the position of the second index in the address lookup table; the device further includes a writing unit, which writes the set number of target data to the corresponding destination address in response to the second cache storing the set number of target data; wherein the address lookup table is a matrix including the plurality of indexes; and in response to the number of indexes in each row of the matrix being less than the set number, the indexes included in the index set are located in the same row of the matrix.

5. A computer program instruction, characterized in that, The computer program instructions, when executed by a processor, implement the method as described in any one of claims 1-3.

6. A computer-readable storage medium storing computer program instructions thereon, characterized in that, The computer program instructions, when executed by a processor, implement the method as described in any one of claims 1-3.

7. A chip comprising a memory and a processing core, characterized in that, The memory is used to store one or more computer program instructions, wherein the one or more computer program instructions are executed by the processing core to implement the method as described in any one of claims 1-3.

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