Gate drive circuit, drive method and display panel

Abstract

The present application discloses a gate drive circuit, a drive method and a display panel. The gate drive circuit includes a pull-up control module, a pull-up module, a pull-down control module, a pull-down module and a voltage stabilizing module. The voltage stabilizing module is connected to the pull-down node and the pull-up control module. Not only can the leakage current of the pull-down node in a high potential state be reduced to stabilize the high potential of the pull-down node, but the level of the pull-down node in a low potential state can also be maintained to stabilize the low potential of the pull-down node.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate drive circuit, a drive method, and a display panel. Background Art

[0002] In the gate drive circuit, the output end of the pull-up control module is connected to the control end of the pull-up module to form a pull-up node, and the output end of the pull-down control module is connected to the control end of the pull-down module to form a pull-down node. The unstable potential of at least one of the pull-up node and the pull-down node will reduce the reliability of the operation. Summary of the Invention

[0003] The present application provides a gate driving circuit, a driving method and a display panel to alleviate the technical problem of poor potential stability of a pull-down node.

[0004] In a first aspect, the present application provides a gate drive circuit, which includes a pull-up control module, a pull-up module, a pull-down control module, a pull-down module and a voltage stabilizing module, wherein the pull-up control module is connected to the pull-up node for controlling the potential of the pull-up node; the pull-up module is connected to the pull-up node for outputting a drive signal according to the potential of the pull-up node; the pull-down control module is connected to the pull-down node and the pull-up control module for controlling the potential of the pull-down node; the pull-down module is connected to the pull-down node and the pull-up module for outputting a drive signal according to the potential of the pull-down node; the voltage stabilizing module is connected to the pull-down node and the pull-up control module for reducing the leakage current of the pull-down node when it is in a high potential state and maintaining the level of the pull-down node in a low potential state.

[0005] In some embodiments, the voltage stabilization module includes a leakage control unit and a first voltage stabilization unit. The leakage control unit is connected to the pull-down node and outputs a trigger signal for reducing the leakage current in response to the pull-down node being in a high potential state. The first voltage stabilization unit is connected to the leakage control unit and the pull-down node and is used to reduce the leakage current of the pull-down node according to the trigger signal, and pull down the potential of the pull-down node in response to the high potential of the pull-up node and the low potential of the pull-down node.

[0006] In some embodiments, the leakage control unit includes a first transistor, one of a source / drain of the first transistor is connected to the high potential line, a gate of the first transistor is connected to the pull-down node, and the other of the source / drain of the first transistor is connected to the first node.

[0007] In some embodiments, the first voltage stabilizing unit includes a second transistor and a third transistor, one of the source / drain of the second transistor is connected to the pull-down node, the other of the source / drain of the second transistor is connected to the other of the source / drain of the first transistor and the first node, and the gate of the second transistor is connected to the first drive line; one of the source / drain of the third transistor is connected to the other of the source / drain of the second transistor, the other of the source / drain of the third transistor is connected to the first low potential line, and the gate of the third transistor is connected to the first drive line.

[0008] In some embodiments, the voltage stabilizing module further includes a second voltage stabilizing unit, which is connected to the pull-down node, the pull-up node, the first node, and the first low-potential line, and is configured to reduce the leakage current of the pull-down node according to a trigger signal, and to pull down the potential of the pull-down node in response to a high potential of the pull-up node and a low potential of the first node.

[0009] In some embodiments, the second voltage stabilizing unit includes a fourth transistor and a fifth transistor, one of the source / drain of the fourth transistor is connected to the pull-down node, the other of the source / drain of the fourth transistor is connected to the first node, and the gate of the fourth transistor is connected to the pull-up node; one of the source / drain of the fifth transistor is connected to the other of the source / drain of the fourth transistor, the other of the source / drain of the fifth transistor is connected to the first low potential line, and the gate of the fifth transistor is connected to the gate of the fourth transistor.

[0010] In some embodiments, the pull-up control module includes a sixth transistor and a seventh transistor, one of the source / drain of the sixth transistor is connected to the high potential line, and the gate of the sixth transistor is connected to the first drive line; one of the source / drain of the seventh transistor is connected to the other of the source / drain of the sixth transistor, the other of the source / drain of the seventh transistor is connected to the pull-up node, and the gate of the seventh transistor is connected to the gate of the sixth transistor.

[0011] In some embodiments, the pull-up control module further includes an eighth transistor, a ninth transistor, a tenth transistor, a first capacitor, an eleventh transistor, and a twelfth transistor, one of the source / drain of the eighth transistor is connected to the input terminal of the pull-up module and the high potential line, and the gate of the eighth transistor is connected to the pull-up node and the control terminal of the pull-up module; one of the source / drain of the ninth transistor is connected to the pull-up node, the other of the source / drain of the ninth transistor is connected to the other of the source / drain of the eighth transistor, and the gate of the ninth transistor is connected to the second driving line; one of the source / drain of the tenth transistor is connected to the other of the source / drain of the ninth transistor, and the other of the source / drain of the tenth transistor is connected to the second driving line. One is connected to the first low potential line, and the gate of the tenth transistor is connected to the gate of the ninth transistor; one end of the first capacitor is connected to the pull-up node, and the other end of the first capacitor is connected to the output end of the pull-up module and the output end of the pull-down module; one of the source / drain of the eleventh transistor is connected to the pull-up node, the other of the source / drain of the eleventh transistor is connected to the other of the source / drain of the eighth transistor, and the gate of the eleventh transistor is connected to the pull-down node; one of the source / drain of the twelfth transistor is connected to the other of the source / drain of the eleventh transistor, the other of the source / drain of the twelfth transistor is connected to the first low potential line, and the gate of the twelfth transistor is connected to the gate of the eleventh transistor.

[0012] In some embodiments, the pull-down control module includes a thirteenth transistor, a second capacitor and a fourteenth transistor, one of the source / drain of the thirteenth transistor is connected to the second driving line, and the gate of the thirteenth transistor is connected to the level transfer line; one end of the second capacitor is connected to the other of the source / drain of the thirteenth transistor; one of the source / drain of the fourteenth transistor is connected to the other end of the second capacitor and the high potential line, the gate of the fourteenth transistor is connected to the other of the source / drain of the thirteenth transistor, the other of the source / drain of the fourteenth transistor is connected to the pull-down node and the control end of the pull-down module, and the input end of the pull-down module is connected to the first low potential line or the second low potential line.

[0013] In a second aspect, the present application provides a display panel, which includes the gate driving circuit in at least one of the above-mentioned embodiments.

[0014] In a third aspect, the present application provides a driving method, which is applied to the gate driving circuit in at least one of the above-mentioned embodiments, and the driving method includes: a pull-up control module controls the potential of the pull-up node according to a first driving signal; a pull-down control module controls the potential of the pull-down node according to a second driving signal and a stage transmission signal; a voltage stabilizing module reduces the leakage current of the pull-down node in a high potential state and maintains the level of the pull-down node in a low potential state according to the first driving signal and the potential of the pull-up node; the pull-up module pulls up and maintains the potential of the driving signal according to the potential of the pull-up node; and the pull-down module pulls down and maintains the potential of the driving signal according to the potential of the pull-down node.

[0015] In some embodiments, the driving method further includes: the scanning control driver generates a rising edge of the first driving signal at a first moment; the scanning control driver generates a first rising edge of the level transfer signal within a first time range; and the scanning control driver constructs a first moment within the first time range.

[0016] In some embodiments, the driving method further includes: the scanning control driver generates a rising edge of a second driving signal at a second moment, the second moment being later than the first moment in a frame and outside the first time range; the scanning control driver generates a second rising edge of the level transfer signal at the second moment.

[0017] In some embodiments, the driving method further includes: the gate driving circuit configures a rising edge of the driving signal within a first time range; and the gate driving circuit configures a falling edge of the driving signal at a second time.

[0018] The gate drive circuit, drive method and display panel provided in the present application are connected to the pull-down node and the pull-up control module through a voltage stabilizing module, which can not only reduce the leakage current of the pull-down node when it is in a high potential state to stabilize the high potential of the pull-down node, but also maintain the level of the pull-down node in a low potential state to stabilize the low potential of the pull-down node, thereby improving the potential stability of the pull-down node and improving the reliability of the operation.

[0019] Furthermore, the voltage stabilizing module can play two different roles under corresponding conditions, and can realize multiple functions with less hardware, thereby simplifying the architecture of the gate driving circuit and reducing the space occupied by the frame of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0021] Figure 1 A schematic diagram of the structure of the gate drive circuit provided in an embodiment of the present application.

[0022] Figure 2 for Figure 1 The timing diagram of the gate drive circuit shown is shown. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0024] This embodiment provides a gate drive circuit. Figure 1 、 Figure 2 ,like Figure 1 As shown, the gate drive circuit includes a pull-up module 200, the input end of the pull-up module 200 is connected to the high potential line, the control end of the pull-up module 200 is connected to the pull-up node Q, and the output end of the pull-up module 200 is used to output the drive signal G3.

[0025] It should be noted that the high potential line is used to transmit the high potential signal VGH, and the pull-up module 200 can provide a high potential for the driving signal G3 according to the potential of the pull-up node Q.

[0026] In one embodiment, the pull-up module 200 includes a pull-up transistor T21, one of the source / drain of the pull-up transistor T21 is connected to the high potential line, the gate of the pull-up transistor T21 is connected to the pull-up node Q, and the other of the source / drain of the pull-up transistor T21 is used to output the driving signal G3.

[0027] It can be understood that the pull-up transistor T21 can provide a high potential for the driving signal G3 when in a conducting state or an open state.

[0028] In one embodiment, the gate drive circuit further includes a pull-down module 400, an input end of the pull-down module 400 is connected to the first low-potential line or the second low-potential line, an output end of the pull-down module 400 is connected to the output end of the pull-up module 200 and outputs a drive signal G3, and a control end of the pull-down module 400 is connected to the pull-down node QB.

[0029] It should be noted that the first low potential line is used to transmit the first low potential signal VGL1, the second low potential line is used to transmit the second low potential signal VGL2, and the pull-down module 400 can provide a low potential for the driving signal G3 according to the potential of the pull-down node QB.

[0030] In one embodiment, the pull-down module 400 includes a pull-down transistor T31, one of the source / drain of the pull-down transistor T31 is connected to the first low-potential line or the second low-potential line, the gate of the pull-down transistor T31 is connected to the pull-down node QB, and the other of the source / drain of the pull-down transistor T31 is connected to the other of the source / drain of the pull-up transistor T21 to output the driving signal G3.

[0031] It can be understood that the pull-down transistor T31 can provide a low potential for the driving signal G3 in the on state or the open state.

[0032] In one embodiment, the gate driving circuit further includes a voltage stabilizing module 500 connected to the pull-down node QB for reducing leakage current when the pull-down node QB is in a high potential state and maintaining the level of the pull-down node QB in a low potential state.

[0033] It can be understood that the gate drive circuit provided in this embodiment is connected to the pull-down node QB through the voltage stabilizing module 500, which can not only reduce the leakage current of the pull-down node QB in a high potential state to stabilize the high potential of the pull-down node QB, but also maintain the level of the pull-down node QB in a low potential state to stabilize the low potential of the pull-down node QB, thereby improving the potential stability of the pull-down node QB and improving the reliability of the operation.

[0034] Furthermore, the voltage stabilizing module 500 can play two different roles under corresponding conditions, and can realize multiple functions with less hardware, thereby simplifying the architecture of the gate driving circuit and reducing the space occupied by the frame of the display panel.

[0035] In one embodiment, the voltage stabilization module 500 includes a leakage control unit 510 and a first voltage stabilization unit 520. The leakage control unit 510 is connected to the pull-down node QB and outputs a trigger signal for reducing the leakage current in response to the pull-down node QB being in a high potential state. The first voltage stabilization unit 520 is connected to the leakage control unit 510 and the pull-down node QB and is used to reduce the leakage current of the pull-down node QB according to the trigger signal, and pull down the potential of the pull-down node QB in response to the high potential of the pull-up node Q and the low potential of the pull-down node QB.

[0036] It should be noted that the input terminal of the leakage control unit 510 can be connected to the high-potential line, the control terminal of the leakage control unit 510 can be connected to the pull-down node QB, and the output terminal of the leakage control unit 510 is connected to the first node N2. The input terminal of the first voltage stabilizing unit 520 is connected to the first low-potential line, the first control terminal of the first voltage stabilizing unit 520 is connected to the second control terminal of the first voltage stabilizing unit 520 and the first drive line, the output terminal of the first voltage stabilizing unit 520 is connected to the pull-down node QB, and the internal node of the first voltage stabilizing unit 520 is connected to the first node N2. The first drive line is used to transmit the first drive signal G1.

[0037] The combination of the first voltage stabilizing unit 520 and the leakage control unit 510 can reduce the leakage current when the pull-down node QB is in a high potential state, thereby stabilizing the high potential of the pull-down node QB. When the pull-down node QB is in a low potential state, the leakage control unit 510 does not operate, and the first voltage stabilizing unit 520 can operate alone. At this time, under the control of the high potential of the first drive signal G1, the potential of the pull-up node Q is the same as the potential of the first drive signal G1, and the low potential of the pull-down node QB can be stabilized at the same potential as the first low potential signal VGL1.

[0038] The trigger signal may be a high potential signal VGH output by the leakage control unit 510 .

[0039] In one embodiment, the leakage control unit 510 includes a first transistor T42, wherein one of the source / drain of the first transistor T42 is connected to the high potential line, the gate of the first transistor T42 is connected to the pull-down node QB, and the other of the source / drain of the first transistor T42 is connected to the first node N2.

[0040] It should be noted that when the first transistor T42 is in the on state or the open state, the high potential signal VGH is transmitted to the first node N2 through the first transistor T42 to serve as the trigger signal.

[0041] In one embodiment, the first voltage stabilizing unit 520 includes a second transistor T45 and a third transistor T46, wherein one of the source / drain of the second transistor T45 is connected to the pull-down node QB, the other of the source / drain of the second transistor T45 is connected to the other of the source / drain of the first transistor T42 and the first node N2, and the gate of the second transistor T45 is connected to the first driving line; one of the source / drain of the third transistor T46 is connected to the other of the source / drain of the second transistor T45, the other of the source / drain of the third transistor T46 is connected to the first low potential line, and the gate of the third transistor T46 is connected to the first driving line.

[0042] It should be noted that the potential of the pull-down node QB is in a high potential state, the first drive signal G1 is in a low potential state, the second transistor T45 and the third transistor T46 are both turned off, and the potential of the first node N2 is the potential of the high potential signal VGH, which is not lower than the potential of the pull-down node QB at this time. Therefore, the leakage path of the charge of the pull-down node QB through the second transistor T45 is slowed down or eliminated, so that the high potential state of the pull-down node QB can be sustained for a longer time.

[0043] The potential of the pull-down node QB is in a low potential state, the first drive signal G1 is in a high potential state, and the second transistor T45 and the third transistor T46 are both turned on. At this time, the potential of the first node N2 is in a natural state and is not clamped by the potential of the high potential signal VGH. Therefore, the second transistor T45 and the third transistor T46 form a conduction path, which can maintain the low potential of the pull-down node QB at the potential of the first low potential signal VGL1.

[0044] In one embodiment, the voltage stabilizing module 500 further includes a second voltage stabilizing unit 530, which is connected to the pull-down node QB, the pull-up node Q, the first node N2, and the first low-voltage line, and is configured to reduce the leakage current of the pull-down node QB according to a trigger signal, and to pull down the potential of the pull-down node QB in response to a high potential of the pull-up node Q and a low potential of the first node N2.

[0045] It should be noted that the input end of the second voltage stabilizing unit 530 is connected to the first low-potential line, the first control end of the second voltage stabilizing unit 530 is connected to the second control end of the second voltage stabilizing unit 530 and the pull-up node Q, and the output end of the second voltage stabilizing unit 530 is connected to the pull-down node QB.

[0046] In one embodiment, the second voltage stabilizing unit 530 includes a fourth transistor T43 and a fifth transistor T44, wherein one of the source / drain of the fourth transistor T43 is connected to the pull-down node QB, the other of the source / drain of the fourth transistor T43 is connected to the first node N2, and the gate of the fourth transistor T43 is connected to the pull-up node Q; one of the source / drain of the fifth transistor T44 is connected to the other of the source / drain of the fourth transistor T43, the other of the source / drain of the fifth transistor T44 is connected to the first low potential line, and the gate of the fifth transistor T44 is connected to the gate of the fourth transistor T43.

[0047] It should be noted that the potential of the pull-down node QB is in a high potential state, the first drive signal G1 is in a low potential state, the potential of the pull-up node Q is also in a low potential state, the fourth transistor T43 and the fifth transistor T44 are both turned off, and the potential of the first node N2 is the potential of the high potential signal VGH, which is not lower than the potential of the pull-down node QB at this time. Therefore, the leakage path of the charge of the pull-down node QB through the fourth transistor T43 is slowed down or eliminated, so that the high potential state of the pull-down node QB can be sustained for a longer time.

[0048] The potential of the pull-down node QB is in a low potential state, the first drive signal G1 is in a high potential state, and the fourth transistor T43 and the fifth transistor T44 are both turned on. At this time, the potential of the first node N2 is in a natural state and is not clamped by the potential of the high potential signal VGH. Therefore, the fourth transistor T43 and the fifth transistor T44 form a conduction path, which can maintain the low potential of the pull-down node QB at the potential of the first low potential signal VGL1.

[0049] In one embodiment, the gate driving circuit further includes a pull-up control module 100 . The pull-up control module 100 is connected to the pull-up node Q and is used to control the potential of the pull-up node Q.

[0050] In one embodiment, the pull-up control module 100 includes a sixth transistor T16 and a seventh transistor T17, wherein one of the source / drain of the sixth transistor T16 is connected to the high potential line, and the gate of the sixth transistor T16 is connected to the first driving line; one of the source / drain of the seventh transistor T17 is connected to the other of the source / drain of the sixth transistor T16, the other of the source / drain of the seventh transistor T17 is connected to the pull-up node Q, and the gate of the seventh transistor T17 is connected to the gate of the sixth transistor T16.

[0051] It should be noted that when the first driving signal G1 is at a high potential, the sixth transistor T16 and the seventh transistor T17 are turned on at the same time, and the potential of the pull-up node Q is also at a high potential.

[0052] The gate of the sixth transistor T16 can share the same first driving line with the gate of the seventh transistor T17, the gate of the second transistor T45 and the gate of the third transistor T46, which can reduce the number of signal lines required by the gate driving circuit and help further reduce the frame space.

[0053] In one embodiment, the pull-up control module 100 further includes an eighth transistor T13, a ninth transistor T15, a tenth transistor T14, a first capacitor C1, an eleventh transistor T11, and a twelfth transistor T12, wherein one of the source / drain of the eighth transistor T13 is connected to the input terminal of the pull-up module 200 and the high potential line, and the gate of the eighth transistor T13 is connected to the pull-up node Q and the control terminal of the pull-up module 200; one of the source / drain of the ninth transistor T15 is connected to the pull-up node Q, the other of the source / drain of the ninth transistor T15 is connected to the other of the source / drain of the eighth transistor T13, and the gate of the ninth transistor T15 is connected to the second driving line; one of the source / drain of the tenth transistor T14 is connected to the other of the source / drain of the ninth transistor T15, and the source / drain of the tenth transistor T14 is connected to the second driving line. The other of the sources / drains of the eleventh transistor T11 is connected to the other of the sources / drains of the eighth transistor T13, and the gate of the eleventh transistor T11 is connected to the pull-down node QB; one of the sources / drains of the twelfth transistor T12 is connected to the other of the sources / drains of the eleventh transistor T11, the other of the sources / drains of the twelfth transistor T12 is connected to the first low potential line, and the gate of the twelfth transistor T12 is connected to the gate of the eleventh transistor T11.

[0054] The other of the source and drain of the eighth transistor T13 may serve as the second node N1 .

[0055] It should be noted that the other one of the source / drain of the tenth transistor T14 can share the same first low-potential line with the other one of the source / drain of the fifth transistor T44, the other one of the source / drain of the twelfth transistor T12, and the other one of the source / drain of the third transistor T46, which can reduce the number of signal lines required for the gate drive circuit and help further reduce the border space.

[0056] In one embodiment, the gate driving circuit further includes a pull-down control module 300 . The pull-down control module 300 is connected to the pull-down node QB and the pull-up control module 100 and is used to control the potential of the pull-down node QB.

[0057] In one embodiment, the pull-down control module 300 includes a thirteenth transistor T47, a second capacitor C2, and a fourteenth transistor T41. One of the source / drain of the thirteenth transistor T47 is connected to the second driving line, and the gate of the thirteenth transistor T47 is connected to the level transfer line; one end of the second capacitor C2 is connected to the other of the source / drain of the thirteenth transistor T47; one of the source / drain of the fourteenth transistor T41 is connected to the other end of the second capacitor C2 and the high potential line, the gate of the fourteenth transistor T41 is connected to the other of the source / drain of the thirteenth transistor T47, the other of the source / drain of the fourteenth transistor T41 is connected to the pull-down node QB and the control end of the pull-down module 400, and the input end of the pull-down module 400 is connected to the first low potential line or the second low potential line.

[0058] The level transfer line is used to transmit the level transfer signal Cout. The other of the source and drain of the thirteenth transistor T47 can serve as a node T.

[0059] It should be noted that one of the source / drain of the thirteenth transistor T47 can share the same second driving line with the gate of the ninth transistor T15 and the gate of the tenth transistor T14, which can reduce the number of signal lines required for the gate driving circuit and help further reduce the frame space.

[0060] Among them, when the input end of the pull-down module 400 is connected to the second low-potential line, the potential of the driving signal G3 can be pulled down separately, and the potential of the pull-up node Q and the potential of the pull-down node QB can be isolated to avoid mutual influence, while also improving the working reliability of the gate drive circuit.

[0061] It should be noted that at least one of the above-mentioned transistors can be an N-channel thin film transistor, specifically an N-channel indium gallium zinc oxide thin film transistor, and at least one of the above-mentioned transistors can also be a P-channel thin film transistor, specifically a P-channel low-temperature polycrystalline silicon thin film transistor.

[0062] Figure 2 for Figure 1 The timing diagram of the gate drive circuit shown in the figure, each of the above transistors is an N-channel thin film transistor, and one working cycle or one frame of the gate drive circuit includes the following two stages:

[0063] Wide pulse output phase P1: When the level transmission signal Cout and the first drive signal G1 are switched to a high level, the sixth transistor T16 and the seventh transistor T17 are turned on, the pull-up node Q is charged to a high level, and the pull-up transistor T21, the second transistor T45, and the third transistor T46 are turned on; at the same time, the second drive signal G2 is at a low level, the thirteenth transistor T47 in the conductive state discharges the gate of the fourteenth transistor T41 to a low level, the pull-down node QB is fully discharged to a low level through the second transistor T45 and the third transistor T46, the pull-down transistor T31 is turned off, and the drive signal G3 starts to output a high level.

[0064] Reset & Idle Phase P2: When the level transfer signal Cout and the second drive signal G2 are switched to a high level, the ninth transistor T15 and the tenth transistor T14 are turned on, the pull-up node Q is discharged to a low level, and the pull-up transistor T21, the second transistor T45, and the third transistor T46 are turned off; at the same time, the second drive signal G2 is high, the thirteenth transistor T47 in the turned-on state charges the gate of the fourteenth transistor T41 to a high level, the pull-down node QB is charged to a high level through the fourteenth transistor T41, the pull-down transistor T31 is turned on, the drive signal G3 outputs a low level, the reset is completed, and the idle phase is entered.

[0065] It should be noted that, since the voltage stabilizing module 500 can reduce the leakage current of the pull-down node QB when it is in a high potential state and maintain the level of the pull-down node QB in a low potential state, the high potential state of the pull-down node QB is easier to maintain in the reset & idle stage P2, so that at the beginning of the wide pulse output stage P1, the rising edge of the first drive signal G1 and the first rising edge of the level transfer signal Cout do not need to be strictly aligned, that is, the first rising edge of the level transfer signal Cout can be moved back and forth relative to the rising edge of the first drive signal G1, that is, the phase is changed. This can modulate the rising edge of the drive signal G3 by adjusting the rising edge of the first drive signal G1 without excessively considering the first rising edge of the level transfer signal Cout, thereby increasing the adjustability of the phase and the adjustable range of the pulse width of the drive signal G3.

[0066] based on Figure 2As shown in the timing diagram, this embodiment provides a driving method, which is applied to the gate driving circuit in at least one of the above-mentioned embodiments, and the driving method includes: a pull-up control module controlling the potential of the pull-up node according to a first driving signal; a pull-down control module controlling the potential of the pull-down node according to a second driving signal and a stage transmission signal; a voltage stabilizing module reducing the leakage current of the pull-down node in a high potential state and maintaining the level of the pull-down node in a low potential state according to the first driving signal and the potential of the pull-up node; the pull-up module pulling up and maintaining the potential of the driving signal according to the potential of the pull-up node; and the pull-down module pulling down and maintaining the potential of the driving signal according to the potential of the pull-down node.

[0067] It can be understood that the driving method provided in this embodiment is connected to the pull-down node QB and the pull-up control module 100 through the voltage stabilizing module 500, which can not only reduce the leakage current of the pull-down node QB in a high potential state to stabilize the high potential of the pull-down node QB, but also maintain the level of the pull-down node QB in a low potential state to stabilize the low potential of the pull-down node QB, thereby improving the potential stability of the pull-down node QB and improving the reliability of the operation.

[0068] Furthermore, the voltage stabilizing module 500 can play two different roles under corresponding conditions, and can realize multiple functions with less hardware, thereby simplifying the architecture of the gate driving circuit and reducing the space occupied by the frame of the display panel.

[0069] In one embodiment, the driving method further includes: the scanning control driver generates a rising edge of the first driving signal at a first moment; the scanning control driver generates a first rising edge of the level transfer signal within a first time range; and the scanning control driver constructs the first moment within the first time range.

[0070] In one embodiment, the driving method further includes: the scanning control driver generates a rising edge of the second driving signal at a second moment, the second moment is later than the first moment in a frame and is outside the first time range; the scanning control driver generates a second rising edge of the level transfer signal at the second moment.

[0071] In one embodiment, the driving method further includes: the gate driving circuit configures a rising edge of the driving signal within a first time range; and the gate driving circuit configures a falling edge of the driving signal at a second time.

[0072] It should be noted that in one frame of this embodiment, the gate drive circuit can construct the rising edge of the drive signal according to the rising edge of the first drive signal and the first rising edge of the level transfer signal, and construct the falling edge of the drive signal according to the rising edge of the second drive signal and the second rising edge of the level transfer signal.

[0073] In one embodiment, Figure 1 、 Figure 2 As shown, this embodiment provides a display panel, which includes the gate driving circuit of at least one of the above embodiments, wherein the driving signal G3 is used to turn on or off the thin film transistor.

[0074] It can be understood that the display panel provided in this embodiment is connected to the pull-down node QB and the pull-up control module 100 through the voltage stabilizing module 500, which can not only reduce the leakage current of the pull-down node QB in a high potential state to stabilize the high potential of the pull-down node QB, but also maintain the level of the pull-down node QB in a low potential state to stabilize the low potential of the pull-down node QB, thereby improving the potential stability of the pull-down node QB and improving the reliability of the operation.

[0075] Furthermore, the voltage stabilizing module 500 can play two different roles under corresponding conditions, and can realize multiple functions with less hardware, thereby simplifying the architecture of the gate driving circuit and reducing the space occupied by the frame of the display panel.

[0076] It should be noted that the above-mentioned high potential can turn on / conduct the N-channel thin film transistor, or can turn off / cut off the P-channel thin film transistor; the above-mentioned low potential can turn on / conduct the P-channel thin film transistor, or can turn off / cut off the N-channel thin film transistor.

[0077] In one embodiment, the first driving signal G1 , the second driving signal G2 and the level transfer signal Cout may all be provided or generated by a scan control driver.

[0078] It is understandable that this can reduce the number of scan control drivers used in the display panel and reduce the space occupied by the frame of the display panel.

[0079] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0080] The above is a detailed introduction to the gate drive circuit, drive method and display panel provided in the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A gate drive circuit, characterized in that: include: a pull-up control module connected to the pull-up node and configured to control the potential of the pull-up node according to a first driving signal; a pull-up module connected to the pull-up node and configured to output a driving signal according to the potential of the pull-up node; a pull-down control module, connected to the pull-down node and the pull-up control module, and configured to control the potential of the pull-down node; a pull-down module, connected to the pull-down node and the pull-up module, and configured to output the driving signal according to the potential of the pull-down node; as well as A voltage stabilizing module is connected to the pull-down node and the pull-up control module, and is used to reduce the leakage current of the pull-down node when it is in a high potential state and maintain the level of the pull-down node in a low potential state according to the first drive signal and the potential of the pull-up node.

2. The gate drive circuit according to claim 1, wherein: The voltage stabilizing module includes: a leakage control unit connected to the pull-down node and outputting a trigger signal for reducing leakage current in response to the pull-down node being in a high potential state; and A first voltage stabilizing unit is connected to the leakage control unit and the pull-down node, and is used to reduce the leakage current of the pull-down node according to the trigger signal, and pull down the potential of the pull-down node in response to the high potential of the pull-up node and the low potential of the pull-down node.

3. The gate drive circuit according to claim 2, wherein: The leakage control unit includes a first transistor, one of a source and a drain of the first transistor is connected to a high potential line, a gate of the first transistor is connected to the pull-down node, and the other of the source and the drain of the first transistor is connected to a first node.

4. The gate driving circuit according to claim 3, wherein: The first voltage stabilizing unit includes: a second transistor, one of a source and a drain of the second transistor being connected to the pull-down node, the other of the source and the drain of the second transistor being connected to the other of the source and the drain of the first transistor and the first node, and a gate of the second transistor being connected to the first driving line; and a third transistor, wherein one of the source / drain of the third transistor is connected to the other of the source / drain of the second transistor, the other of the source / drain of the third transistor is connected to the first low potential line, and the gate of the third transistor is connected to the first drive line.

5. The gate driving circuit according to claim 4, wherein: The voltage stabilizing module also includes a second voltage stabilizing unit, which is connected to the pull-down node, the pull-up node, the first node and the first low-potential line, and is used to reduce the leakage current of the pull-down node according to the trigger signal, and pull down the potential of the pull-down node in response to the high potential of the pull-up node and the low potential of the first node.

6. The gate driving circuit according to claim 5, wherein: The second voltage stabilizing unit includes: a fourth transistor, one of a source and a drain of the fourth transistor being connected to the pull-down node, the other of the source and the drain of the fourth transistor being connected to the first node, and a gate of the fourth transistor being connected to the pull-up node; and a fifth transistor, one of the source / drain of the fifth transistor is connected to the other of the source / drain of the fourth transistor, the other of the source / drain of the fifth transistor is connected to the first low potential line, and the gate of the fifth transistor is connected to the gate of the fourth transistor.

7. The gate driving circuit according to claim 4, wherein: The pull-up control module includes: a sixth transistor, one of a source and a drain of the sixth transistor being connected to the high potential line, and a gate of the sixth transistor being connected to the first driving line; and a seventh transistor, one of the source / drain of the seventh transistor is connected to the other of the source / drain of the sixth transistor, the other of the source / drain of the seventh transistor is connected to the pull-up node, and a gate of the seventh transistor is connected to the gate of the sixth transistor.

8. The gate driving circuit according to claim 7, wherein: The pull-up control module further includes: an eighth transistor, wherein one of a source and a drain of the eighth transistor is connected to the input terminal of the pull-up module and the high potential line, and a gate of the eighth transistor is connected to the pull-up node and the control terminal of the pull-up module; a ninth transistor, wherein one of a source and a drain of the ninth transistor is connected to the pull-up node, the other of the source and the drain of the ninth transistor is connected to the other of the source and the drain of the eighth transistor, and the gate of the ninth transistor is connected to the second driving line; a tenth transistor, wherein one of the source and the drain of the tenth transistor is connected to the other of the source and the drain of the ninth transistor, the other of the source and the drain of the tenth transistor is connected to the first low potential line, and the gate of the tenth transistor is connected to the gate of the ninth transistor; a first capacitor, one end of the first capacitor being connected to the pull-up node, and the other end of the first capacitor being connected to the output end of the pull-up module and the output end of the pull-down module; an eleventh transistor, one of a source and a drain of the eleventh transistor being connected to the pull-up node, the other of the source and the drain of the eleventh transistor being connected to the other of the source and the drain of the eighth transistor, and a gate of the eleventh transistor being connected to the pull-down node; and a twelfth transistor, one of the source / drain of the twelfth transistor is connected to the other of the source / drain of the eleventh transistor, the other of the source / drain of the twelfth transistor is connected to the first low potential line, and the gate of the twelfth transistor is connected to the gate of the eleventh transistor.

9. The gate driving circuit according to claim 8, wherein: The pull-down control module includes: a thirteenth transistor, wherein one of a source and a drain of the thirteenth transistor is connected to the second driving line, and a gate of the thirteenth transistor is connected to the stage transfer line; a second capacitor, one end of the second capacitor being connected to the other of the source and the drain of the thirteenth transistor; and a fourteenth transistor, wherein one of the source / drain of the fourteenth transistor is connected to the other end of the second capacitor and the high potential line, the gate of the fourteenth transistor is connected to the other of the source / drain of the thirteenth transistor, the other of the source / drain of the fourteenth transistor is connected to the pull-down node and the control end of the pull-down module, and the input end of the pull-down module is connected to the first low potential line or the second low potential line.

10. A display panel, characterized in that: The gate drive circuit comprises the gate drive circuit according to any one of claims 1 to 9.

11. A driving method, characterized in that: The driving method includes: The pull-up control module controls the potential of the pull-up node according to the first driving signal; The pull-down control module controls the potential of the pull-down node according to the second driving signal and the level transmission signal; The voltage stabilizing module reduces the leakage current of the pull-down node in a high potential state and maintains the level of the pull-down node in a low potential state according to the first driving signal and the potential of the pull-up node; The pull-up module pulls up and maintains the potential of the driving signal according to the potential of the pull-up node; The pull-down module pulls down and maintains the potential of the driving signal according to the potential of the pull-down node.

12. The driving method according to claim 11, wherein: The driving method further includes: The scan control driver generates a rising edge of the first driving signal at a first moment; The scan control driver generates a first rising edge of the level transfer signal in a first time range; The scan control driver configures the first time to be within the first time range.

13. The driving method according to claim 12, wherein: The driving method further includes: The scanning control driver generates a rising edge of the second driving signal at a second moment, where the second moment is later than the first moment in a frame and is outside the first time range; The scan control driver generates a second rising edge of the level transfer signal at the second moment.

14. The driving method according to claim 13, wherein: The driving method further includes: The gate drive circuit is configured so that the rising edge of the drive signal is within the first time range; The gate driving circuit configures the falling edge of the driving signal to occur at the second moment.

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