Method for manufacturing an insulated gate bipolar transistor

Abstract

The application relates to a preparation method of an insulated gate bipolar transistor, comprising the following steps: providing a first substrate and a second substrate, wherein the first substrate comprises a first surface; implanting the first substrate from the first surface to form a back structure of the insulated gate bipolar transistor; forming a sacrificial layer on the second substrate; bonding the second substrate to the side of the first substrate with the back structure through the sacrificial layer; forming a front structure of the insulated gate bipolar transistor on the side of the first substrate away from the second substrate; and removing the sacrificial layer to separate the second substrate from the first substrate. The application makes the manufacturing process of the back structure simpler and reduces the equipment cost for manufacturing the back structure of the insulated gate bipolar transistor.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and particularly relates to a preparation method of an insulated gate bipolar transistor. BACKGROUND

[0002] With the development of semiconductor technology, a traditional reverse-conducting insulated gate bipolar transistor structure has the characteristic of extremely thin thickness.

[0003] However, the traditional reverse-conducting insulated gate bipolar transistor structure has the problems of excessively high difficulty of back surface process (including high-energy injection and high-temperature annealing) and expensive processing equipment of the back surface structure. SUMMARY

[0004] Therefore, it is necessary to provide a preparation method of an insulated gate bipolar transistor for solving the problems of excessively high difficulty of back surface process and expensive processing equipment of the back surface structure in the prior art.

[0005] In order to achieve the above object, the present application provides a preparation method of an insulated gate bipolar transistor, which comprises the following steps:

[0006] injecting a first surface of a first substrate to form a back surface structure of the insulated gate bipolar transistor;

[0007] forming a sacrificial layer on a second substrate;

[0008] bonding the second substrate to a side of the first substrate on which the back surface structure is formed through the sacrificial layer;

[0009] forming a front surface structure of the insulated gate bipolar transistor on a side of the first substrate away from the second substrate;

[0010] removing the sacrificial layer to separate the second substrate from the first substrate.

[0011] The preparation method of the insulated gate bipolar transistor is used for first forming the back surface structure of the insulated gate bipolar transistor on the first surface of the first substrate and then forming the front surface structure of the insulated gate bipolar transistor on the first substrate, so that the manufacturing process of the back surface structure is simpler and the cost of equipment for manufacturing the back surface structure of the insulated gate bipolar transistor is reduced.

[0012] The sacrificial layer can facilitate the bonding and separation of the first substrate and the second substrate. Meanwhile, the sacrificial layer separates the back surface structure formed on the first substrate and the second substrate, so that the back surface structure formed on the first substrate can be effectively prevented from being damaged in the process of removing the second substrate.

[0013] In one embodiment, the sacrificial layer includes a first oxide layer, and forming the sacrificial layer on the second substrate includes:

[0014] thermally oxidizing the second substrate to form the first oxide layer on a surface of the second substrate.

[0015] In one embodiment, removing the sacrificial layer to separate the second substrate from the first substrate includes:

[0016] thinning the second substrate away from the first substrate;

[0017] removing a remaining portion of the second substrate by a first etching solution;

[0018] removing the sacrificial layer by a second etching solution.

[0019] In one embodiment, the thinning the second substrate away from the first substrate includes:

[0020] mechanically thinning the second substrate away from the first substrate.

[0021] In one embodiment, implanting the first substrate from a first surface thereof to form a back structure of the insulated gate bipolar transistor includes:

[0022] implanting ions into the first substrate from a first surface thereof to form a buffer layer;

[0023] forming an implantation blocking layer on a surface of the buffer layer, the implantation blocking layer having an opening therein exposing the buffer layer;

[0024] implanting ions into the buffer layer based on the implantation blocking layer to form an N-type shorting region at a bottom of the buffer layer;

[0025] removing the implantation blocking layer and implanting ions into the buffer layer and the N-type shorting region to form a P-type doped region at the bottom of the buffer layer. In one embodiment, forming the implantation blocking layer on the surface of the buffer layer includes:

[0026] forming an implantation blocking material layer on the buffer layer;

[0027] forming a patterned photoresist on the implantation blocking material layer;

[0028] etching the implantation blocking material layer based on the patterned photoresist to form the implantation blocking layer on the surface of the buffer layer.

[0029] In one of the embodiments, the injection barrier material layer comprises a second oxide layer, and the forming of the injection barrier material layer on the buffer layer comprises the following steps:

[0030] performing a thermal oxidation process on the buffer layer to form the second oxide layer on the surface of the buffer layer.

[0031] In one of the embodiments, the injection barrier material layer further comprises a third oxide layer, and before the forming of the buffer layer on the first surface of the first substrate, the method further comprises the following steps:

[0032] performing a thermal oxidation process on the first substrate to form the third oxide layer on the first surface of the first substrate;

[0033] the third oxide layer has a thickness smaller than that of the second oxide layer, and after the thermal oxidation process on the buffer layer, the second oxide layer is located between the third oxide layer and the buffer layer.

[0034] In one of the embodiments, before the forming of the front structure of the insulated gate bipolar transistor on the side of the first substrate away from the first surface, the method comprises the following steps:

[0035] thinning the side of the first substrate away from the second substrate.

[0036] In one of the embodiments, the thinning of the side of the first substrate away from the second substrate comprises the following steps:

[0037] mechanically thinning the side of the first substrate away from the second substrate;

[0038] chemically mechanically polishing the mechanically thinned first substrate. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0040] Figure 1 a flow chart of the method for manufacturing the insulated gate bipolar transistor provided in an embodiment;

[0041] Figures 2 to 12 a cross-sectional structure schematic diagram of the structure obtained in the method for manufacturing the insulated gate bipolar transistor provided in an embodiment;

[0042] Reference numerals: 10-first substrate, 20-back structure, 21-buffer layer, 22-N-type short-circuit region, 23-P-type doped region, 31-injection barrier material layer, 311-second oxide layer, 312-third oxide layer, 30-injection barrier layer, 40-patterned photoresist, 50-collector layer, 60-front structure, 70-second substrate, 80-sacrificial layer. DETAILED DESCRIPTION

[0043] For the purposes of this application, reference will be made to the accompanying drawings in which embodiments of the application are illustrated. The application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the application to those skilled in the art.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0045] It should be understood that when an element or layer is referred to as being "on" or "adjacent" or "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on," "directly adjacent," "directly connected" or "directly coupled" to another element or layer, there are no intervening elements or layers present. It will be appreciated that, although terms such as first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0046] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0047] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0048] In one embodiment, see Figure 1 A method for fabricating an insulated gate bipolar transistor is provided, comprising the following steps:

[0049] Step S10: Provide a first substrate 10 and a second substrate 70, wherein the first substrate 10 includes a first surface;

[0050] Step S20: Implantation is performed on the first surface of the first substrate 10 to form the back structure 20 of the insulated gate bipolar transistor; Step S30: A sacrificial layer 80 is formed on the second substrate 70.

[0051] In step S40, the second substrate 70 is bonded to the side of the first substrate 10 where the back structure 20 is formed through the sacrificial layer 80;

[0052] Step S60: An insulated gate bipolar transistor front structure 60 is formed on the side of the first substrate 10 away from the second substrate 70.

[0053] Step S70: Remove the sacrificial layer 80 and separate the second substrate 70 from the first substrate 10.

[0054] In step S10, the first substrate 10 and / or the second substrate 70 may be, but are not limited to, silicon wafers.

[0055] The first substrate 10 is used to carry and form a device structure of an insulated gate bipolar transistor. A front surface of the first substrate 10 can be a smooth surface, which can be a first surface. The second substrate 70 is used to support the first substrate 10 and a back surface structure 20 of the insulated gate bipolar transistor formed on the first substrate 10, so as to further process a front surface structure 60 of the insulated gate bipolar transistor.

[0056] As an example, the first substrate 10 can be an N-type zone-fusion single crystal wafer, which has a surface area of eight inches and a thickness of 700 μm, and a resistivity of 100 Ω*cm. The second substrate 70 can have a thickness of 700 μm.

[0057] In step S20, referring to Figure 7 , the back surface structure 20 of the insulated gate bipolar transistor includes a buffer layer 21, an N-type short circuit region 22, and a P-type doped region 23.

[0058] Specifically, when implanting the first substrate 10, phosphorus ions can be implanted from the first surface of the first substrate 10 first to form the buffer layer 21. Then, arsenic ions are implanted to the buffer layer 21 to form the N-type short circuit region 22. Finally, boron ions are implanted to the buffer layer 21 and the N-type short circuit region 22 to form the P-type doped region 23.

[0059] In step S30, referring to Figure 8 , the material of the sacrificial layer 80 can include silicon dioxide, silicon nitride, silicon oxynitride, or the like. The formation method of the sacrificial layer 80 can include thermal oxidation or deposition, etc. The deposition process can include one or more of chemical vapor deposition (CVD), atomic layer deposition (ALD), high-density plasma deposition (HDP), plasma-enhanced deposition, spin-on dielectric (SOD), and the like, but is not limited thereto.

[0060] In step S40, referring to Figure 8 , the second substrate 70 is bonded to the first substrate 10. Specifically, the sacrificial layer 80 formed on the surface of the second substrate 70 is bonded to the back surface structure 20 formed on the first substrate 10.

[0061] In step S60, referring to Figure 9 , the front surface structure 60 of the insulated gate bipolar transistor is formed on the side of the first substrate 10 away from the second substrate 70. The formation method of the front surface structure 60 is the same as that in the conventional technology, which will not be described here.

[0062] In step S70, referring to Figures 9 to 11 , the second substrate 70, as a support substrate, needs to be separated from the first substrate 10 in this step. Specifically, the sacrificial layer 80 can be removed by wet etching and / or dry etching, etc., and the first substrate 10 can be separated from the second substrate 70.

[0063] Referring to Figure 12 , step S70 can further include:

[0064] Step S80, forming the collector layer 50.

[0065] Specifically, the collector layer 50 can be formed by sputtering metal, and the metal can be one or more of aluminum, titanium, nickel, and silver.

[0066] In the embodiment, the back surface structure 20 of the insulated gate bipolar transistor is completed on the first surface of the first substrate 10 first, and the front surface structure 60 of the insulated gate bipolar transistor is completed on the first substrate 10 later, so that the manufacturing process of the back surface structure 20 is simpler, and the cost of equipment for manufacturing the back surface structure 20 of the insulated gate bipolar transistor is reduced.

[0067] The sacrificial layer 80 facilitates the bonding and separation of the first substrate 10 and the second substrate 70. At the same time, the sacrificial layer 80 separates the second substrate 70 from the back surface structure 20 formed on the first substrate 10, so that the back surface structure 20 formed on the first substrate 10 can be effectively prevented from being damaged during the removal of the second substrate 70.

[0068] In one embodiment, the sacrificial layer 80 includes a first oxide layer, and step S30 includes the following steps:

[0069] Step S31, performing a thermal oxidation treatment on the second substrate 70 to form a first oxide layer on the surface of the second substrate 70.

[0070] For example, the thickness of the first oxide layer can be to For example, it can be

[0071] Specifically, after the thermal oxidation treatment on the second substrate 70, the first oxide layer can be formed on both the front surface and the back surface of the second substrate 70. Then, one of the surfaces (the front surface or the back surface) can be selected to bond the first substrate 10 through the first oxide layer of the surface.

[0072] Of course, the formation method of the sacrificial layer 80 is not limited to this, and in other cases, the sacrificial layer 80 can also be formed by deposition, etc., which is not limited herein.

[0073] In one embodiment, referring to Figures 9 to 11S70, comprising the following steps:

[0074] S71, thinning the second substrate 70 away from the first substrate 10;

[0075] S72, removing the remaining part of the second substrate 70 by the first etching solution.

[0076] S73, removing the sacrificial layer 80 by the second etching solution.

[0077] In step S71, please refer to Figure 9 As an example, the mechanical thinning method can be used to thin the second substrate 70 away from the first substrate 10. Of course, other methods (such as chemical mechanical polishing) can also be used to thin the second substrate 70 away from the first substrate 10, which is not limited here.

[0078] In step S72, please refer to Figure 10 The remaining part of the second substrate 70 can be removed by wet etching with the first etching solution. At this time, the first etching solution is a chemical solution that has an etching effect on the second substrate 70.

[0079] In step S73, please refer to Figure 11 The sacrificial layer 80 can be removed by wet etching with the second etching solution. At this time, the second etching solution is a chemical solution that has an etching effect on the sacrificial layer 80. The first etching solution and the second etching solution are different solutions.

[0080] For example, when the sacrificial layer 80 is a silicon dioxide layer, hydrofluoric acid (HF) can be selected as the second etching solution.

[0081] In this embodiment, the second substrate 70 is first thinned, which can quickly reduce the thickness of the second substrate 70. After the second substrate 70 is thinned, the remaining part of the second substrate 70 can be removed by the first etching solution, which can avoid over-thinning and mechanical damage to the back structure 20 on the first substrate 10.

[0082] At the same time, the second substrate 70 and the first substrate 10 have a sacrificial layer 80. By removing the sacrificial layer 80 with the second etching solution, the first etching solution can be effectively prevented from etching the remaining part of the second substrate 70 while also etching the back structure 20 of the first substrate 10, thereby better protecting the back structure 20 of the first substrate 10.

[0083] In one embodiment, please refer to Figures 3 to 7 S20, comprising the following steps:

[0084] S21, please refer to Figure 3The first surface of the first substrate 10 is ion implanted to form a buffer layer 21;

[0085] In step S22, referring to Figure 6 An implantation blocking layer 30 is formed on the surface of the buffer layer 21, and the implantation blocking layer 30 has an opening exposing the buffer layer 21;

[0086] In step S23, referring to Figure 6 and Figure 7 The buffer layer 21 is ion implanted based on the implantation blocking layer 30 to form an N-type short circuit region 22 at the bottom of the buffer layer 21.

[0087] In step S24, referring to Figure 7 The implantation blocking layer 30 is removed, and the buffer layer 21 and the N-type short circuit region 22 are ion implanted to form a P-type doped region 23 at the bottom of the buffer layer 21.

[0088] In step S21, the first surface of the first substrate 10 can be implanted with phosphorus elements, specifically, the implantation dose can be 5E12-3E13 / cm 2 , and the implantation energy can be 80-120KeV. Then, the first substrate 10 can be sent into a high-temperature furnace tube for thermal process promotion to form the buffer layer 21.

[0089] In step S22, a patterned photoresist 40 is formed on the buffer layer 21, and the implantation blocking layer 30 is formed based on the patterned photoresist, and the implantation blocking layer 30 has an opening exposing the buffer layer 21 and defining the size and position of the N-type short circuit region 22.

[0090] In step S23, the buffer layer 21 can be implanted with arsenic ions based on the implantation blocking layer 30, and the implantation dose can be 1E15-3E15 / cm 2 , and the implantation energy can be 100-150KeV, so as to form the N-type short circuit region 22 at the bottom of the buffer layer 21.

[0091] In step S24, the implantation blocking layer 30 can be removed by etching first. Then, the buffer layer 21 and the N-type short circuit region 22 can be implanted with boron ions on the whole surface, and the implantation dose can be 1E13-5E13 / cm 2 , and the implantation energy can be 30-50KeV, so as to form the P-type doped region 23 at the bottom of the buffer layer 21.

[0092] In this embodiment, the implantation blocking layer 30 with the implantation opening formed on the surface of the buffer layer 21 can facilitate the formation of the N-type short circuit region 22.

[0093] In one embodiment, referring to Figures 4 to 6Step S22 includes the following steps:

[0094] Step S221, refer to Figure 4 forming an injection barrier material layer 31 on the buffer layer 21;

[0095] Step S222, refer to Figure 5 forming a patterned photoresist 40 on the injection barrier material layer 31;

[0096] Step S223, refer to Figure 6 etching the injection barrier material layer 30 based on the patterned photoresist 40 to form the injection barrier layer 30 on the surface of the buffer layer 21.

[0097] In step S221, refer to Figure 4 The thickness of the second oxide layer 311 can be greater than 1 μm. For example, the thickness of the second oxide layer 311 can be 1 μm to 1.5 μm.

[0098] As an example, the injection barrier material layer 30 can include the second oxide layer 311. At this time, the present step can include: performing a thermal oxidation process on the buffer layer 21 to form the second oxide layer 311 on the surface of the buffer layer 21.

[0099] Specifically, at this time, after ion implantation from the first surface of the first substrate 10, the first substrate 10 can be first sent into a high-temperature furnace tube to perform a thermal process push trap to form the buffer layer 21, and then the buffer layer 21 after the push trap is performed in the high-temperature furnace tube to perform a thermal oxidation process, thereby forming the second oxide layer 311.

[0100] Of course, the injection barrier material layer 30 can also be formed by other means, for example, by deposition, which is not limited here.

[0101] In step S222, refer to Figure 5 First, a photoresist is coated on the injection barrier layer 30, and then the photoresist is exposed and developed to form the patterned photoresist 40.

[0102] In step S223, refer to Figure 6 The injection barrier material layer 30 can be dry etched based on the patterned photoresist 40, thereby forming the injection barrier layer 30 with controllable opening shape.

[0103] In the present embodiment, the injection barrier layer 30 with injection openings is simply and effectively formed by photolithography, etching and other processes.

[0104] In one embodiment, refer to Figures 2 to 3 The injection barrier material layer 31 further includes a third oxide layer 312, and the step S21 further includes the following steps:

[0105] Referring to Figure 2 The first substrate 10 is subjected to thermal oxidation to form a third oxide layer 312 on the first substrate 10.

[0106] After the first substrate 10 is processed, the front side and the back side of the first substrate 10 can both form the third oxide layer 312.

[0107] Referring to Figure 3 The thickness of the third oxide layer 312 is less than the thickness of the second oxide layer 311. Specifically, the thickness of the third oxide layer 312 can be to For example, it can be The thickness of the second oxide layer 311 can be greater than 1 μm, for example.

[0108] At this time, due to the presence of the third oxide layer 312, the tunnel effect can be effectively prevented during the ion implantation process in step S21, so that the thickness of the buffer layer 21 formed by implantation is more uniform. At the same time, the third oxide layer 312 can effectively prevent damage to the first substrate 10 during implantation.

[0109] At the same time, due to the small thickness of the third oxide layer 312, oxidation can pass through the third oxide layer 312 into the buffer layer 21. Therefore, after the third oxide layer 312 and the buffer layer 21 are formed, subsequent steps can continue to form the second oxide layer 311 on the surface of the buffer layer 21 by thermal oxidation.

[0110] After the buffer layer 21 is subjected to thermal oxidation, the second oxide layer 311 is located between the third oxide layer 312 and the buffer layer 21.

[0111] In one embodiment, before step S60, the following steps are included:

[0112] Step S50, thinning the side of the first substrate 10 away from the second substrate 70, referring to Figure 7 and Figure 8 .

[0113] In this embodiment, thinning the first substrate 10 can reduce the overall thickness of the chip to some extent, so that a smaller thickness of the reverse conducting insulated gate bipolar transistor structure can be formed.

[0114] In one embodiment, step S50 includes the following steps:

[0115] Step S51, mechanically thinning the side of the first substrate 10 away from the second substrate 70;

[0116] Step S52, chemically mechanically polishing the first substrate 10 after mechanical thinning.

[0117] In step S51, the first substrate 10 is mechanically thinned, which can reduce the cost of thinning.

[0118] In step S52, the surface of the first substrate 10 is planarized by a chemical mechanical polishing process, which can optimize the working performance and reliability of the device.

[0119] In the present embodiment, the first substrate 10 is thinned to effectively reduce the thickness of the chip. Furthermore, the mechanically thinned first substrate 10 is subjected to chemical mechanical polishing to form a smooth and planar surface on which the front surface structure 60 of the insulated gate bipolar transistor can be better formed.

[0120] It should be understood that, although Figure 1 the steps in the flowchart of FIG. 1 are shown in a sequential order, such that each step is performed after another, the steps do not have to be performed in this order. Unless explicitly stated, the steps are not necessarily performed in the order shown in the flowchart. Moreover, Figure 1 at least a part of the steps in the flowchart of FIG. 1 can include a plurality of steps or stages, which are not necessarily performed at the same time, but can be performed at different times. The steps or stages can not necessarily be performed in sequence, but can be performed alternately or in rotation with at least a part of the other steps or the steps or stages in the other steps.

[0121] In the description of the present specification, the description referring to the terms "some embodiments", "other embodiments", "ideal embodiments", and the like means that the specific features, structures, materials, or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example.

[0122] The technical features of the above-described embodiments can be combined in any manner. For brevity, not all possible combinations of the technical features of the above-described embodiments are described, but it should be understood that any combination of the technical features is within the scope of the present application as long as the combination does not result in a contradiction.

[0123] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent application scope. It should be noted that, for those skilled in the art, several modifications and improvements can be made without departing from the concept of the present application, and these are within the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A method for fabricating an insulated gate bipolar transistor, characterized in that, Includes the following steps: A first substrate and a second substrate are provided, wherein the first substrate includes a first surface; To form the back structure of the insulated gate bipolar transistor by implanting ions into the first surface of the first substrate, the method includes: ion implantation into the first surface of the first substrate to form a buffer layer; and forming an implantation barrier layer on the surface of the buffer layer, wherein the implantation barrier layer has an opening that exposes the buffer layer. A sacrificial layer is formed on the second substrate; The second substrate is bonded to the side of the first substrate where the back structure is formed through the sacrificial layer; The front structure of the insulated gate bipolar transistor is formed on the side of the first substrate away from the second substrate; Remove the sacrificial layer to separate the second substrate from the first substrate; The process of forming an injection barrier layer on the surface of the buffer layer includes: An injection barrier material layer is formed on the buffer layer; the injection barrier material layer includes a second oxide layer and a third oxide layer; Before forming a buffer layer on the first surface of the first substrate, the following steps are also included: The first substrate is subjected to thermal oxidation treatment to form the third oxide layer on the first surface of the first substrate; The thickness of the third oxide layer is less than that of the second oxide layer. After the buffer layer is subjected to thermal oxidation treatment, the second oxide layer is located between the third oxide layer and the buffer layer.

2. The method for fabricating an insulated gate bipolar transistor according to claim 1, characterized in that, The sacrificial layer includes a first oxide layer, and the sacrificial layer is formed on the second substrate, including the following steps: The second substrate is subjected to thermal oxidation treatment to form the first oxide layer on the surface of the second substrate.

3. The method for fabricating an insulated-gate bipolar transistor according to claim 1, characterized in that, Removing the sacrificial layer and separating the second substrate from the first substrate includes the following steps: The side of the second substrate furthest from the first substrate is thinned; The remaining portion of the second substrate is removed using the first etching solution; The sacrificial layer is removed by a second etchant.

4. The method for fabricating an insulated gate bipolar transistor according to claim 3, characterized in that, The thinning of the side of the second substrate away from the first substrate includes: Mechanical thinning is performed on the side of the second substrate away from the first substrate.

5. The method for fabricating an insulated-gate bipolar transistor according to claim 1, characterized in that, Implantation from the first surface of the first substrate to form the back structure of the insulated gate bipolar transistor further includes the following steps: Ion implantation is performed on the buffer layer based on the implantation barrier layer to form an N-type short-circuit region at the bottom of the buffer layer; The implantation barrier layer is removed, and ion implantation is performed on the buffer layer and the N-type short-circuit region to form a P-type doped region at the bottom of the buffer layer.

6. The method for fabricating an insulated gate bipolar transistor according to claim 5, characterized in that, The process of forming an injection barrier layer on the surface of the buffer layer also includes the following steps: A patterned photoresist is formed on the injection barrier material layer; The injection barrier layer is formed on the surface of the buffer layer by etching the injection barrier material layer using patterned photoresist.

7. The method for fabricating an insulated-gate bipolar transistor according to claim 6, characterized in that, Forming an injection barrier material layer on the buffer layer includes the following steps: The buffer layer is subjected to thermal oxidation treatment to form a second oxide layer on the surface of the buffer layer.

8. The method for fabricating an insulated-gate bipolar transistor according to claim 1, characterized in that, Before forming the front structure of the insulated gate bipolar transistor on the side of the first substrate away from the first surface, the following steps are included: The side of the first substrate away from the second substrate is thinned.

9. The method for fabricating an insulated-gate bipolar transistor according to claim 8, characterized in that, Thinning the side of the first substrate away from the second substrate includes the following steps: The side of the first substrate furthest from the second substrate is mechanically thinned; The first substrate, after mechanical thinning, is subjected to chemical mechanical polishing.

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