Structure for improved mechanical, electrical and / or thermal performance

Abstract

Embodiments of the present application relate to structures for improved mechanical, electrical, and / or thermal performance. In some aspects, the present disclosure relates to a module for improved mechanical, electrical, or thermal performance. In some embodiments, the module includes a bottom surface, a side surface, a first solder bump disposed on the bottom surface, and a second solder bump disposed on the bottom surface. In some embodiments, the bottom surface extends in a first lateral direction and a second lateral direction perpendicular to the first lateral direction. In some embodiments, the side surface extends in a vertical direction perpendicular to the first lateral direction and the second lateral direction. In some embodiments, the second solder bump is adjacent to the side surface. In some embodiments, the first solder bump has a first length in the first lateral direction. In some embodiments, the second solder bump has a second length in the first lateral direction. In some embodiments, the first length is greater than the second length.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims the benefit of and priority to U.S. Provisional Patent Application No. 63 / 272,994, filed October 28, 2021, entitled “Structures for Improved Mechanical, Electrical, and Thermal Performance,” and U.S. Provisional Patent Application No. 63 / 221,564, filed July 14, 2021, entitled “Structures for Improved Mechanical, Electrical, and Thermal Performance,” each of which is incorporated by reference in its entirety for all purposes. TECHNICAL FIELD

[0003] Embodiments of the present application generally relate to the field of semiconductors, and in particular to structures for improved mechanical, electrical, and / or thermal performance. BACKGROUND

[0004] Semiconductor packages with electronic components are commonly used to operate compact consumer devices, such as mobile phones, personal computers, tablets, and the like. Many packages commonly include a substrate with both passive and active circuit components, such as an integrated circuit (IC) chip connected thereto. SUMMARY

[0005] An embodiment of the present application provides a module comprising: a bottom surface extending in a first lateral direction and a second lateral direction perpendicular to the first lateral direction; a side surface extending in a vertical direction perpendicular to the first lateral direction and the second lateral direction; a first solder bump disposed on the bottom surface, wherein the first solder bump has a first length in the first lateral direction; and a second solder bump disposed on the bottom surface, wherein the second solder bump has a second length in the first lateral direction, wherein the first length is greater than the second length, wherein the second solder bump is adjacent to the side surface.

[0006] Another embodiment of the present application provides a chip set comprising: a printed circuit board (PCB) comprising a first surface extending in a first lateral direction and a second lateral direction perpendicular to the first lateral direction; and a module comprising: a second surface extending in the first lateral direction and the second lateral direction, wherein the second surface is disposed above the first surface; and a solder bump disposed between the first surface and the second surface, wherein the solder bump is one or more of an ellipse, a rectangle, or an L-shape.

[0007] Another embodiment of the present application provides a method comprising: combining a first pad for a first solder bump and a second pad for a second solder bump into a single pad for both solder bumps; adding a solder material to the single pad; applying the two solder bumps; and reflowing the solder material and the two or more solder bumps to produce a custom sized solder bump. BRIEF DESCRIPTION OF DRAWINGS

[0008] Various objects, aspects, features, and advantages of the present disclosure will become more fully understood and appreciated by referring to the detailed description, along with the accompanying drawings, in which like reference numerals refer to like elements throughout. In the drawings, similar reference characters denote similar elements throughout the several views.

[0009] Figure 1 is a cross-sectional view schematic of a module according to some embodiments of the present disclosure.

[0010] Figure 2 illustrates a cross-sectional view schematic of a chip set according to some embodiments of the present disclosure.

[0011] Figures 3A to 3C is a top plan view schematic of various modules according to some embodiments of the present disclosure.

[0012] Figure 4 illustrates a flow of operations for providing custom bumps on a module according to some embodiments.

[0013] Figure 5A is a top plan view schematic of a circuit board including a solder material on a single pad according to some embodiments.

[0014] Figure 5B is a top plan view schematic of a circuit board including a solder material on a single pad and two solder bumps according to some embodiments.

[0015] Figure 5C is a top plan view schematic of a circuit board including a custom sized solder bump according to some embodiments.

[0016] Details of various embodiments of methods and systems are described in the following detailed description and in the drawings. DETAILED DESCRIPTION

[0017] The following description provides examples, and is not intended to limit the scope, applicability or configuration of the claims. Rather, the ensuing description will provide those skilled in the art with an enabling description of the described embodiments. It is understood that various changes can be made in the function and arrangement of elements without departing from the spirit and scope of the claims.

[0018] Semiconductor packages with electronic components are commonly used to operate compact consumer devices, such as mobile phones, personal computers, tablets, and the like. Many packages contain a substrate with both passive and active circuit components, such as an integrated circuit (IC) chip connected thereto. The substrate can be connected to a larger circuit board via one or a series of solder balls. When exposed to external forces, such as high g-forces imparted when dropped, the solder balls, especially at the edges and corners of the substrate, can experience stress-induced cracking. The term package includes packages, including but not limited to, single active components, more than one active component (e.g., a multi-chip module or a heterogeneous package), and any combination of one or more active components and one or more passive components.

[0019] The reduction in size of packages and components provided or used in electronic devices (e.g., smartphones, tablets, wearables, computers, sensors, access points, radios, network components, storage devices, etc.) can be achieved by placing some of the IC chips and passive circuit components on the backside of the package. This type of configuration can reduce the module size and the corresponding number of solder balls on the backside of the package, which can make the package more susceptible to mechanically stress-induced (e.g., impact, strain, force) damage. This susceptibility can increase primarily because there can be fewer solder balls available to accommodate the same mechanical stress as a package with more solder balls. Thus, similar stresses can be imparted on a smaller number of solder balls, concentrating the stress through the remaining solder balls. During mechanical deformation or warpage, the stress can peak at the corner bumps. Removing the bumps along the edges of the module can further reduce the module size, at the risk of increased peak stress at the corner bumps.

[0020] The solder balls can be designed such that there is a stress concentration point at the interface of the solder ball with the printed circuit board (PCB), the metal traces of the PCB, and / or the pads of the PCB. The stress concentration point can be formed due to the shape assumed by the solder material during deposition or attachment to the PCB, the metal traces, and / or the pads. The natural shape assumed by the solder material can form a relatively "sharp" corner (e.g., near orthogonal corner) at the interface between the solder material and the PCB. This can become a point of failure in a package with fewer solder balls as compared to a package with a uniform distribution of solder balls, a denser distribution of solder balls, or a conventional full complement of solder balls.

[0021] Some embodiments of the present disclosure address, mitigate, and / or solve challenges associated with stress. In some embodiments, the module includes unevenly sized bumps on a surface of the module (e.g., a set of smaller bumps and a set of larger bumps). For example, the corner bumps can be larger than the other bumps. The larger bumps can have a particular shape (e.g., oval, rectangular, diamond, and / or L-shaped). In some embodiments, the bumps reduce mechanical stress and improve thermal and electrical conductivity.

[0022] Applications may include RF and wireless applications such as cell phones. Additionally or alternatively, applications may include millimeter wave, optical, telematics (automotive), avionics, or any application where the product requires high mechanical, electrical, or thermal robustness.

[0023] Various embodiments disclosed herein relate to a module. In some embodiments, the module includes a bottom surface, a side surface, a first solder bump disposed on the bottom surface, and a second solder bump disposed on the bottom surface. In some embodiments, the bottom surface extends in a first lateral direction and a second lateral direction perpendicular to the first lateral direction. In some embodiments, the side surface extends in a vertical direction perpendicular to the first lateral direction and the second lateral direction. In some embodiments, the second solder bump is adjacent to the side surface. In some embodiments, the first solder bump has a first length in the first lateral direction. In some embodiments, the second solder bump has a second length in the first lateral direction. In some embodiments, the first length is greater than the second length. In some embodiments, the first length is at least twice the second length.

[0024] In some embodiments, the first solder bump is one or more of an oval, a rectangle, or an L. In some embodiments, the module includes a first edge, a second edge opposite the first edge, and a first distance from the first edge to the second edge, and wherein the first solder bump is a second distance from the first edge, wherein the second distance is less than 5% of the first distance.

[0025] In some embodiments, a first component is disposed on the bottom surface and a second component is disposed on the bottom surface. In some embodiments, the first component and the second component are spaced apart from each other by a distance less than twice the second length. In some embodiments, the first solder bump is disposed between the first component and the second component.

[0026] In some embodiments, the first solder bump has a first height in a vertical direction perpendicular to the first lateral direction and the second lateral direction. In some embodiments, the second solder bump has a second height in the vertical direction. In some embodiments, the first height is equal to the second height.

[0027] In some embodiments, the module includes a first via extending in a vertical direction to contact a first portion of the first solder bump and a second via extending in the vertical direction to contact a second portion of the first solder bump. In some embodiments, the first via is separated from the second via by a distance in the first lateral direction. In some embodiments, the vertical direction is perpendicular to the first lateral direction and the second lateral direction.

[0028] In some embodiments, the module includes a first pad disposed between the bottom surface and the first solder bump and a second pad disposed between the bottom surface and the second solder bump. In some embodiments, the first pad has a third length in the first lateral direction, the second pad has a fourth length in the first lateral direction, and the third length is greater than the second length.

[0029] In some embodiments, the module includes a first component further disposed on the bottom surface and a top surface opposite the bottom surface. In some embodiments, a silicon die is disposed on the top surface. In some embodiments, the module includes a first conductive structure electrically coupling the first solder bump to the silicon die and a second conductive structure electrically coupling the second solder bump to the silicon die.

[0030] Various embodiments disclosed herein relate to a chip set. In some embodiments, the chip set includes a printed circuit board (PCB) including a first surface extending in a first lateral direction and a second lateral direction perpendicular to the first lateral direction. In some embodiments, the chip set includes a module including a second surface extending in the first lateral direction and the second lateral direction and a solder bump disposed between the first surface and the second surface. In some embodiments, the solder bump is one or more of elliptical, rectangular, or L-shaped. In some embodiments, the second surface is disposed above the first surface. In some embodiments, an air gap is disposed between the first surface and the second surface.

[0031] In some embodiments, the module includes a first edge, a second edge opposite the first edge, and a first distance from the first edge to the second edge. In some embodiments, the solder bump is a second distance from the first edge. In some embodiments, the second distance is less than 5% of the first distance. In some embodiments, there are no intervening solder bumps between the first edge and the solder bump.

[0032] In some embodiments, the module includes a second solder bump disposed between the first surface and the second surface. In some embodiments, the solder bump has a length in the first lateral direction. In some embodiments, the second solder bump has a diameter in the first lateral direction. In some embodiments, the length is greater than the diameter. In some embodiments, the solder bump has a first height in a vertical direction perpendicular to the first lateral direction and the second lateral direction. In some embodiments, the second solder bump has a second height in the vertical direction. In some embodiments, the first height is equal to the second height.

[0033] Various embodiments disclosed herein relate to a method. The method includes merging a first pad for a first solder bump and a second pad for a second solder bump into a single pad for both solder bumps, adding a solder material to the single pad, dispensing the two solder bumps, and reflowing the solder material and the two or more solder bumps to produce a custom-sized solder bump.

[0034] In some embodiments, the pads include a single pad and additional pads. In some embodiments, adding a solder material to a single pad includes placing a template over the plurality of pads. In some embodiments, the template includes an opening that exposes the single pad. In some embodiments, adding a solder material to a single pad includes dispensing solder to the single pad exposed by the opening. In some embodiments, adding a solder material to the single pad includes three-dimensional (3D) printing the solder material. In some embodiments, the method includes removing a portion of the custom-sized solder bump using laser ablation.

[0035] Figure 1 A cross-sectional view of a module 100 is illustrated in accordance with some embodiments of the disclosure. The module 100 can be referred to as a package. The module 100 includes a first layer 104, a number of intermediate layers 108 disposed (e.g., contacting, vertically adjacent, etc.) on a first (e.g., lower, bottom, etc.) surface 112 of the first layer, and a second layer 116 disposed on a first (e.g., lower, bottom, etc.) surface 120 of the intermediate layers 108. In the cross-sectional view, the first surface 112 and the first surface 120 extend in a first direction (e.g., X-direction, lateral, etc.).

[0036] The first layer 104 includes a number of first pads 124 (e.g., contact pads, footprints). The module 100 includes a number of first solder bumps 128. Each of the first solder bumps 128 is disposed on a respective one of the first pads 124. Each of the first solder bumps 128 can be formed as a solder ball or other circular or spherical shape. In some embodiments, each of the solder bumps 128 has a length (e.g., diameter) in a range of about 25 um to 125 um, although any length value is within the scope of the present disclosure. Each of the first solder bumps 128 can include, but is not limited to, a lead alloy solder, a lead-free solder, a silver alloy solder, or any material that bonds one of a module, a silicon die, a passive component, or a PCB to a second of the module, the silicon die, the passive component, or the PCB.

[0037] The module 100 includes a silicon die 132 disposed on the number of first solder bumps 128. The silicon die includes a number of second pads 136, and each of the second pads 136 is disposed between a respective one of the first solder bumps 128 and a first (e.g., lower, bottom, etc.) surface 140 of the silicon die 132. In a cross-sectional view, the first surface 140 extends in the first direction. Although four first solder bumps 128, first pads 124, and second pads 136 are shown, a greater or fewer number of first solder bumps 128, first pads 124, and second pads 136 are within the scope of the present disclosure.

[0038] The module 100 includes an underfill (UF) layer 134 disposed between the first layer 104 and the silicon die 132. The UF layer 134 can protect the bond of the silicon die 132 to the first solder bumps 128. The UF layer 134 can include a dielectric material.

[0039] The second layer 116 includes a number of third pads 144 and a number of fourth pads 148. Each of the third pads 144 includes a length 146. Each of the fourth pads includes a length 150. The length 146 is greater than the length 150. For example, the length 146 can be at least two, three, or four times greater than the length 150, although any ratio of the length 146 to the length 150 is within the scope of the present disclosure. In some embodiments, each of the third pads 144 is a single conductive structure (e.g., including a uniform conductive material), while in other embodiments, each of the third pads 144 is a collection of multiple pads with a space (e.g., a dielectric material) between each of the multiple pads. In some embodiments, each of the third pads 144, the fourth pads 148, the first pads 124, and the second pads 136 includes a conductive material.

[0040] The module 100 includes a number of second solder bumps 152. Each of the second solder bumps 152 is disposed on a respective one of the third pads 144. Each of the second solder bumps 152 includes a height 156 and a length 160. In some embodiments, the length 160 is about 150 um to 600 um, although any length value is within the scope of the present disclosure. Each of the second solder bumps 152 can include the same material as each of the first solder bumps 128. Although one second solder bump 152, one third pad 144, one third solder bump 164, and one fourth pad 148 are shown, a greater number of each of the second solder bumps 152, the third pads 144, the third solder bumps 164, and the fourth pads 148 are within the scope of the present disclosure.

[0041] The module 100 includes a number of third solder bumps 164. Each of the third solder bumps 164 is disposed on a respective one of the fourth pads 148. Each of the third solder bumps 164 includes a length (e.g., diameter) 168 and a height 172. Each of the third solder bumps 164 can be similar to each of the first solder bumps 128, except that each of the third solder bumps 164 has a length of about 100 um to 250 um, although any length value is within the scope of the present disclosure. In some embodiments, there are no solder bumps disposed on the second layer 116 (e.g., disposed on a pad in the second layer 116 or on a pad associated with the second layer 116) having a length less than the length 168.

[0042] Each of the second solder bumps 152 can be larger than each of the third solder bumps 164. In some embodiments, the length 160 of one of the second solder bumps 152 is greater than the length 168. For example, the length 160 can be at least two, three, or four times greater than the length 168, although any ratio of the length 160 to the length 168 is within the scope of the present disclosure. The height 156 of each of the second solder bumps 152 can be equal to or substantially equal to the height 172 of each of the third solder bumps 164. Including the second solder bumps 152 in the module 100 can improve electrical, mechanical, and / or thermal integrity / performance as compared to including more instances of the third solder bumps 164 in place of the second solder bumps 152.

[0043] The second layer 116 includes a first (e.g., bottom) surface 175. The third pads 144 include a first (e.g., bottom) surface 177. In some embodiments, the first surface 175 is aligned (e.g., flat, no recess, etc.) with the first surface 177, while in other embodiments, the first surface 177 is recessed relative to the first surface 175. The first surface 175 and the first surface 177 can be referred to as (e.g., a single, uniform, etc.) surface.

[0044] The second layer 116 includes a second (e.g., side) surface 176. In the cross-sectional view, the second surface 176 extends in a second direction (e.g., Y-direction, vertical, etc.) that is perpendicular to the first direction. In some embodiments, the second surface 176 coincides with the first surface 175 to form an edge 179 (e.g., the edge 179 couples the first surface 175 and the second surface 176). In some embodiments, one of the second solder bumps 152 is adjacent to (e.g., closest to) the second surface 176 (e.g., the edge 179). That is, in some embodiments, no solder bump is disposed (e.g., interposed) between one of the second solder bumps 152 and the second surface 176.

[0045] One of the solder bumps 152 has a first surface 178 that extends in the second direction. The second surface 176 (e.g., the edge 179) and the first surface 178 are separated in the first direction by a first distance 180. In some embodiments, the distance 180 is less than the length 168 of each of the third solder bumps 164 (e.g., such that any of the third solder bumps 164 or any other solder bump having a length less than each of the second solder bumps 152 cannot be disposed between one of the second solder bumps 152 and the second surface 176). The distance 180 from the first surface 178 to the second surface 176 can be less than a predetermined distance, distance percentage, or distance ratio. For example, the distance 180 can be less than 10%, 5%, or 2.5% of a length 182 of the module 100 in the first direction, although any distance, distance percentage, or distance ratio is within the scope of the present disclosure.

[0046] The middle layer 108 includes a conductive structure 184 that electrically couples at least one of the first pads 124 to at least one of the third pads 144. The conductive structure 184 can include copper (Cu), aluminum (Al), cobalt (Co), ruthenium (Ru), tungsten (W), or any other various conductive materials. In some embodiments, the conductive structure 184 includes a first conductive structure 188 disposed on a first portion of one of the third pads 144, and a second conductive structure 192 disposed on a second portion of the one of the third pads 144.

[0047] In some embodiments, each of the first and second conductive structures 188, 192 includes a via 194 disposed on a respective portion of one of the third pads 144. In some embodiments, each via 194 is in a layer 195 of the intermediate layer 108. In some embodiments, the via 194 of the first conductive structure 188 is electrically coupled to the via 194 of the second conductive structure 192 through one of the third pads 144, but not through any other conductive material in the layer 195. In some embodiments, the via 194 of the first conductive structure 188 (e.g., the center of the via, the midpoint of the edges of the via, the widest point of the edges of the via, etc.) is electrically coupled to the via 194 of the second conductive structure 192 and separated by a distance 197.

[0048] The intermediate layer 108 includes a conductive structure 196 disposed on one of the fourth pads 148. In some embodiments, the conductive structure 196 includes the same material as the conductive structure 184. In some embodiments, the conductive structure 196 is electrically coupled to the first and second conductive structures 188, 192, while in other embodiments, the conductive structure 196 is not electrically coupled to (e.g., is electrically isolated from) the first and second conductive structures 188, 192. In some embodiments, a first portion of the intermediate layer 108 between the first and second conductive structures 188, 192, and a second portion of the intermediate layer 108 between the conductive structures 184, 196, include a dielectric material.

[0049] In some embodiments, the conductive structure 196 includes a via 198 disposed on one of the fourth pads 148. In some embodiments, the length (e.g., diameter), height, and gap of the via 198 are the same as the length, height, and gap of the via 194, where the length of each via is in the first direction and the height and gap of each via are in the second direction, and where the gap is the distance between the via and the nearest adjacent via. In some embodiments, the number of vias 194 disposed over one of the third pads 144 is greater than the number of vias 198 disposed over one of the fourth pads 148.

[0050] Figure 2A cross-sectional view of a chip set 200 according to some embodiments of the disclosure is illustrated. The chip set 200 includes the module 100 and a printed circuit board (PCB) 202 (e.g., a customer PCB, a motherboard, an interface board, a test suite board) coupled to the module 100. The PCB 202 includes a number of first pads 204 and a number of second pads 206 disposed. Each of the first pads 204 and the second pads 206 are disposed on a first surface 208 of the PCB 202, where the first (e.g., upper, top, etc.) surface 208 extends in a first direction. Each of the second solder bumps 152 is disposed on a respective one of the first pads 204, and each of the third solder bumps 164 is disposed on a respective one of the second pads 206.

[0051] In some embodiments, an air gap 210 (e.g., a cavity, air, etc.) is disposed between the PCB 202 and the second layer 116 of the module 100. In some embodiments, a UF layer (e.g., the UF layer 134) is not disposed between the PCB 202 and the second layer 116 of the module 100. UF can be very expensive and can negatively impact adjacent devices. UF can increase dielectric loss. UF can extend to adjacent devices on a motherboard, causing undesirable effects. For ultra-high frequency applications, adding UF can change, degrade the frequency response of the device, and increase assembly complexity and cost. UF can carry low halogen content, which can lead to electrochemical induced corrosion. In some embodiments, having an air gap 210 (rather than UF) between the module 100 and the PCB 202 improves assembly efficiency and high frequency performance, although other improvements are within the scope of the disclosure.

[0052] Figure 3A A top-down view of a module 300 according to some embodiments of the disclosure is illustrated. The module 300 includes a plurality of bumps 302 disposed on a surface 304 of the module 300. The plurality of bumps 302 is arranged in an array of rows extending in a first lateral direction and columns extending in a second lateral direction.

[0053] The plurality of bumps 302 includes solder bumps 306, solder bumps 307, solder bumps 308, solder bumps 309, and a number of solder bumps 314. Each of the solder bumps 306-309 is similar to the second solder bump 152 of Figure 1 . Each of the solder bumps 314 is similar to the third solder bump 164 of Figure 1 . Each of the solder bumps 306-309 occupies an area that would otherwise be occupied by two of the solder bumps 314. In other words, each of the solder bumps 306-309 extends across at least two rows or two columns. For example, the solder bump 306 extends across two columns, the solder bump 307 extends across two rows, the solder bump 308 extends across two columns, and the solder bump 309 extends across two rows.

[0054] Each of the solder bumps 306-309 is disposed on a corner portion of a surface of the module 100. Specifically, the solder bump 306 is within a first distance from the edge 310 of the module 300, and the solder bump 307 is within a first distance from the edge 311 of the module 300, and the solder bump 308 is within a first distance from the edge 312 of the module 300, and the solder bump 309 is within a first distance from the edge 313 of the module 300, and within a first distance from the edge 310 of the module 300. In some embodiments, the first distance can be the same as the first distance 180 of Figure 1 Each of the solder bumps 306-309 occupies a cross point of a row and a column closest to a corner of the module 100. In some embodiments, the solder bumps 306-309 can provide additional mechanical strength.

[0055] The module 300 includes several components (e.g., silicon components, silicon dies, etc.) disposed on the surface 304. The several components include component 316, component 318, component 320, component 322, and component 324. Although five components are shown in FIG. 3, a greater or lesser number of components included in the module 300 is within the scope of the present disclosure. In some embodiments, the module 300 can be a double-sided module. In other words, at least one component is disposed on a second surface (not shown) opposite the surface 304. The at least one component can be similar to the silicon die 132.

[0056] Some of the components can be separated by only one row or one column of solder bumps. For example, the components 316 and 318 are separated by only one column of solder bumps. In some embodiments, a distance between the component 316 and the component 318 is less than twice a length (e.g., the length 168) of one of the solder bumps 314 (e.g., so that only one column of solder bumps can be disposed between the component 316 and the component 318). The module 300 includes a solder bump 326 disposed between the components 316 and 318. In some embodiments, the solder bump 326 is similar to the second solder bump 152 of Figure 1 The solder bump 326 extends along the column separating the components 316 and 318. In some embodiments, the solder bump 326 improves electrical isolation between the components 316 and 318. Figure 1

[0057] A top-down view of a module 330 is illustrated in accordance with some embodiments of the present disclosure. In some embodiments, the module 330 is similar to the module 100 of Figure 3B Figure 3A ​Module 300, except that module 330 includes solder bump 332 and solder bump 334. Each of solder bumps 332-334 is similar to Figure 1 18. Each of solder bumps 332-334 may be within a predetermined distance of the component. For example, solder bump 332 is located in a column next to component 324 (e.g., one column away and on the same row), and solder bump 332 is located in a second column that is two columns away from component 324 and on the same row as component 324. In some embodiments, the distance between solder bump 332 and component 324 is less than 2.5%, 5%, or 10% of the length of module 330 (e.g., length 182). In some embodiments, each of solder bumps 332-334 is electrically coupled to a reference (e.g., ground, a ground plane, etc.). In some embodiments, the reference is coupled to component 324. Solder bumps 332-334 may improve heat dissipation from component 324.

[0058] Figure 3C Illustrate a top-down view of a module 350 according to some embodiments of the present disclosure. In some embodiments, the module 350 is similar to Figure 3A Module 300 is similar to module 350, except that module 350 includes solder bump 352 instead of solder bump 306, and includes solder bump 354 instead of solder bump 309. Each of solder bumps 352-354 is similar to solder bumps 306-309, except that solder bumps 306-309 are oval (e.g., as shown in FIG. Figure 3A and Figure 3C ), the solder bumps 352 are square (e.g., as shown in the top-down view of FIG. Figure 3C ), and the solder bump 354 is L-shaped (e.g., as shown in the top-down view of FIG. Figure 3C (as illustrated in the top-down view of ).

[0059] Solder bump 352 occupies an area that would otherwise be occupied by four of solder bumps 314 (e.g., a 2x2 array of solder bumps 314). Solder bump 354 occupies an area that would otherwise be occupied by three of solder bumps 314 (e.g., a column of two solder bumps 314 and an adjacent column of one solder bump 314 in the same row as one of the two solder bumps 314). Although module 350 includes oval, square, and L-shaped solder bumps, the solder bumps may be any of a variety of shapes while remaining within the scope of the present disclosure.

[0060] Figure 4 A method 400 for providing customized bumps on a module according to some embodiments is described. Depending on the embodiment, additional, fewer, or different operations may be performed in the method 400.

[0061] Briefly summarized, the method 400 includes merging two or more pads for two or more solder bumps into a single pad (at operation 410), selectively adding solder to the single pad (at operation 420), applying solder bumps to all pads (at operation 430), and reflowing the single pad (at operation 440).

[0062] In more detail, at operation 410, the method begins by merging two or more pads for (e.g., corresponding to, associated with) two or more solder bumps to create a single pad (e.g., the third pad 144 of FIG. 1). The single pad is a pad on which custom / special shaped solder bumps can be placed through the remaining operations. In some embodiments, the two or more pads are located at a corner of a module, such as the module 300 of FIG. 3. In some embodiments, the single pad has an oval shape, while in other embodiments, the single pad has an L-shape, a square shape, or a rectangular shape. Figure 1

[0063] At operation 420, the method continues by selectively adding solder material (e.g., solder paste) to the single pad or otherwise adjusting the solder material. In some embodiments, the solder material is selectively added to the single pad in order to create the same height as the smaller solder bumps after reflowing. In some embodiments, the solder material can be added directly to the solder bumps. In some embodiments, the solder material can be added using a three-dimensional (3D) printer (e.g., 3D printing the solder material and placing the 3D printed solder material on the solder bumps). In some embodiments, the solder material can be added by: (a) placing a stencil (e.g., a mask) over the plurality of pads (including the single pad), with one opening exposing the single pad (e.g., over it), and (b) applying solder to the single pad exposed by the opening. That is, the solder material can be aimed at the plurality of pads, but the stencil can prevent the solder material from being applied to those pads not exposed by the opening. Advantageously, adjusting the volume of solder material of the single pad can improve coplanarity (e.g., custom sized solder bumps and standard sized solder bumps can have the same height) and solder profile. Figure 5A An illustration of solder material 501 on the single pad 502 after operation 420 of the method 400 is shown according to some embodiments, while no solder material is on the pads 503.

[0064] At operation 430, the method continues by applying solder bumps (e.g., solder balls) to the single pad. In some embodiments, two or more solder bumps are applied to the single pad. In some embodiments, three or more solder bumps are applied to the single pad. In some embodiments, additional solder bumps are applied to additional pads, such as the fourth pad 148 of FIG. 1. Figure 1 Figure 1 ​​164. In some embodiments, a single pad is wider, longer, or wider and longer than each of the additional pads. Figure 5B Two examples of solder material and solder bumps 504 on a single pad 502 are illustrated following operation 430 of method 400, in accordance with some embodiments. In some embodiments, each of pads 503 also includes a solder bump 504.

[0065] At operation 440, the method creates custom sized solder bumps (eg, Figure 1 3 ). In some embodiments, the custom-sized solder bumps are located at the corners of a module (e.g., module 300 of FIG. 3 ). In some embodiments, the custom-sized solder bumps can be oval, L-shaped, rectangular, or various other shapes. In some embodiments, the custom-sized solder bumps are wider, longer, or both wider and longer than each of the additional solder bumps. In some embodiments, the custom-sized bumps have the same height as the additional solder bumps. Figure 5C A single solder bump 506 is illustrated after operation 430 of method 400 , in accordance with some embodiments.

[0066] In some embodiments, after reflow, a portion of the custom-sized solder bump is removed. In some embodiments, a portion of the larger bump is removed by laser ablation (eg, photoablation), which includes irradiating the larger bump with a laser beam.

[0067] Specific details are given in the description to provide a thorough understanding of the example embodiments. However, one of ordinary skill in the art will understand that the example embodiments can be practiced without these specific details. In other instances, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail in order to avoid obscuring the example embodiments.

[0068] While illustrative embodiments have been described in detail herein, it should be understood that the inventive concepts may be otherwise variously embodied and employed, and that the appended claims are intended to be interpreted to encompass such variations except to the extent limited by the prior art.

[0069] It will be understood that when an element, such as a region, layer, section, substrate, etc., is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present. Conversely, when an element is referred to as being "directly on" another element, there are no intervening elements present. It will be further understood that when an element is referred to as being "formed" or "established" on another element, it can be grown, deposited, etched, attached, connected, coupled, or otherwise prepared or manufactured on the other element or intervening elements.

[0070] Moreover, relative terms such as "lower" or "bottom" and "upper" or "top" can be used herein to describe one element's or feature's relationship to another element or feature as illustrated in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. By way of example, if a device in the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. The term "lower" can encompass both an "lower" and "upper" orientation. The terms "below" or "beneath" can refer to either an "below" or "above" orientation, depending upon the particular orientation of the device. Thus, the terms "below" or "beneath" should be interpreted as "below" or "above", depending on the particular orientation of the device.

[0071] The phrases "at least one", "one or more", "or", and "and / or", as used herein, are open-ended expressions that are both conjunctive and disjunctive in operation. For example, each of the expressions "at least one of A, B, and C", "at least one of A, B, or C", "one or more of A, B, and C", "one or more of A, B, or C" means A alone, B alone, C alone, A combined with B, A combined with C, B combined with C, or A combined with B combined with C. Similarly, "A, B, and / or C" means A alone, B alone, C alone, A combined with B, A combined with C, B combined with C, or A combined with B combined with C.

[0072] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure.

[0073] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. The term "and / or" includes any and all combinations of one or more of the associated listed items.

Claims

1. A module comprising: a die having a bottom die surface including a first pad, the first having a first area; a second solder bump disposed on the first pad; a layered structure including a first layer having a second pad, wherein the second pad has a second area greater than the first area and extends across a third lateral length overlapping the first pad, the first pad coupled to the second pad via a via provided by the first layer; the layered structure including: a bottom surface extending in a first lateral direction and a second lateral direction perpendicular to the first lateral direction; a side surface extending in a vertical direction perpendicular to the first lateral direction and the second lateral direction; a first solder bump disposed on the bottom surface, wherein the first solder bump has a first lateral length in the first lateral direction and is disposed on a third pad, wherein the third pad is coupled to the second pad, and the first lateral length is greater than a sum of lateral lengths of the first pad; and a second solder bump disposed on the bottom surface, wherein the second solder bump has a second lateral length in the first lateral direction, wherein the first lateral length is greater than the second lateral length, wherein the second solder bump is adjacent to the side surface, and wherein the third lateral length is greater than the first lateral length.

2. The module of claim 1, wherein the first solder bump is one or more of an oval shape, a rectangular shape, or an L-shape.

3. The module of claim 1, wherein the module includes a first edge, a second edge opposite the first edge, and a first distance from the first edge to the second edge, wherein the first solder bump is a second distance from the first edge, and wherein the second distance is less than 5% of the first distance.

4. The module of claim 1, further comprising a first component disposed on the bottom surface and a second component disposed on the bottom surface, wherein the first component and the second component are spaced apart from each other by a distance less than twice the second lateral length, wherein the first solder bump is disposed between the first component and the second component.

5. The module of claim 1, wherein the first solder bump has a first height in the vertical direction perpendicular to the first lateral direction and the second lateral direction, wherein the second solder bump has a second height in the vertical direction, wherein the first height is equal to the second height.

6. The module of claim 1, further comprising: a first via extending in the vertical direction to contact a first portion of the first solder bump; and a second via extending in the vertical direction to contact a second portion of the first solder bump, wherein the first via is separated from the second via by a distance in the first lateral direction, wherein the vertical direction is perpendicular to the first lateral direction and the second lateral direction.

7. The module of claim 1, further comprising: a first bottom pad disposed between the bottom surface and the first solder bump; and a second bottom pad disposed between the bottom surface and the second solder bump. a second underfill disposed between the bottom surface and the second solder bump.

8. The module of claim 7, wherein the first pad has a third length in the first lateral direction, the second pad has a fourth length in the first lateral direction, and the third length is greater than the second length.

9. The module of claim 1, further comprising a first component further disposed on the bottom surface; and a top surface opposite the bottom surface, wherein a silicon die is disposed on the top surface.

10. The module of claim 9, further comprising a first conductive structure electrically coupling the first solder bump to the silicon die; and a second conductive structure electrically coupling the second solder bump to the silicon die.

11. The module of claim 1, wherein the first lateral length is at least twice the second lateral length.

Images