PWELL isolated gate-controlled diode-triggered SCR device for ESD protection

Abstract

The present invention discloses a PWELL-isolated, gate-controlled diode-triggered SCR device for ESD protection. The device comprises a P+ injection region and a second N-well added to a conventional SCR, and utilizes a gate-controlled diode for auxiliary triggering, resulting in a technical solution with low voltage hysteresis and strong ESD robustness. On the one hand, the SCR device has an auxiliary trigger path of a gate-controlled diode, which can reduce the device's trigger voltage and increase its current discharge capability. On the other hand, as ESD stress increases, the SCR trigger path between the surface and the substrate of the device opens, which helps enhance the device's ESD current discharge capability and improves its ESD robustness. Furthermore, the longer base width increases the device's holding voltage, which helps alleviate the deep hysteresis problem that often occurs in ESD protection devices.

Description

Technical Field

[0001] The present invention belongs to the field of electrostatic discharge protection of integrated circuits, and in particular relates to a PWELL-isolated gate-controlled diode-triggered SCR device for ESD protection. Background Art

[0002] With the rapid development of the integrated circuit (IC) field, the integration density of integrated circuit (IC) chips is increasing, the process flow and related application materials of electronic products are diversifying, and the number of production links is gradually increasing. On the one hand, this has led to the shrinking feature size of IC manufacturing processes, increasing chip performance and power consumption. On the other hand, it has also brought challenges to the reliability of IC chips. On-chip IC electrostatic discharge (ESD) protection design faces increasingly severe challenges.

[0003] Different types of electrostatic discharge (ESD) models, ESD protection methods, ESD protection device designs, and related testing technologies for ICs are all developing rapidly. Generally speaking, ESD protection devices must meet three requirements: transparency, effectiveness, and robustness. Specifically, the protection device should be off during normal operation of the integrated circuit and quickly open to discharge the ESD current when an ESD pulse arrives. The protection device itself also needs to have a certain degree of resistance to ESD pulses. Electrically, this can be summarized as follows: the trigger voltage of the ESD protection device must be lower than the breakdown voltage of the protected device, and the maintenance voltage of the protection device must be higher than the normal operating voltage of the chip. For safety reasons, a safety margin of 10%-15% is usually required. Furthermore, the secondary failure current of the protection device must be sufficiently high.

[0004] Currently, the main ESD protection devices commonly used in on-chip ICs include diodes, MOS transistors, and silicon-controlled rectifiers (SCRs). Each of these ESD protection devices has its advantages and disadvantages, and their selection should be based on actual needs. Diodes have a simple structure and few parasitic effects, making them commonly used for ESD protection in low-voltage ICs. However, these devices suffer from high leakage currents. MOS transistors, with their excellent process compatibility, are widely used in on-chip IC ESD protection, particularly NMOS transistors. However, due to their relatively compromised overall ESD protection performance, they are primarily used for ESD protection of various I / O ports within ICs. The major drawback of MOS devices is their poor ESD robustness and large chip area occupation.

[0005] Compared to diodes and MOS devices, SCR devices offer enhanced ESD robustness while consuming the same chip area. However, due to the deep hysteresis (high trigger voltage and low hold voltage) of the SCR structure under ESD stress, latch-up can easily occur. Therefore, traditional SCR structures cannot generally be used directly for on-chip IC ESD protection. Typically, improvements and layout optimization based on the traditional SCR structure are required to meet the operational requirements of different circuits. Summary of the Invention

[0006] In order to solve the low holding voltage problem of traditional low-triggering voltage SCRs as ESD protection devices, an embodiment of the present invention provides a PWELL-isolated gate-controlled diode-triggered SCR device for ESD protection, which fully utilizes the strong ESD robustness of the SCR structure and increases the width of the transistor base region in the parasitic SCR by embedding a gate-controlled diode. When the device is subjected to an ESD pulse, a gate-controlled diode auxiliary trigger path and an SCR trigger path located on the surface and buried layer can be formed, thereby realizing an ESD protection design scheme with low triggering, high holding voltage and strong ESD robustness.

[0007] The PWELL-isolated gate-controlled diode-triggered SCR device for ESD protection provided in the embodiment includes a P substrate, characterized in that it also includes a first N-well, a P-well, and a second N-well provided on the surface of the P substrate, a first N+ injection region and a second P+ injection region embedded in the first N-well and the P-well, respectively, a first P+ injection region spanning the first N-well and the P-well and embedded, a third P+ injection region spanning the P-well and the second N-well and embedded, and a second N+ injection region, a fourth P+ injection region, and a third N+ injection region embedded in the second N-well at intervals;

[0008] A first thin gate oxide layer and a first polysilicon gate layer covering the first N-well surface and between the first N+ implantation region and the first P+ implantation region are provided; a second thin gate oxide layer and a second polysilicon gate covering the second N-well surface and between the third P+ implantation region and the second N+ implantation region are provided;

[0009] The gate-controlled diode D2 is formed by the first N+ implantation region, the first N well, the first thin gate oxide layer, the first polysilicon gate layer covering the first N+ implantation region, and the first P+ implantation region;

[0010] The gate-controlled diode D1 is formed by the third P+ implantation region, the second N well, the second thin gate oxide layer, the second polysilicon gate covering the third P+ implantation region, and the second N+ implantation region.

[0011] The second N-well and the third N+ injection region constitute a parasitic resistor Rn1, the fourth P+ injection region, the second N-well, the P-well and the P-substrate constitute a parasitic PNP transistor Q1, the fourth P+ injection region, the second N-well and the third P+ injection region constitute a parasitic PNP transistor Q2, the second P+ injection region, the P-well and the third P+ injection region constitute a parasitic resistor Rp1, the second N-well, the P-well and the first N-well constitute a parasitic NPN transistor Q3, the P-substrate 101 constitutes a parasitic resistor Rp2, and the first N+ injection region and the first N-well constitute a parasitic resistor Rn2.

[0012] In an embodiment, on the surface of the P substrate, the left edge of the P substrate is connected to the left edge of the first N well, the right side of the first N well is connected to the left side of the P well, the right side of the P well is connected to the left side of the second N well, and the right side of the second N well is connected to the right edge of the P substrate.

[0013] In an embodiment, on the surface of the first N-well, the left side of the first thin gate oxide layer and the first polysilicon gate layer covering it is connected to the right side of the first N+ injection region, and the right side of the first thin gate oxide layer and the first polysilicon gate layer covering it is connected to the left side of the first P+ injection region.

[0014] In an embodiment, on the surface of the second N-well, the left side of the second thin gate oxide layer and the second polysilicon gate covering it is connected to the right side of the third P+ injection region, and the right side of the second thin gate oxide layer and the second polysilicon gate covering it is connected to the left side of the second N+ injection region.

[0015] In an embodiment, when the SCR device is used for ESD protection, the circuit connection of the SCR device includes: the first N+ implant region is connected to the first metal, the first polysilicon gate is connected to the second metal, the first P+ implant region is connected to the third metal, the second P+ implant region is connected to the fourth metal, the third P+ implant region is connected to the fifth metal, the second polysilicon gate is connected to the sixth metal, the second metal, the third metal, the fifth metal, and the sixth metal are all connected to the tenth metal, the first metal and the fourth metal are both connected to the ninth metal, and a first electrode is drawn from the ninth metal to serve as the metal cathode of the device;

[0016] The fourth P+ injection region is connected to the seventh metal, the third N+ injection region is connected to the eighth metal, the seventh metal and the eighth metal are both connected to the eleventh metal, and a second electrode is drawn out from the eleventh metal to serve as a metal anode of the device.

[0017] In the embodiment, when forward ESD stress occurs at the metal anode 2 of the device, avalanche breakdown first occurs at the junction of the second N-well and the third P+ implantation region, and the reverse-gated diode D1 is immediately turned on; then, the ESD current reaches the metal cathode through the reverse-gated diode D1 and the forward-gated diode D2, and the ESD current in the second N-well is accumulated in the floating second N+ implantation region 109;

[0018] In addition, the electrostatic discharge current will apply a voltage to the gate of the gate-controlled diode through the third P+ injection region connected across it.

[0019] In an embodiment, when ESD occurs on the metal anode, the potential of the second N-well increases; at a certain moment, avalanche breakdown begins to occur at the junction of the second N-well and the third P+ injection region due to the high electric fields in the two regions, and electron-hole pairs are generated; then, the hole current flows into the P-well through the parasitic PNP transistor Q1 and the parasitic PNP transistor Q2, which increases the potential of the P-well; the emitter-base junction of the parasitic NPN transistor Q3 is forward biased by the potential of the P-well and turns on; the current of Q3 from the collector of Q1 to the cathode provides a forward bias for Q1; the voltage at the anode 213 no longer needs to provide a bias for Q1.

[0020] In an embodiment, the holding voltage can be tuned to meet different requirements by adjusting the length of the P well, the length of the first P+ injection region, the length of the third P+ injection region, and the distance between the second P+ injection region and the third P+ injection region.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] In the present invention, two gate-controlled diodes are formed by the first N+ implantation region, the first thin gate oxide layer and the first polysilicon gate layer covering it, the first P+ implantation region, the third P+ implantation region, the second polysilicon gate and the second thin gate oxide layer covering it, and the second N+ implantation region. Due to the high concentration of the third P+ implantation region, it has a low trigger voltage. The first N well and the first N+ implantation region form a parasitic resistor Rn2. The parasitic capacitor formed by the second thin gate oxide layer and the second polysilicon gate covering it and the second N well and the parasitic resistor Rn2 can form a resistor-capacitor coupling trigger network, thereby reducing the trigger voltage of the device and improving the turn-on speed of the device.

[0023] In the present invention, the P substrate, the first N-well, the P-well, the second N-well, the first N+ injection region, the second P+ injection region, the third P+ injection region, the fourth P+ injection region, and the third N+ injection region form an SCR path. The second N-well, the P-well, and the first N-well form a parasitic NPN transistor, and the second P+ injection region, the P-well, and the third P+ injection region form a parasitic resistor Rp1. The parasitic resistor Rn2, the parasitic resistor Rp1, and the P-well, which serves as the base region of the parasitic NPN transistor, increase the device's holding voltage. The SCR path can enhance the device's ESD robustness. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0025] Figure 1 1 is a schematic cross-sectional view of the structure of an SCR device provided by an embodiment of the present invention;

[0026] Figure 2 This is a circuit connection diagram of an SCR for ESD protection provided by an embodiment of the present invention;

[0027] Figure 3 is an equivalent circuit diagram of an auxiliary triggering path of an SCR under ESD stress provided by an embodiment of the present invention;

[0028] Figure 4 This is an equivalent circuit diagram of an SCR triggering path of an SCR device provided by an embodiment of the present invention under ESD stress.

[0029] Figure 5 This is a diagram comparing the SCR device provided by an embodiment of the present invention with a conventional low trigger voltage SCR structure;

[0030] Figure 6 1 is a comparison chart of the test results of the SCR device provided by the embodiment of the present invention during forward electrostatic protection. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and do not limit the scope of protection of the present invention.

[0032] To address the deep snapback problem of traditional SCR structures in ESD protection, a technical solution with reduced voltage snapback and strong ESD robustness was proposed by adding a P+ injection region and a second N-well to the conventional SCR and utilizing a gate-controlled diode for auxiliary triggering. On the one hand, the device's auxiliary trigger path, provided by the gate-controlled diode, reduces the device's trigger voltage and increases its current discharge capability. On the other hand, as ESD stress increases, the SCR trigger path between the device's surface and substrate opens, enhancing the device's ESD current discharge capability and improving its ESD robustness. Furthermore, by adjusting the width of the longer parasitic transistor base region, the device's holding voltage can be increased, which helps alleviate the deep snapback problem often associated with ESD protection devices.

[0033] like Figure 1 The internal structure cross-sectional view of the SCR device provided by the embodiment of the present invention is shown in FIG. Figure 1 As shown, the embodiment designs a PWELL-isolated gate-controlled diode-triggered SCR device for ESD protection, including an auxiliary trigger path of the gate-controlled diode and an SCR trigger path located on the surface and substrate with the parasitic transistor base region width adjusted, so as to reduce the trigger voltage of the ESD protection device, increase the holding voltage, reduce the voltage hysteresis amplitude after the ESD protection device is turned on, and enhance the ESD robustness of the device. Specifically, it includes: a P substrate (P-sub) 101, a first N well (Nwell) 102, a P well (Pwell) 103, a second N well (Nwell) 104, a first N+ injection region 105, a first P+ injection region 106, a second P+ injection region 107, a third P+ injection region 108, a second N+ injection region 109, a fourth P+ injection region 110, a third N+ injection region 111, a first thin gate oxide layer 112 and a first polysilicon gate layer 113 covering it, a second thin gate oxide layer 114 and a second polysilicon gate 115 covering it.

[0034] The first N-well 102, the P-well 103 and the second N-well 104 are sequentially provided on the surface area of the P-substrate 101 from left to right. The left edge of the P-substrate 101 is connected to the left edge of the first N-well 102, the right side of the first N-well 102 is connected to the left side of the P-well 103, the right side of the P-well 103 is connected to the left side of the second N-well 104, and the right side of the second N-well 104 is connected to the right edge of the P-substrate 101.

[0035] The first N+ implant region 105 and the second P+ implant region 107 are embedded from the surface of the first N-well 102 and the P-well 103, respectively. The second N+ implant region 109, the fourth P+ implant region 110, and the third N+ implant region 111 are embedded from the surface of the second N-well 104 in an alternating manner. The first P+ implant region 106 spans and is embedded in the first N-well 102 and the P-well 103. The third P+ implant region 108 spans and is embedded in the P-well 103 and the second N-well 104.

[0036] The first thin gate oxide layer 112 and the first polysilicon gate layer 113 covering it are arranged on the surface of the first N well 102 and between the first N+ injection region 105 and the first P+ injection region 106. Specifically, the left side of the first thin gate oxide layer 112 and the first polysilicon gate layer 113 covering it is connected to the right side of the first N+ injection region 105, and the right side of the first thin gate oxide layer 112 and the first polysilicon gate layer 113 covering it is connected to the left side of the first P+ injection region 106.

[0037] The second thin gate oxide layer 114 and the second polysilicon gate 115 covering it are arranged on the surface of the second N well 104 and between the third P+ injection region 108 and the second N+ injection region 109. Specifically, the left side of the second thin gate oxide layer 114 and the second polysilicon gate 115 covering it is connected to the right side of the third P+ injection region 108, and the right side of the second thin gate oxide layer 114 and the second polysilicon gate 115 covering it is connected to the left side of the second N+ injection region 109.

[0038] The lengths of the first thin gate oxide layer 112 and the first polysilicon gate layer 113 covering it and the second thin gate oxide layer 114 and the second polysilicon gate 115 covering it meet the minimum feature size of the manufacturing process. The length of the P well 103 is designed according to requirements, which can increase the base width of the parasitic NPN tube and improve the holding voltage of the device.

[0039] When the SCR device provided in the embodiment is used for ESD protection, Figure 2As shown, the circuit connection of the SCR device includes: the first N+ injection region 105 is connected to the first metal 201, the first polysilicon gate 113 is connected to the second metal 202, the first P+ injection region 106 is connected to the third metal 203, the second P+ injection region 107 is connected to the fourth metal 204, the third P+ injection region 108 is connected to the fifth metal 205, the second polysilicon gate 115 is connected to the sixth metal 206, the second metal 202, the third metal 203, the fifth metal 205 and the sixth metal 206 are all connected to the tenth metal 210, the first metal 201 and the fourth metal 204 are all connected to the ninth metal 209, and a first electrode 212 is drawn out from the ninth metal 209 to serve as the metal cathode of the device.

[0040] The fourth P+ implant region 110 is connected to the seventh metal 207, the third N+ implant region 111 is connected to the eighth metal 208, and both the seventh metal 207 and the eighth metal 208 are connected to the eleventh metal 211. A second electrode 213 is drawn from the eleventh metal 211 to serve as the metal anode of the device. It should be noted that all metals are made of the same material.

[0041] Figure 3 : is an equivalent circuit diagram of the auxiliary trigger path of the SCR device under ESD stress provided by the embodiment of the present invention. Figure 3 As shown, the first N+ implant region 105, the first N-well 102, the first thin gate oxide layer 112, the first polysilicon gate layer 113 covering it, and the first P+ implant region 106 form a gate-controlled diode D2. The third P+ implant region 108, the second N-well 104, the second thin gate oxide layer 114, the second polysilicon gate 115 covering it, and the second N+ implant region 109 form a gate-controlled diode D1. The second N-well 104 and the third N+ implant region 111 form a parasitic resistor Rn1. When forward ESD stress occurs at the metal anode 213 of the device, avalanche breakdown first occurs at the junction of the second N-well 104 and the third P+ implant region 108, and the reverse-gated diode D1 immediately turns on because the third P+ implant region 108 has a higher concentration and therefore a lower trigger voltage. Then, the ESD current reaches the metal cathode 212 of the device through the reverse gated diode D1 and the forward gated diode D2. The ESD current in the second N well 104 will be concentrated in the floating second N+ injection region 109 because the floating second N+ injection region 109 has a higher doping concentration.

[0042] In addition, the electrostatic discharge current will apply voltage to the gates of the gate-controlled diodes D1 and D2 through the bridged third P+ injection region 108. This will, on the one hand, improve the current discharge capability of the gate-controlled diode D1 and accelerate the conduction of the gate-controlled diode D2. On the other hand, for the gate-controlled diode D1, the parasitic resistance formed by the gate capacitance and the second N+ injection region 109 and the second N well 104 forms a resistor-capacitor coupling trigger network, which reduces the device trigger voltage and increases the device turn-on speed. The increased gate voltage further enhances the gate coupling effect, thereby improving the current discharge capability of the gate-controlled diode D1. For the gate-controlled diode D2, the first polysilicon layer 113 reduces the current path length of the gate-controlled diode D2, enabling triggering with a lower voltage and a faster response time under ESD stress. The gate voltage accelerates this process, and therefore, the gate voltage accelerates the conduction of the gate-controlled diode D2. Once the gate-controlled diode D2 is turned on, the auxiliary triggered diode path starts to discharge the ESD current. When the voltage drop generated by the current on the parasitic resistor Rn1 reaches 0.7V, the SCR path is triggered to discharge the main ESD current.

[0043] Figure 4 : is an equivalent circuit diagram of the SCR triggering path of the SCR device provided by the embodiment of the present invention under ESD stress. Figure 4 As shown, the second N-well 104 and the third N+ injection region 111 constitute a parasitic resistor Rn1, the fourth P+ injection region 110, the second N-well 104, the P-well 103 and the P-substrate 101 constitute a parasitic PNP transistor Q1, the fourth P+ injection region 110, the second N-well 104 and the third P+ injection region 108 constitute a parasitic PNP transistor Q2, the second P+ injection region 107, the P-well 103 and the third P+ injection region 108 constitute a parasitic resistor Rp1, the second N-well 104, the P-well 103 and the first N-well 102 constitute a parasitic NPN transistor Q3, the P-substrate 101 constitutes a parasitic resistor Rp2, and the first N+ injection region 105 and the first N-well 102 constitute a parasitic resistor Rn2.

[0044] When ESD occurs on the metal anode 213, the potential of the second N-well 104 increases. At a certain moment, avalanche breakdown begins to occur at the junction of the second N-well 104 and the third P+ injection region 108 due to the high electric fields in the two regions, and electron-hole pairs are generated. The hole current then flows into the P-well 103 through the parasitic PNP transistors Q1 and Q2, which increases the potential of the P-well 103. The emitter-base junction of the parasitic NPN transistor Q3 is forward biased by the potential of the P-well 103 and turns on. The current of Q3 from the collector of Q1 to the cathode provides a forward bias for Q1. The voltage at the anode 213 no longer needs to provide a bias for Q1. Therefore, whether the ESD current discharged by the auxiliary triggered diode path generates a 0.7V voltage drop on the parasitic resistor Rn1, or the emitter-base junction of the parasitic NPN transistor Q3 is forward biased through the potential of the P well 103, the SCR path will be triggered to discharge the main ESD current, thereby achieving a lower trigger voltage and higher robustness.

[0045] Furthermore, because free carriers are injected from the emitter regions of the two PNP transistors Q1 and Q2, the holding voltage depends on the degree of space charge neutralization in the base regions of the NPN transistor Q3 and the PNP transistors Q1 and Q2. Therefore, the lateral dimensions associated with the transistor base widths and Rn2 and Rp1 are crucial. The holding voltage can be tuned to meet different requirements by adjusting the length of the P-well 103, the lengths of the first and third P+ injection regions 106 and 108, and the distance between the second and third P+ injection regions 107 and 108.

[0046] Figure 5 This is a comparison diagram of the SCR device provided by an embodiment of the present invention and the traditional low trigger voltage SCR structure. Figure 6 This is a comparison chart of the test results of the SCR device provided by the embodiment of the present invention during forward electrostatic protection. Figure 6 It can be seen that when used for forward electrostatic pulse protection, the maintenance voltage (Voltage) of the traditional low trigger voltage SCR structure is about 3V, and the maintenance voltage of the SCR device provided in this embodiment is about 6V. Compared with the traditional SCR structure, the maintenance voltage of the SCR device provided in this embodiment is significantly improved; the triggering voltage of the traditional low trigger voltage SCR is about 10V, and the triggering voltage of the SCR device provided in this embodiment is about 10V. Compared with the traditional SCR structure, the triggering voltage of the SCR device provided in this embodiment is basically the same; at the same time, according to Figure 6It can be seen that the failure current of the traditional low trigger voltage SCR device is about 2.6A, while the failure current of the SCR device provided in this embodiment is about 2.6A. Compared with the traditional low trigger voltage SCR structure, the failure current of the SCR device provided in this embodiment is basically the same; that is, when the trigger voltage and failure current are basically unchanged, the maintenance voltage of the SCR device provided in this embodiment is significantly improved compared with the traditional low trigger voltage SCR structure.

[0047] In summary, the SCR device provided in the above embodiment utilizes a gate-controlled diode to reduce the trigger voltage of the device and increase the turn-on speed of the device. In addition, the SCR structure has the advantage of strong ESD robustness, and the SCR holding voltage is increased through structural design. When subjected to ESD stress, the SCR device provided in the embodiment can not only form an auxiliary trigger path composed of a gate-controlled diode to reduce the voltage hysteresis amplitude after the ESD protection device is turned on, but also form an SCR trigger path with a high holding voltage, thereby enhancing the ESD robustness of the device.

[0048] The specific implementation methods described above provide a detailed description of the technical solutions and beneficial effects of the present invention. It should be understood that the above is only the most preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, supplements and equivalent substitutions made within the scope of the principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A PWELL isolated gate-controlled diode triggered SCR device for ESD protection, comprising a P substrate, characterized in that: The system further comprises a first N-well, a P-well, and a second N-well disposed on the surface of the P-substrate, a first N+ injection region and a second P+ injection region embedded in the first N-well and the P-well, respectively, a first P+ injection region spanning the first N-well and the P-well and embedded therein, a third P+ injection region spanning the P-well and the second N-well and embedded therein, and a second N+ injection region, a fourth P+ injection region, and a third N+ injection region embedded therein at intervals. A first thin gate oxide layer and a first polysilicon gate layer covering the first N-well surface and between the first N+ implantation region and the first P+ implantation region are provided; a second thin gate oxide layer and a second polysilicon gate covering the second N-well surface and between the third P+ implantation region and the second N+ implantation region are provided; The first N+ implantation region, the first N well, the first thin gate oxide layer, the first polysilicon gate layer covering the first N+ implantation region, and the first P+ implantation region constitute a forward gate-controlled diode D2; The third P+ implantation region, the second N well, the second thin gate oxide layer, the second polysilicon gate covering the third P+ implantation region, and the second N+ implantation region constitute a reverse gated diode D1; The second N-well and the third N+ injection region constitute a parasitic resistor Rn1, the fourth P+ injection region, the second N-well, the P-well, and the P-substrate constitute a parasitic PNP transistor Q1, the fourth P+ injection region, the second N-well, and the third P+ injection region constitute a parasitic PNP transistor Q2, the second P+ injection region, the P-well, and the third P+ injection region constitute a parasitic resistor Rp1, the second N-well, the P-well, and the first N-well constitute a parasitic NPN transistor Q3, the P-substrate constitutes a parasitic resistor Rp2, and the first N+ injection region and the first N-well constitute a parasitic resistor Rn2; When the SCR device is used for ESD protection, the circuit connection of the SCR device includes: the first N+ implant region is connected to the first metal, the first polysilicon gate is connected to the second metal, the first P+ implant region is connected to the third metal, the second P+ implant region is connected to the fourth metal, the third P+ implant region is connected to the fifth metal, the second polysilicon gate is connected to the sixth metal, the second metal, the third metal, the fifth metal and the sixth metal are all connected to the tenth metal, the first metal and the fourth metal are both connected to the ninth metal, and a first electrode is drawn from the ninth metal to serve as a metal cathode of the device; The fourth P+ injection region is connected to the seventh metal, the third N+ injection region is connected to the eighth metal, the seventh metal and the eighth metal are both connected to the eleventh metal, and a second electrode is drawn out from the eleventh metal to serve as a metal anode of the device.

2. The PWELL isolated gate-controlled diode triggered SCR device for ESD protection according to claim 1, characterized in that: On the surface of the P substrate, the left edge of the P substrate is connected to the left edge of the first N well, the right side of the first N well is connected to the left side of the P well, the right side of the P well is connected to the left side of the second N well, and the right side of the second N well is connected to the right edge of the P substrate.

3. The PWELL isolated gate-controlled diode triggered SCR device for ESD protection according to claim 1, characterized in that: On the surface of the first N well, the left side of the first thin gate oxide layer and the first polysilicon gate layer covering it is connected to the right side of the first N+ injection region, and the right side of the first thin gate oxide layer and the first polysilicon gate layer covering it is connected to the left side of the first P+ injection region.

4. The PWELL isolated gate-controlled diode triggered SCR device for ESD protection according to claim 1, characterized in that: On the surface of the second N well, the left side of the second thin gate oxide layer and the second polysilicon gate covering it is connected to the right side of the third P+ injection region, and the right side of the second thin gate oxide layer and the second polysilicon gate covering it is connected to the left side of the second N+ injection region.

5. The PWELL isolated gate-controlled diode triggered SCR device for ESD protection according to claim 1, characterized in that: When forward ESD stress occurs at the metal anode of the device, avalanche breakdown first occurs at the junction of the second N-well and the third P+ implant region, and the reverse-gated diode D1 is immediately turned on. Then, the ESD current reaches the metal cathode through the reverse-gated diode D1 and the forward-gated diode D2, and the ESD current in the second N-well is concentrated in the floating second N+ implant region. In addition, the electrostatic discharge current will apply a voltage to the gate of the gate-controlled diode through the third P+ injection region connected across it.

6. The PWELL isolated gate-controlled diode triggered SCR device for ESD protection according to claim 1, characterized in that: When ESD occurs on the metal anode, the potential of the second N-well increases; at a certain moment, avalanche breakdown begins to occur at the junction of the second N-well and the third P+ injection region due to the high electric fields in the two regions, and electron-hole pairs are generated; then, the hole current flows into the P-well through the parasitic PNP transistor Q1 and the parasitic PNP transistor Q2, which increases the potential of the P-well; the emitter-base junction of the parasitic NPN transistor Q3 is forward biased by the potential of the P-well and turns on; the current of the parasitic NPN transistor Q3 from the collector of the parasitic PNP transistor Q1 to the cathode provides a forward bias for the parasitic PNP transistor Q1; the voltage at the metal anode no longer needs to provide a bias for the parasitic PNP transistor Q1.

7. The PWELL isolated gate-controlled diode triggered SCR device for ESD protection according to claim 1, characterized in that: The holding voltage is tuned to meet different requirements by adjusting the length of the P well, the length of the first P+ injection region, the length of the third P+ injection region, and the distance between the second P+ injection region and the third P+ injection region.

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