A radio frequency power detector chip layout structure and a radio frequency power detector chip

Abstract

The application relates to the technical field of integrated circuit design, and provides a radio frequency power detector chip layout structure and a radio frequency power detector chip, the layout structure comprises a first layout area, a second layout area and a third layout area; the first layout area is in an L shape and is formed with a first embedded groove; the third layout area is in a concave shape and is formed with a second embedded groove; the left and right sides of the second layout area are respectively embedded into the first embedded groove and the second embedded groove. According to the application, the layout structure of the radio frequency power detector chip is divided into three different layout areas, the pads needing electrostatic protection are uniformly arranged in the first layout area, the pads not needing electrostatic protection are uniformly arranged in the third layout area, and the main components of the radio frequency power detector chip are uniformly arranged in the second layout area, so that the layout structure is more compact between different layout areas, and the rationality and compactness during layout of multiple layout areas are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit design, in particular to a radio frequency power detector chip layout structure and a radio frequency power detector chip. BACKGROUND

[0002] With the continuous development of communication technology, the power control module is becoming an indispensable part of the communication system. As the core part of the power control module, the radio frequency power detector has been pursuing the goal of more superior performance, smaller device area and lower cost with the development of integrated circuit technology.

[0003] The existing radio frequency power detector chip has a large number of modules on the chip and the shapes of the modules are irregular. When the overall layout is performed, the layout rationality and compactness between the modules are poor, which results in low area utilization of the chip and increases the manufacturing cost of the chip. SUMMARY

[0004] The present application relates to the technical field of integrated circuit design, in particular to a radio frequency power detector chip layout structure and a radio frequency power detector chip.

[0005] The technical problems to be solved by the present application are as follows:

[0006] In one aspect, the present application provides a radio frequency power detector chip layout structure, comprising a first layout area, a second layout area and a third layout area arranged in sequence from left to right.

[0007] The first layout area is L-shaped and formed with a first embedded slot, the third layout area is concave-shaped and formed with a second embedded slot, and the left and right sides of the second layout area are embedded in the first and second embedded slots, respectively.

[0008] In some possible embodiments, the layout structure composed of the first, second and third layout areas is rectangular, and the layout structure is provided with a polycrystalline layer and a plurality of metal layers.

[0009] The first and second layout areas and the second and third layout areas are connected by metal layers.

[0010] In some possible embodiments, the first layout area includes an input and output module composed of a polycrystalline layer and a plurality of metal layers, and a plurality of anti-static modules, the input and output module is arranged away from the second layout area, and the plurality of anti-static modules are arranged close to the second layout area.

[0011] The second layout area includes a radio frequency power detector module composed of a polycrystal layer and a multi-layer metal layer, and the third layout area includes a signal input module composed of a multi-layer metal layer.

[0012] In some possible embodiments, the input and output module includes a plurality of first pads, the plurality of first pads are sequentially arranged on a side away from the second layout area, and the metal layer constituting the first pad is greater than two layers.

[0013] In some possible embodiments, the signal input module includes a radio frequency signal input module, the radio frequency signal input module includes a second pad and an input series capacitor, and the second pad and the input series capacitor are sequentially arranged above the third layout area.

[0014] The metal layer constituting the second pad is less than or equal to two layers, and the area of the second pad is less than or equal to 80% of the area of the first pad.

[0015] In some possible embodiments, the signal input module further includes a bias voltage input module, the bias voltage input module includes an input series resistor and a third pad, the input series resistor and the third pad are sequentially arranged below the third layout area, and the third pad has the same structure as the first pad.

[0016] In some possible embodiments, the radio frequency power detector module includes a current superposition module, a voltage division module, a filter module, and a plurality of power-to-current conversion modules, the voltage division module and the filter module are located at the upper left corner of the lower left area of the second layout area, the current superposition module is arranged adjacent to the voltage division module and close to the third layout area.

[0017] In some possible embodiments, the power-to-current conversion module is composed of a plurality of power-to-current conversion sub-modules, the power-to-current conversion sub-module is composed of a MOS tube and an RC filter.

[0018] In some possible embodiments, the current superposition module is composed of a plurality of MOS tubes connected in parallel and connected in series with a resistor, the filter module is composed of a flat plate capacitor, and the voltage division module includes a plurality of resistors.

[0019] In another aspect, the present application provides a radio frequency power detector chip made of the radio frequency power detector chip layout structure as described above.

[0020] The technical scheme of the embodiment of the present application has at least the following advantages and beneficial effects:

[0021] The present application divides the layout structure of the radio frequency power detector chip into three different layout areas, places the pads needing electrostatic protection in the first layout area, places the pads not needing electrostatic protection in the third layout area, places the main components of the radio frequency power detector chip in the second layout area, and embeds the second layout area between the first layout area and the third layout area, so that the layout structure is more compact between different layout areas, improves the rationality and compactness of the layout of multiple layout areas, helps to improve the area utilization rate of the chip and reduce the manufacturing cost of the chip.

[0022] In addition, the present application improves the first pad to obtain the second pad, which can effectively reduce the attenuation of the radio frequency signal on the basis of reducing the area occupied by the second pad. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 The structural block diagram of the radio frequency power detector chip layout structure provided by the embodiment of the present application is provided;

[0024] Figure 2 The structural block diagram of the first layout area provided by the embodiment of the present application is provided;

[0025] Figure 3 The structural block diagram of the second layout area provided by the embodiment of the present application is provided;

[0026] Figure 4 The structural block diagram of the third layout area provided by the embodiment of the present application is provided;

[0027] Figure 5 The structural schematic diagram of the first pad provided by the embodiment of the present application is provided;

[0028] Figure 6 The structural schematic diagram of the second pad provided by the embodiment of the present application is provided;

[0029] Figure 7 The layout schematic diagram of the radio frequency power detector chip provided by the embodiment of the present application is provided.

[0030] Icon: 10-first layout area, 10a-first embedding slot, 11-anti-static module, 12-first pad, 20-second layout area, 21-current superposition module, 22-voltage division module, 23-filtering module, 24-power-to-current module, 30-third layout area, 30a-second embedding slot, 31-second pad, 32-input series capacitor, 33-input series resistor, 34-third pad. DETAILED DESCRIPTION

[0031] EMBODIMENT

[0032] Please refer to Figures 1 to 7This embodiment provides a layout structure for a radio frequency power detector chip to at least overcome the technical problem of poor rationality and compactness of the layout of modules on existing radio frequency power detector chips, resulting in low chip area utilization. Specifically, the layout structure of the radio frequency power detector chip includes a first layout region 10, a second layout region 20, and a third layout region 30.

[0033] In this embodiment, please refer to Figure 1 The first map region 10, the second map region 20, and the third map region 30, which constitute the map structure, are arranged sequentially from left to right. Among them, combined with... Figure 2 The content shown indicates that the first layout area 10 is L-shaped, and a first embedding groove 10a is formed on the side of the first layout area 10 closest to the second layout area 20. For example, the first embedding groove 10a is formed on the lower right side of the first layout area 10; simultaneously, combined with Figure 4 As shown, the third pattern area 30 is U-shaped, and a second embedding groove 30a is formed on the side of the third pattern area 30 closest to the second pattern area 20. That is, the U-shaped groove of the third pattern area 30 serves as the second embedding groove 30a and faces the second pattern area 20. At this time, combined with... Figure 2 As shown, the second layout area 20 has an irregular shape, so that the left and right sides of the second layout area 20 can be embedded in the first embedding groove 10a and the second embedding groove 30a respectively, thereby achieving the tight enclosure of the second layout area 20 by the first layout area 10 and the third layout area 30.

[0034] Understandably, in actual implementation, it is necessary to combine Figure 1 The layout structure shown, consisting of the first layout area 10, the second layout area 20, and the third layout area 30, is rectangular. This design enhances the aesthetics of the layout and facilitates the placement of corresponding modules. Furthermore, the layout structure incorporates polycrystalline layers and multiple metal layers. The first layout area 10 and the second layout area 20, as well as the second layout area 20 and the third layout area 30, are connected via these metal layers.

[0035] In order to make the layout of each module in the layout structure more reasonable and compact, so as to improve the chip area utilization, this embodiment further defines the modules set on the first layout area 10, the second layout area 20 and the third layout area 30.

[0036] Specifically, please refer to Figure 2The first layout area 10 includes an input / output module composed of a polycrystalline layer and multiple metal layers, as well as multiple anti-static modules 11, wherein the multiple anti-static modules 11 are disposed on one side close to the second layout area 20. For example, in this embodiment, a total of four anti-static modules 11 are provided, one of which is disposed in the area of ​​the first layout area 10 extending toward the second layout area 20, and the other three anti-static modules 11 are disposed sequentially from top to bottom on the first layout area 10.

[0037] Continue to refer to Figure 2 The input / output module is located on the side away from the second layout area 20. The input / output module includes multiple first pads 12, which are sequentially arranged on the side away from the second layout area 20. For example, in this embodiment, three first pads 12 are provided, and the three first pads 12 are sequentially arranged from top to bottom on the side of the first layout area 10 away from the second layout area 20.

[0038] It should be noted that, in combination Figure 5 As shown, the metal layers constituting the first pad 12 are more than two; for example, the metal layers constituting the first pad 12 can be nine. Furthermore, the first pads 12 located on the first layout area 10 are all pads requiring electrostatic discharge (ESD) protection, including but not limited to power pads, ground pads, and output pads.

[0039] Please refer to Figure 3 The second layout area 20 includes an RF power detector module composed of polycrystalline layers and multiple metal layers, serving as the main body of the RF power detector chip. Specifically, the RF power detector module includes a current superposition module 21, a voltage divider module 22, a filter module 23, and multiple power-to-current conversion modules 24.

[0040] In this circuit, the voltage divider module 22 receives a voltage source as input, while the filter module 23 filters out high-frequency signals from the output signal. At this point, combined with... Figure 3 As shown, the voltage divider module 22 and the filter module 23 are located in the upper left corner of the lower left area of ​​the second layout area 20 and close to the first layout area 10. The voltage divider module 22 and the filter module 23 are arranged horizontally side by side. The placement of multiple power-to-current modules 24 is not specifically limited. The placement of the power-to-current modules 24 can be reasonably determined according to the size of the second layout area 20. However, it should be ensured that the current superposition module 21 is placed close to the voltage divider module 22 and near the third layout area 30, so that at least one current superposition module 21 is located near the filter module 23.

[0041] It is understood that the power-to-current module 24 in this embodiment is composed of multiple power-to-current sub-modules, and each power-to-current sub-module is composed of a MOSFET and an RC filter. The current superposition module 21 is composed of multiple MOSFETs connected in parallel and then connected in series with a resistor, the filter module 23 is composed of a parallel plate capacitor, and the voltage divider module 22 includes multiple resistors.

[0042] Please refer to Figure 4 The third section, area 30, includes a signal input module composed of multiple metal layers. Specifically, the signal input module includes an RF signal input module and a bias voltage input module.

[0043] The radio frequency signal input module includes a second pad 31 and an input series capacitor 32. The second pad 31 and the input series capacitor 32 are sequentially disposed above the third layout area 30. For example, the second pad 31 is located at the top of the third layout area 30, and the input series capacitor 32 is disposed adjacent to the second pad 31 to isolate the DC component of the input signal through the input series capacitor 32.

[0044] It should be noted that, in order to reduce the occupied area of ​​the second pad 31 and reduce RF signal attenuation, while retaining the wire bonding function of the second pad 31, the number of metal layers constituting the second pad 31 is limited in this embodiment. Specifically, in conjunction with Figure 6 As shown, the metal layers constituting the second pad 31 are less than or equal to two layers, preferably, the metal layers constituting the second pad 31 are two layers; at the same time, the area of ​​the second pad 31 is less than the area of ​​the first pad 12, preferably, the area of ​​the second pad 31 is less than 80% of the area of ​​the first pad 12.

[0045] Continue to refer to Figure 4 The bias voltage input module includes an input series resistor 33 and a third pad 34. The input series resistor 33 and the third pad 34 are sequentially arranged below the third layout area 30, that is, the input series resistor 33 is arranged adjacent to the input series capacitor 32, and the third pad 34 is arranged adjacent to the input series resistor 33. The structure of the third pad 34 is the same as that of the first pad 12.

[0046] It should be noted that the bias voltage input module is not necessarily required in actual implementation. Therefore, when the third layout area 30 is not equipped with a bias voltage input module, the second embedded slot 30a of the third layout area 30 may expand to the area where the input series resistor 33 or the third pad 34 is located.

[0047] On the other hand, this embodiment provides a radio frequency power detector chip, which is fabricated using the radio frequency power detector chip layout structure described above.

[0048] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A layout structure for a radio frequency power detector chip, characterized in that, This includes the first map area, the second map area, and the third map area, arranged from left to right. The first layout area is L-shaped and has a first embedding groove, and the third layout area is U-shaped and has a second embedding groove. The first embedding groove and the second embedding groove are respectively embedded on the left and right sides of the second layout area. The first layout area includes an input / output module composed of a polycrystalline layer and multiple metal layers, as well as multiple anti-static modules; The input / output module includes multiple first pads, which are sequentially arranged on the side away from the second layout area; the multiple anti-static modules are arranged on the side close to the second layout area. The second layout area includes a radio frequency power detector module composed of polycrystalline layers and multiple metal layers; The third layout area includes a signal input module composed of multiple metal layers; the signal input module includes a radio frequency signal input module and a bias voltage input module. The radio frequency signal input module includes a second pad and an input series capacitor, which are sequentially disposed above the third layout area. The bias voltage input module includes an input series resistor and a third pad, which are sequentially arranged below the third layout area.

2. The radio frequency power detector chip layout structure according to claim 1, characterized in that, The layout structure formed by the first layout area, the second layout area and the third layout area is a rectangular structure, and the layout structure is provided with a polycrystalline layer and multiple metal layers. The first and second map regions, as well as the second and third map regions, are connected by a metal layer.

3. The radio frequency power detector chip layout structure according to claim 1, characterized in that, The metal layers constituting the first pad are more than two.

4. The radio frequency power detector chip layout structure according to claim 1, characterized in that, The metal layers constituting the second pad are less than or equal to two layers, and the area of ​​the second pad is less than 80% of the area of ​​the first pad.

5. The radio frequency power detector chip layout structure according to claim 1, characterized in that, The structure of the third pad is the same as that of the first pad.

6. The radio frequency power detector chip layout structure according to claim 1, characterized in that, The radio frequency power detector module includes a current superposition module, a voltage divider module, a filter module, and multiple power-to-current modules. The voltage divider module and the filter module are located in the upper left corner of the lower left area of ​​the second layout region, and the current superposition module is located adjacent to the voltage divider module and close to the third layout region.

7. The radio frequency power detector chip layout structure according to claim 6, characterized in that, The power-to-current module consists of multiple power-to-current sub-modules, each of which is composed of a MOSFET and an RC filter.

8. The radio frequency power detector chip layout structure according to claim 6, characterized in that, The current superposition module is composed of multiple MOSFETs connected in parallel and then in series with a resistor; the filter module is composed of a parallel plate capacitor; and the voltage divider module includes multiple resistors.

9. A radio frequency power detector chip, characterized in that, It is fabricated using the radio frequency power detector chip layout structure as described in any one of claims 1-8.

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