A semiconductor laser and its fabrication method

Abstract

This invention relates to a semiconductor laser and its fabrication method, comprising a substrate, an active region and an anti-reflection window region disposed on the substrate, the active region including an active layer and a grating layer, the anti-reflection window region being located at the light-emitting end face, the active region and the anti-reflection window region being adjacent to each other, the anti-reflection window region including a bottom contour, a side contour and a top contour, an anti-reflection structure disposed within the anti-reflection window region, the anti-reflection structure including a waveguide layer, one end of the waveguide layer extending to the light-emitting end face, corresponding to the active layer, and the thickness of the waveguide layer being greater than or equal to the thickness of the active layer, the other end extending to the top contour, and an isolation layer disposed along the contour of the anti-reflection window region, and at least located between the side contour and the waveguide layer, for separating the active region and the waveguide layer; this semiconductor laser can not only achieve better anti-reflection light effect and significantly improve the anti-reflection capability of the chip itself, but also ensure that the efficiency of forward light coupling from the active region into the waveguide is not affected.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor lasers, in particular to a semiconductor laser with an anti-reflection structure and a preparation method thereof. BACKGROUND

[0002] With the comprehensive popularization of optical fiber communication system engineering, the core optical module presents the trend of miniaturization, integration and low cost, and every optical module manufacturer is actually facing the pressure of pursuing high performance and low cost, and this pressure is continuously transmitted to the upstream optical chip manufacturers. In the backbone network, metropolitan area network, local area network and fiber to the home network, >10Km transmission distance uses DFB laser in large quantities, and this type of semiconductor laser (or semiconductor laser chip) will be affected by the resonant disturbance of the reflected light in the system link, resulting in the deterioration of the system receiving sensitivity. An optical isolator must be added in the optical device to block the reflected light, however, the optical isolator mainly depends on import, and the price is expensive, which will greatly increase the cost of the optical module and reduce the competitiveness of the optical chip.

[0003] Therefore, improving the anti-reflection capability of the optical chip itself is a main technical approach to realize high performance and low cost of the optical chip and the optical module. The anti-reflection capability of the chip end is usually related to the waveguide design of the light-emitting end. Domestic mainstream optical chip manufacturers have some patent layouts in this regard. For example, Chinese patent CN 209993866 U discloses a 10G anti-reflection distributed feedback laser technology, which is designed to have a light waveguide layer at the light-emitting end face, and the thickness of the light waveguide layer in the horizontal direction is gradually changed to realize the loss of reflected light in the end face waveguide layer. For another example, Chinese patent CN 111541149 A discloses another 10G anti-reflection laser and its preparation process, which is designed to have a more complex light waveguide layer at the light-emitting end face, and the thickness of the light waveguide layer is gradually changed, and the basic principle is similar to that of patent CN 209993866 U. For another example, Chinese patent CN 209993868 U discloses a 25G anti-reflection distributed feedback laser, which is designed to have a light waveguide layer with a constant thickness at the light-emitting end face, and the loss of external reflected light is realized by misalignment with the active layer. For another example, Chinese patent CN 112290382 A discloses a semiconductor laser and its manufacturing method, and provides another anti-reflection structure, which is designed to have a double-layer waveguide layer with a constant thickness at the light-emitting end face, and the optimization of the divergence angle and the anti-reflection capability of the chip is realized by changing the light field distribution of the window area. The above-mentioned different optical chip anti-reflection design schemes have their own advantages, but also have some common shortcomings, for example, one end of each light waveguide layer is directly connected with the active area, so that when the external back-reflected light enters the light waveguide layer from the light-emitting end face and propagates along the light waveguide layer, the loss of the reflected light is small, and the reflected light is very easy to enter the active area through the interface between the light waveguide layer and the active area, resulting in poor anti-reflection performance of the semiconductor laser. Therefore, it is necessary to design a semiconductor laser with better anti-reflection performance, and a simpler structure and easier preparation. SUMMARY

[0004] The first aspect of the present application aims to solve the above technical problems and provides a semiconductor laser with a simpler structure, easier growth and preparation, and more excellent anti-reflection performance. The main idea is as follows:

[0005] A semiconductor laser includes a substrate, an active region and an anti-reflection window area arranged above the substrate, the active region includes an active layer and a grating layer, the anti-reflection window area is located at a light-emitting end face, and the active region is connected with the anti-reflection window area,

[0006] The anti-reflection window area includes a bottom profile, a side profile facing away from the light-emitting end face, and a top profile, the side profile is connected with the bottom profile and the top profile respectively, the bottom profile is flush with or lower than the lower edge of the active layer, and the top profile is flush with or higher than the upper edge of the grating layer,

[0007] The anti-reflection structure is arranged in the anti-reflection window region, and the waveguide layer extends to the light-out end face at one end, the end corresponds to the active layer, and the thickness of the waveguide layer is greater than or equal to the thickness of the active layer, and extends to the top profile at the other end, and

[0008] The isolation layer is arranged along the profile of the anti-reflection window region and is located at least between the side profile and the waveguide layer, and is used to separate the active region and the waveguide layer. In this scheme, on the one hand, by arranging the waveguide layer in the anti-reflection window region, and making one end of the waveguide layer located at the light-out end face and the other end located at the top profile, since the light-out end face and the top profile are in different directions, the waveguide layer is curved. The reflected light from the light-out end face into the waveguide layer can be emitted from the other end of the waveguide layer under the guidance of the waveguide layer, effectively preventing the reflected light from entering the active region. On the other hand, by arranging the isolation layer between the side profile and the waveguide layer, not only the distance between the active region and the waveguide layer can be increased, but also the isolation effect between the active region and the waveguide layer can be achieved, so that the active region and the waveguide layer do not contact each other, thereby greatly increasing the loss of the external backward reflected light coupled into the active region. The combination of the two aspects not only can achieve better anti-reflection effect and significantly improve the anti-reflection ability of the chip itself, but also can ensure that the efficiency of the active region forward light coupling into the waveguide is not affected.

[0009] In some embodiments, the material of the waveguide layer adopts InGaAsP quaternary compound. Compared with the Al-containing material of the active region, the oxidation defect is not easy to be introduced, and the refractive index of the waveguide layer is higher than that of the InP cladding layer one and the InP cladding layer two. The waveguide layer adopting this material can effectively confine the light in the optical waveguide and effectively improve the anti-reflection effect.

[0010] In some embodiments, the isolation layer at least includes an InP cladding layer one made of InP material.

[0011] In some embodiments, the anti-reflection structure further includes an InP cladding layer two arranged between the waveguide layer and the top profile.

[0012] In order to further improve the anti-reflection performance, in some embodiments, isolation layers are arranged between the side profile and the waveguide layer and between the bottom profile and the waveguide layer. So as to strictly separate the waveguide layer and the active region, thereby facilitating further improvement of the anti-reflection performance.

[0013] Preferably, the shape of the waveguide layer is adapted to the shape composed of the bottom profile and the side profile of the anti-reflection window region. This facilitates the molding of the waveguide layer, and the growth preparation is simple and has good repeatability.

[0014] To solve the problem of easy molding, in some embodiments, the bottom profile is a horizontally arranged planar structure, and the side profile is an arc-shaped structure,

[0015] The waveguide layer comprises a first part and a second part connected with the first part, one end of the first part extends to the light-out end face, and one end of the second part extends to the top profile, the first part and the second part correspond to the bottom profile and the side profile respectively, wherein the first part is horizontally arranged and corresponds to the active layer, the lower edge of the first part is lower than or flush with the lower edge of the active layer, and the upper edge of the first part should be higher than or flush with the upper edge of the active layer, and the second part is an arc-shaped structure. In this scheme, by configuring the side profile as an arc-shaped structure and configuring the second part as an arc-shaped structure, not only is the etching and molding of the anti-reflection window area facilitated, but also the growth of the anti-reflection structure in the anti-reflection window area is facilitated, thereby solving the problem of improving the anti-reflection performance and facilitating the preparation.

[0016] Preferably, the sum of the horizontal length L1 of the bottom profile and the horizontal length L2 of the side profile is 10-50 μm. Not only can the light-out power of the laser chip be ensured, but also better anti-reflection effect can be achieved.

[0017] Preferably, the n-type cladding layer is arranged below the active layer, and the depth H1 of the bottom profile below the lower edge of the n-type cladding layer is 0 nm-1 μm.

[0018] Preferably, the height H2 of the top profile above the upper edge of the grating layer is in the range of 0 nm-1 μm.

[0019] Preferably, the thickness H3 of the isolation layer between the bottom profile and the waveguide layer is 0 nm-1 μm.

[0020] Preferably, the thickness H4 of the first part is 0 nm-1 μm.

[0021] The second aspect of the present application is to solve the problem of preparing the above-mentioned semiconductor laser, and provides a preparation method of the semiconductor laser, comprising,

[0022] Step S1: forming a primary epitaxial structure on a substrate;

[0023] Step S2: forming a mask pattern of an anti-reflection window area on the basis of the primary epitaxial structure;

[0024] Step S3: performing isotropic etching on the end face window area to form an anti-reflection window area, and the end face etching area of the anti-reflection window area comprises an arc-shaped structure;

[0025] Step S4: performing protection treatment on the end face etching area of the anti-reflection window area;

[0026] Step S5, sequentially growing an isolation layer, a waveguide layer and an InP cladding layer in the end surface etching area of the anti-reflection window area to form an anti-reflection structure.

[0027] Step S6, performing secondary epitaxial growth.

[0028] The third aspect of the present application aims to further improve the anti-reflection capability of the chip itself. In some embodiments, a second anti-reflection area is further arranged above the substrate, the second anti-reflection area is arranged in the side profile of the anti-reflection window area and is in communication with the anti-reflection window area, the second anti-reflection area corresponds to at least the active layer, and the second anti-reflection area is filled with an isolation layer. By arranging the second anti-reflection area and filling the isolation layer, the spacing between the active layer and the waveguide layer can be further increased, the loss of external back-reflected light coupled into the active area along the waveguide layer is further increased, and the anti-reflection capability of the chip itself can be further improved.

[0029] To facilitate the preparation of the shape, the second anti-reflection area includes a bottom edge and a side edge away from the light emitting end surface and connected to the active area, the side edge is connected to the bottom edge, the upper end of the side edge is higher than the active layer, and the lower end of the bottom edge is lower than the active layer.

[0030] In some embodiments, the active area further includes an n-type cladding layer arranged below the active layer and a p-type cladding layer arranged above the active layer, the upper end of the side edge is higher than or flush with the upper edge of the p-type cladding layer, and the lower end of the bottom edge is lower than or flush with the lower edge of the n-type cladding layer. This is conducive to achieving better anti-reflection effect.

[0031] To solve the problem of facilitating the preparation of the shape, in some embodiments, the bottom edge is a horizontally arranged planar structure, and the side edge is an arc-shaped structure. This profile shape is more convenient for etching and shaping, and can greatly reduce the process difficulty.

[0032] Preferably, the horizontal length L3 of the bottom edge is 0 nm to 1 μm.

[0033] The fourth aspect of the present application aims to solve the problem of preparing the above-mentioned semiconductor laser, and provides a preparation method of the semiconductor laser, comprising,

[0034] Step S1, forming a primary epitaxial structure on the substrate;

[0035] Step S2, forming a mask pattern of the anti-reflection window area on the basis of the primary epitaxial structure;

[0036] Step S3, performing isotropic etching of the end surface window area to form an anti-reflection window area, and the end surface etching area of the anti-reflection window area includes an arc-shaped structure;

[0037] Step S4, area etching is performed on the end surface active region, and a second anti-reflection region is formed in communication with the anti-reflection window region at the position corresponding to the active layer;

[0038] Step S5, the end surface etching area of the anti-reflection window region is protected;

[0039] Step S6, a separation layer, a waveguide layer and an InP cladding layer are sequentially grown on the end surface etching area of the anti-reflection window region to form an anti-reflection structure;

[0040] Step S7, secondary epitaxial growth is performed.

[0041] Compared with the prior art, the semiconductor laser and the preparation method thereof provided by the application have a simpler structure, are easier to grow and prepare, have good repeatability, can not only achieve better anti-reflection light effect and significantly improve the anti-reflection ability of the chip itself, but also can ensure that the efficiency of the active region forward light coupling into the waveguide is not affected. BRIEF DESCRIPTION OF DRAWINGS

[0042] In order to more clearly illustrate the technical solutions of the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0043] Figure 1 is a structure schematic diagram of a semiconductor laser provided by Embodiment 1 of the application.

[0044] Figure 2 is a structure schematic diagram of a semiconductor laser provided by Embodiment 1 of the application.

[0045] Figure 3 is a structure schematic diagram of a semiconductor laser provided by Embodiment 1 of the application.

[0046] Figure 4 is a structure schematic diagram of a semiconductor laser provided by Embodiment 1 of the application.

[0047] Figure 5 is a structure schematic diagram of a semiconductor laser provided by Embodiment 1 of the application.

[0048] Figure 6 This is a schematic diagram of the structure after growing an InP cladding layer II in the end face etching region of the anti-reflection window area in the fifth step of the semiconductor laser fabrication method provided in Embodiment 1 of the present invention.

[0049] Figure 7 This is a schematic diagram of a semiconductor laser provided in Embodiment 2 of the present invention, wherein the black arrow represents reflected light and the white arrow represents the forward light output from the active region.

[0050] Figure 8 This is a schematic diagram of the structure after the fourth step of the semiconductor laser fabrication method provided in Embodiment 2 of the present invention, in which a second anti-reflection region connected to the anti-reflection window region is formed at the position of the corresponding active layer.

[0051] Figure 9 This is a schematic diagram of the structure after growing an isolation layer in the end face etching area of ​​the anti-reflection window region in the sixth step of the semiconductor laser fabrication method provided in Embodiment 2 of the present invention.

[0052] Figure 10 This is a schematic diagram of the structure after growing a waveguide layer in the end face etching region of the anti-reflection window area in the sixth step of the semiconductor laser fabrication method provided in Embodiment 2 of the present invention.

[0053] Figure 11 This is a schematic diagram of the structure after growing an InP cladding layer II in the end face etching region of the anti-reflection window area in the sixth step of the semiconductor laser fabrication method provided in Embodiment 2 of the present invention.

[0054] Figure 12 This is a schematic diagram of the structure after secondary epitaxy in the seventh step of the semiconductor laser fabrication method provided in Embodiment 2 of the present invention.

[0055] Figure 13 This invention relates to an eye diagram result obtained by an anti-reflection semiconductor laser chip under a -12dB external reverse reflection light test condition;

[0056] Explanation of markings in the diagram

[0057] 10. InP buffer layer; 11. n-type cladding layer; 12. Active layer; 13. p-type cladding layer; 14. Raster layer; 15. p-type capping layer one; 16. p-type capping layer two.

[0058] 20. InP substrate; 21. p-type contact layer

[0059] 30. Antireflective coating; 31. High reflective coating

[0060] 40. Isolation layer; 41. Waveguide layer; 42. InP cladding layer II

[0061] 50. Anti-reflection window area; 51. Light-emitting end face; 52. Bottom profile; 53. Side profile; 54. Top profile.

[0062] 61. Part One, 62. Part Two

[0063] 70. Second anti-reflection area; 71. Bottom edge; 72. Side edge. Detailed Implementation

[0064] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0065] Example 1

[0066] This embodiment provides a semiconductor laser, including a substrate, preferably an InP substrate 20. An active region and an anti-reflection window region 50 are disposed on the substrate.

[0067] like Figure 1 As shown, an InP buffer layer 10, an n-type cladding layer 11, an active layer 12, a p-type cladding layer 13, a grating layer 14, and a p-type capping layer 15 are grown sequentially from bottom to top on the substrate. In this embodiment, the height H2 between the upper edge of the grating layer 14 and the upper edge of the p-type capping layer 15 can be 0 nm to 1 μm.

[0068] The anti-reflective window region 50 can be an area etched out above the substrate for growing the anti-reflective structure, such as... Figure 1 As shown, the anti-reflection window region 50 is located at the light-emitting end face 51, and the active layer 12 is connected to the anti-reflection window region 50, so that the forward light emitted from the active region can enter the anti-reflection window region 50 through the active layer 12 and finally be emitted through the light-emitting end face 51.

[0069] like Figure 1 As shown, in this embodiment, an anti-reflection structure is provided within the anti-reflection window region 50. The anti-reflection structure includes a waveguide layer 41 (or optical waveguide layer 41) and an isolation layer 40 (or optical isolation layer 40). One end of the waveguide layer 41 extends to the light-emitting end face 51, as shown... Figure 1As shown, the other end of the waveguide layer 41 extends in a direction away from the substrate and extends to a position at least above the grating layer 14. For example, this end of the waveguide layer 41 may preferably extend between the grating layer 14 and the p-type capping layer 15, or it may extend to a position flush with the p-type capping layer 15. Figure 1 As shown; of course, it can also be extended to a position above the p-type cladding layer 15; in fact, it is only necessary to ensure that this end of the waveguide layer 41 is higher than the active layer 12.

[0070] like Figure 1 As shown, the isolation layer 40 is disposed at least along the contour (i.e., side contour 53) of the anti-reflection window region 50 on the side opposite to the light-emitting end face 51, and the isolation layer 40 is located at least between the active layer 12 and the waveguide layer 41, so as to separate the active region from the waveguide layer 41 and the active region from the anti-reflection window region 50. Figure 1 As shown, this ensures that the active region and the waveguide layer 41 do not come into contact with each other, thereby achieving a better anti-reflection effect.

[0071] In implementation, the contour of the anti-reflective window region 50 includes a bottom contour 52, a side contour 53 facing away from the light-emitting end face 51, and a top contour 54. The side contour 53 is connected to the bottom contour 52 and the top contour 54, respectively, and the top contour 54 is located above the bottom contour 52. In implementation, the bottom contour 52 and the side contour 53 can each have various embodiments. For example, the bottom contour 52 and the side contour 53 can form an arc-shaped structure, which facilitates etching and the forming of the anti-reflective structure. Alternatively, the bottom contour 52 can be an inclined planar structure, a horizontal planar structure, an arc-shaped structure, etc., while the corresponding side contour 53 can be an inclined planar structure. Furthermore, in this embodiment, as shown in the figure, the bottom contour 52 can be a horizontal planar structure, and the side contour 53 can be an arc-shaped structure, such as... Figure 1 As shown, this contour shape facilitates etching and molding, and also makes it easier to grow the anti-reflection structure. Furthermore, in implementation, the sum of the horizontal length L1 of the bottom contour 52 and the horizontal length L2 of the side contour 53 (i.e., the length of the anti-reflection window region 50) can be 10~50 μm. Using this length not only ensures the output power of the laser chip but also achieves better anti-reflection performance. For example, as shown in the figure, the sum of L1 and L2 is 36 μm.

[0072] Furthermore, in implementation, the bottom profile 52 must be at least below the lower edge of the active layer 12. In implementation, the bottom profile 52 can be flush with the lower edge of the active layer 12, or it can be located between the lower edge of the active layer 12 and the lower edge of the n-type cladding 11, or it can be flush with the lower edge of the n-type cladding 11. Of course, it can also be below the lower edge of the n-type cladding 11, and the depth H1 below the lower edge of the n-type cladding 11 can be determined according to actual needs. Preferably, H1 can be 0 nm to 1 μm, for example, ... Figure 1 As shown, the depth H1 of the bottom contour 52 below the lower edge of the n-type cladding 11 can be 200 nm.

[0073] In implementation, the two ends of the top profile 54 are connected to the side profile 53 and the light-emitting end face 51, respectively, as follows: Figure 1 As shown, the top contour 54 is higher than or flush with the upper edge of the grating layer 14 to achieve a better anti-reflection effect. In implementation, the height H2 of the top contour 54 above the upper edge of the grating layer 14 can range from 0 nm to 1 μm. Furthermore, in a preferred embodiment, the top contour 54 can be flush with the upper edge of the p-type capping layer 15, such as... Figure 1 As shown, the height H2 between the upper edge of the grating layer 14 and the upper edge of the p-type capping layer 15 can be controlled within the range of 0nm~1μm.

[0074] In implementation, the shape of the waveguide layer 41 can be determined according to actual needs. However, the shape of the waveguide layer 41 can preferably be adapted to the shape formed by the bottom contour 52 and the side contour 53 in the anti-reflection window region 50, so as to facilitate the forming of the isolation layer 40 and the waveguide layer 41. For example, when the bottom contour 52 and the side contour 53 form an arc-shaped structure, the waveguide layer 41 can adopt an arc-shaped structure as a whole. Figure 1As shown, at this time, one end of the waveguide layer 41 located at the light-emitting end face 51 can correspond to the active layer 12, and the thickness of the waveguide layer 41 is greater than or equal to the thickness of the active layer 12, so that the light emitted from the active region in the forward direction can only be emitted from the light-emitting end face after passing through the waveguide layer 41. For example, to facilitate the fabrication and production of the waveguide layer 41, when the shapes of the bottom contour 52 and the side contour 53 are different, the waveguide layer 41 can include a first part 61 and a second part 62 connected to the first part 61. The first part 61 and the second part 62 can correspond to the bottom contour 52 and the side contour 53 respectively, so as to adapt to the shapes of the bottom contour 52 and the side contour 53 respectively. For example, when the bottom contour 52 is a horizontally arranged planar structure, the first part 61 can also be horizontally arranged and correspond to the active layer 12, and the thickness of the first part 61 is greater than or equal to the thickness of the active layer 12. The lower edge of the first portion 61 should be lower than or flush with the lower edge of the active layer 12, while the upper edge of the first portion 61 should be higher than or flush with the upper edge of the active layer 12. For example, as shown in the figure, in one embodiment, the lower edge of the first portion 61 can be flush with the lower edge of the n-type cladding 11, and the upper edge of the first portion 61 can be flush with the upper edge of the p-type cladding 13. In practice, the thickness H4 of the first portion 61 can be 0 nm to 1 μm; for example, in this embodiment, the thickness H4 of the first portion 61 is 250 nm. Figure 1 As shown, one end of the second part 62 is connected to the first part 61, and the other end extends to the top contour 54 in a direction away from the substrate, so that the second part 62 can fit the side contour 53 and face the light-emitting end face 51. In implementation, the second part 62 can be an arc-shaped structure, a planar structure, or other irregular structures, as long as it is ensured that the end of the second part 62 away from the first part 61 is higher than the grating layer 14; as an example, such as Figure 1 As shown, in this embodiment, the second part 62 adopts an arc-shaped structure to fit the shape of the side profile 53, and the second part 62 extends away from the first part 61 to the top profile 54 and is flush with the upper edge of the p-type cover layer 15. This not only achieves a better anti-reflection effect, but also makes it easier to form.

[0075] As mentioned above, since the isolation layer 40 can be set at least along the contour (i.e., side contour 53) of the anti-reflection window region 50 away from the light-emitting end face 51, in one embodiment, the isolation layer 40 can be set only between the side contour 53 and the waveguide layer 41. On the one hand, the isolation layer 40 can play a role in isolating the active region and the waveguide layer 41, which greatly increases the loss of external back-reflected light coupling into the active region, thereby effectively improving the anti-reflection capability of the chip itself. On the other hand, when the waveguide layer 41 includes an arc-shaped structure, especially when the second part 62 corresponding to the active region adopts an arc-shaped structure, the reflected light entering the waveguide layer 41 from the light-emitting end face 51 can be guided by the waveguide layer 41 and emitted from the other end of the waveguide layer 41, which can also improve the anti-reflection capability of the chip itself. The combination of these two aspects can not only achieve a better anti-reflection light effect, but also ensure that the efficiency of forward light coupling into the waveguide from the active region is not affected. At this time, the first part 61 of the waveguide layer 41 can be directly connected to the bottom contour 52.

[0076] In another embodiment, the isolation layer 40 can be disposed between the contour of the anti-reflection window region 50 and the waveguide layer 41, such as... Figure 1 As shown, isolation layers 40 are provided between waveguide layer 41 and side contour 53 and bottom contour 52, so that waveguide layer 41 is completely isolated from the contour of anti-reflection window region 50. With this structure, on the one hand, isolation layer 40 can isolate the active region from waveguide layer 41, which greatly increases the loss of external back-reflected light coupling into the active region, thereby effectively improving the anti-reflection capability of the chip itself. On the other hand, when waveguide layer 41 includes an arc structure, especially when the second part 62 corresponding to the active region adopts an arc structure, the reflected light entering waveguide layer 41 from light-emitting end face 51 can be guided by waveguide layer 41 and emitted from the other end of waveguide layer 41, which can also improve the anti-reflection capability of the chip itself. The combination of these two aspects can not only achieve better anti-reflection light effect, but also ensure that the efficiency of forward light coupling into the waveguide from the active region is not affected.

[0077] In implementation, the isolation layer 40 includes at least an InP cladding layer of InP material. Of course, the isolation layer 40 may also include a filler layer of other materials. For example, in this embodiment, the isolation layer 40 uses an InP cladding layer. The thickness of the isolation layer 40 can be determined according to actual needs. Preferably, such as... Figure 1As shown, the height H3 of the isolation layer 40 between the bottom contour 52 and the waveguide layer 41 can be 0 nm to 1 μm. For example, in this embodiment, H3 can be 200 nm. In a more complete solution, the anti-reflection structure further includes an InP cladding layer 2 42 disposed between the waveguide layer 41 and the top contour 54. For ease of molding, in a preferred embodiment, the upper edge of the InP cladding layer 2 42 can be flush with the upper edge of the waveguide layer 41, such as... Figure 2 As shown.

[0078] In addition, a p-type capping layer 16 is also covered above the p-type capping layer 15 and the InP cladding layer 42, and a p-type electrode contact layer is also covered above the p-type capping layer 16.

[0079] In this embodiment, the waveguide layer 41 can preferably be made of InGaAsP quaternary compound. Compared with Al-containing materials in the active region, it is less prone to oxidation defects. Moreover, the refractive index of the waveguide layer 41 is higher than that of InP cladding layer 1 and InP cladding layer 2 42. Waveguide layer 41 made of this material can effectively confine light to propagate within the optical waveguide. The refractive index of waveguide layer 41 can be adjusted and optimized by adjusting the composition of the InGaAsP quaternary compound.

[0080] Furthermore, in this embodiment, the InP material of InP cladding layer one is perfectly matched with the substrate lattice, and its thickness between the bottom profile 52 and the waveguide layer 41 is H3. The InP material of InP cladding layer two 42 is also perfectly matched with the substrate lattice.

[0081] In this embodiment, the contour of the anti-reflection window region 50 is constructed to include an arc-shaped structure, which is beneficial for the high-quality growth of the MO epitaxial film at the docking interface. The growth preparation is simple and has good repeatability.

[0082] Based on the semiconductor laser provided in this embodiment, this embodiment also provides a method for fabricating the semiconductor laser, including the following main steps:

[0083] Step S1: Form a primary epitaxial structure on the substrate. Specifically, an InP buffer layer 10, an n-type cladding layer 11, an active layer 12, a p-type cladding layer 13, a grating layer 14, and a p-type capping layer 15 can be sequentially deposited on an indium phosphide (InP) substrate 20 using metal-organic chemical vapor deposition (MOCVD). Figure 3 As shown.

[0084] Step S2: A mask pattern for the anti-reflection window region 50 is formed based on the primary epitaxial structure. Specifically, a SiO2 mask layer can be deposited on the surface of the p-type capping layer 15 using plasma-enhanced chemical vapor deposition (PECVD). The material of the mask layer can be Si3N4 or SiO2. The mask pattern is then fabricated using photolithography to expose the anti-reflection window region 50 of the light-emitting end face 51.

[0085] Step S3: Perform isotropic etching on the end-face window area to form the anti-reflection window area 50, such as... Figure 3 As shown, the end face etching area of ​​the anti-reflection window region 50 includes an arc-shaped structure. The specific process can be as follows: First, the mask layer is etched using a RIE dry etching process. Then, different materials in the window region are etched using a wet etching solution (etching solution one includes Br2, HBr, H3PO4, and H2O). Along the top-to-bottom direction, the etched layers include a p-type capping layer 15 (InP), a grating layer 14 (InGaAsP), a p-type cladding layer 13 (InAlAs, InAlGaAs), and an active layer 12 (InAlGaAs). During implementation, the position of the bottom contour 52 of the designed anti-reflection window region 50 can be used to determine whether to continue etching the lower n-type cladding layer 11 (InAlAs, InAlGaAs) and the InP buffer layer 10. For example, in this embodiment, after etching the active layer 12 (InAlGaAs), the lower n-type cladding layer 11 (InAlAs, InAlGaAs) and part of the InP buffer layer 10 are etched. Figure 3 As shown, the bottom contour 52 of the anti-reflection window region 50 forms a horizontally arranged planar structure, and the side contour 53 of the anti-reflection window region 50 forms an arc-shaped structure, with the arc-shaped structure facing away from the substrate. In this step, the curvature of the arc-shaped structure can be optimized and controlled by adjusting the etching rate and etching time of the wet etching solution. Simultaneously, this step can also control the sum of the horizontal length L1 of the bottom contour 52 and the horizontal length L2 of the side contour 53 (i.e., the length of the anti-reflection window region 50) to be 10~50 μm. For example, in one embodiment, the sum of the lengths L1+L2 of the end-face etching area (in this embodiment, the end-face etching area includes the bottom contour 52 and the side contour 53 connected thereto) can be 40 μm, the etching depth H1 on the InP buffer layer 10 can be 200 nm, and the spacing H2 between the upper edge of the p-type capping layer 15 and the grating layer 14 can be 300 nm. This etching solution has isotropic etching characteristics; by adjusting the etching solution ratio and controlling the etching rate, a structure like... Figures 4-6 The bottom profile 52 and side profile 53 are shown.

[0086] Step S4 involves protecting the end face etched area of ​​the anti-reflection window region 50. Specifically, a saturated ammonium sulfide solution can be used to treat the oxides on the etched surfaces (such as the bottom contour 52 and the side contour 53) to generate a sulfide protective layer.

[0087] Step S5: In the end face etching area of ​​the anti-reflection window region 50, the isolation layer 40, the waveguide layer 41, and the InP cladding layer 42 are sequentially grown to form an anti-reflection structure, such as... Figures 4-6As shown. Specifically, an isolation layer 40, a waveguide layer 41, and an InP cladding layer 2 42 can be sequentially deposited in the etched area on the end face using MOCVD epitaxy. In practice, the isolation layer 40 includes at least an InP cladding layer 1, and the waveguide layer 41 can preferably be made of an InGaAsP quaternary compound, so that the refractive index of the waveguide layer 41 is higher than that of the InP cladding layer 1 and the InP cladding layer 2 42, thereby effectively confining light to propagate within the optical waveguide. Simultaneously, this step also requires controlling the position and thickness of the waveguide layer 41, especially the position and thickness of the portion of the waveguide layer 41 corresponding to the active layer 12 (as described above, the first portion 61), ensuring that this portion corresponds to the active layer 12 and its thickness is greater than or equal to the thickness of the active layer 12. For example, in this embodiment, as... Figures 4-6 As shown, the thickness H3 of the isolation layer 40 between the bottom contour 52 and the waveguide layer 41 can be controlled to be 200 nm, the thickness H4 of the first part 61 of the waveguide layer 41 can be controlled to be 250 nm, and the thickness of the second InP cladding layer 42 can be determined by H2. That is, the upper edge of the second InP cladding layer 42 can be located between the upper edge of the grating layer 14 and the p-type capping layer 15, for example, as Figure 1 As shown, the InP cladding layer 42 can be epitaxially grown to be flush with the upper edge of the p-type capping layer 15.

[0088] In a more refined version, this process also includes step S6, performing secondary epitaxial growth. Specifically, MOCVD can be used to sequentially deposit a p-type capping layer 16 and a p-type contact layer 21 above the p-type capping layer 15 and the InP cladding layer 42, as follows: Figure 1 As shown.

[0089] Step S7: Perform chip fabrication. A ridge waveguide or buried heterojunction structure can be formed on the wafer using a common photolithography process, followed by the formation of p-metal electrodes. Then, the back side of the InP substrate 20 is thinned and polished to 100μm ± 10μm, and an n-metal electrode is deposited. After the wafer is separated by bar strips, a film is deposited on the light-emitting end face 51 of the chip, as shown below. Figure 7 As shown, an anti-reflection film 30 can be deposited on the light-emitting end face 51. At the same time, a high-reflection film 31 can also be deposited on the other side of the active region. Thus, the process is completed, and an anti-reflection semiconductor laser chip is obtained.

[0090] In this embodiment, the material composition of the active region of the chip can be either InAlGaAs quaternary compound or InGaAsP quaternary compound, and the optical waveguide structure can be either a ridge waveguide structure or a BH (buried heterojunction) structure.

[0091] The method used to prepare semiconductor lasers is simple, has good repeatability, and can achieve superior anti-reflection performance.

[0092] Example 2

[0093] The main difference between this embodiment 2 and embodiment 1 is that, in the semiconductor laser provided in this embodiment, a second anti-reflection region 70 is further provided above the substrate. The second anti-reflection region 70 is disposed on the side contour 53 of the anti-reflection window region 50 and is connected to the anti-reflection window region 50. The second anti-reflection region 70 at least corresponds to the active layer 12. Figure 7 As shown, the second anti-reflection region 70 is filled with an isolation layer 40, which can further increase the spacing between the active layer 12 and the waveguide layer 41, thereby further increasing the loss of external back-reflected light coupled into the active region along the waveguide layer 41, and thus further improving the chip's own anti-reflection capability.

[0094] In implementation, the outline of the second anti-reflection region 70 includes a bottom edge 71 and a side edge 72 that faces away from the light-emitting end face 51 and is connected to the active region. The side edge 72 is connected to the bottom edge 71, with its upper end higher than the active layer 12 and its lower end lower than the active layer 12. The bottom edge 71 and the side edge 72 can be implemented in various ways. For example, the bottom edge 71 and the side edge 72 can form an arc-shaped structure, which facilitates etching. Alternatively, the bottom edge 71 can be an inclined planar structure, a horizontal planar structure, an arc-shaped structure, etc., while the corresponding side edge 72 can be an inclined planar structure. Furthermore, in the preferred embodiment provided in this example, the bottom edge 71 can be a horizontal planar structure, such as... Figure 7 As shown, side 72 can be an arc-shaped structure, such as... Figure 7 As shown, this contour shape is easier to etch and can greatly reduce the difficulty of the process.

[0095] In implementation, the area of ​​the second anti-reflective region 70 can be determined according to implementation requirements. In a preferred embodiment, the upper end of the side edge 72 can be higher than or flush with the upper edge of the p-type cladding 13, and the lower end of the bottom edge 71 can be lower than or flush with the lower edge of the n-type cladding 11. Figure 7 As shown. Meanwhile, in a preferred embodiment, the horizontal length L3 of the bottom edge 71 can be 0 nm to 1 μm. Using this length not only ensures the output power of the laser chip but also achieves better anti-reflection performance. For example, as... Figure 2 As shown, in this embodiment, L3 is 200nm.

[0096] In this embodiment, the provision of the second anti-reflection region 70 is beneficial for filling the isolation layer 40 and reducing the resonance disturbance of external back-reflected light.

[0097] Based on the semiconductor laser provided in this embodiment, this embodiment also provides a method for fabricating the semiconductor laser, including the following main steps:

[0098] Step S1: Form a primary epitaxial structure on the substrate. Specifically, an InP buffer layer 10, an n-type cladding layer 11, an active layer 12, a p-type cladding layer 13, a grating layer 14, and a p-type capping layer 15 can be sequentially deposited on an indium phosphide (InP) substrate 20 using metal-organic chemical vapor deposition (MOCVD). Figure 3 As shown.

[0099] Step S2: A mask pattern for the anti-reflection window region 50 is formed based on the primary epitaxial structure. Specifically, a SiO2 mask layer can be deposited on the surface of the p-type capping layer 15 using plasma-enhanced chemical vapor deposition (PECVD), and the mask pattern can be fabricated using photolithography to expose the anti-reflection window region 50 of the light-emitting end face 51.

[0100] Step S3: Perform isotropic etching on the end-face window area to form the anti-reflection window area 50, such as... Figure 3 As shown, the end face etching area of ​​the anti-reflection window region 50 includes an arc-shaped structure. The specific process can be as follows: First, the mask layer is etched using a RIE dry etching process. Then, different materials in the window region are etched using a wet etching solution (etching solution one includes Br2, HBr, H3PO4, and H2O). Along the top-to-bottom direction, the etched layers include a p-type capping layer 15 (InP), a grating layer 14 (InGaAsP), a p-type cladding layer 13 (InAlAs, InAlGaAs), and an active layer 12 (InAlGaAs). During implementation, the position of the bottom contour 52 of the designed anti-reflection window region 50 can be used to determine whether to continue etching the lower n-type cladding layer 11 (InAlAs, InAlGaAs) and the InP buffer layer 10. For example, in this embodiment, after etching the active layer 12 (InAlGaAs), the lower n-type cladding layer 11 (InAlAs, InAlGaAs) and part of the InP buffer layer 10 are etched. Figure 8As shown, the bottom contour 52 of the anti-reflection window region 50 forms a horizontally arranged planar structure, and the side contour 53 of the anti-reflection window region 50 forms an arc-shaped structure, with the arc-shaped structure facing away from the substrate. In this step, the curvature of the arc-shaped structure can be optimized and controlled by adjusting the etching rate and etching time of the wet etching solution. At the same time, this step can also control the sum of the horizontal length L1 of the bottom contour 52 and the horizontal length L2 of the side contour 53 (i.e., the length of the anti-reflection window region 50) to be 10~50μm. For example, in one embodiment, the sum of the lengths L1+L2 of the end face etching area can be 36μm, the etching depth H1 on the InP buffer layer 10 can be 200 nm, and the spacing H2 between the upper edge of the p-type capping layer 15 and the grating layer 14 can be 100 nm.

[0101] Step S4: Perform area etching in the active region of the end face, and form a second anti-reflection region 70 connected to the anti-reflection window region 50 at the position corresponding to the active layer 12, such as... Figure 8 As shown. Specifically, a wet etching solution two (including H2SO4, H2O2, and H2O) can be used to etch at least the active layer 12 within the window region. Based on the semiconductor laser structure described above, in this step, the wet etching solution two can also be used to etch the film layer adjacent to the active layer 12 to obtain a second anti-reflection region 70 of different areas. For example, in this embodiment, a wet etching solution two is used to etch the Al-containing film layers such as the n-type cladding 11, the active layer 12, and the p-type cladding 13 within the window region to form a... Figures 9-11 The second anti-reflection region 70 shown can have a length of 0 nm to 1 μm in practice. For example, in this embodiment, L3 can be 200 nm.

[0102] Step S5 involves protecting the end face etched area of ​​the anti-reflective window region 50. Specifically, a saturated ammonium sulfide solution can be used to treat the oxides on the etched surfaces (such as the bottom contour 52, side contour 53, bottom edge 71, and side edge 72) to generate a sulfide protective layer.

[0103] Step S6: In the end-face etched area of ​​the anti-reflection window region 50, the isolation layer 40, the waveguide layer 41, and the second InP cladding layer 42 are sequentially deposited to form an anti-reflection structure. Specifically, the isolation layer 40, the waveguide layer 41, and the second InP cladding layer 42 can be sequentially deposited in the end-face etched area using MOCVD epitaxy. In practice, the isolation layer 40 includes at least the first InP cladding layer and can fill the second anti-reflection region 70. Simultaneously, this step also requires controlling the position and thickness of the waveguide layer 41, especially the position and thickness of the portion of the waveguide layer 41 corresponding to the active layer 12 (as described above, the first portion 61), ensuring that this portion corresponds to the active layer 12 and that its thickness is greater than or equal to the thickness of the active layer 12. For example, in this embodiment, as... Figures 9-11 As shown, the thickness H3 of the isolation layer 40 between the bottom contour 52 and the waveguide layer 41 can be controlled to be 200 nm, the thickness H4 of the first part 61 of the waveguide layer 41 can be controlled to be 150 nm, and the thickness of the second InP cladding layer 42 can be determined by H2. That is, the upper edge of the second InP cladding layer 42 can be located between the upper edge of the grating layer 14 and the p-type capping layer 15, for example, as... Figure 12 As shown, the InP cladding layer 42 can be epitaxially grown to be flush with the upper edge of the p-type capping layer 15.

[0104] In a more refined version, this process also includes step S7, performing secondary epitaxial growth. Specifically, MOCVD can be used to sequentially deposit a p-type capping layer 16 and a p-type contact layer 21 above the p-type capping layer 15 and the InP cladding layer 42, as follows: Figure 7 As shown.

[0105] Step S8 involves chip fabrication. A ridge waveguide or buried heterojunction structure can be formed on the wafer using a common photolithography process, followed by the formation of p-metal electrodes. Then, the back side of the InP substrate 20 is thinned and polished to 100μm ± 10μm, and an n-metal electrode is deposited. After the wafer is separated by bar strips, a film is deposited on the light-emitting end face 51 of the chip, as shown below. Figure 13 As shown, an anti-reflection film 30 can be deposited on the light-emitting end face 51. At the same time, a high-reflection film 31 can also be deposited on the other side of the active region. Thus, the process is completed, and an anti-reflection semiconductor laser chip is obtained.

[0106] ​The image shows the eye diagram results of the semiconductor laser chip prepared using this method under a -12dB external back-reflection light test condition. As can be seen from the figure, on the one hand, the prepared semiconductor laser chip meets the usage requirements when no isolator is installed at the module end, indicating that the prepared semiconductor laser chip has better anti-reflection performance. On the other hand, it can also be seen that the prepared semiconductor laser chip's own anti-reflection capability covers the entire temperature range (-40~85℃), which is superior to existing semiconductor laser chips.

[0107] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A semiconductor laser, comprising a substrate, an active region and an anti-reflection window region disposed above the substrate, the active region comprising an active layer and a grating layer, the anti-reflection window region being located at an emission facet, the active region being in abutment with the anti-reflection window region, the anti-reflection window region comprising a bottom profile, a side profile facing away from the emission facet, and a top profile, the side profile being connected with the bottom profile and the top profile respectively, the bottom profile being lower than a lower edge of the active layer, the top profile being flush with or higher than an upper edge of the grating layer, and an anti-reflection structure being disposed in the anti-reflection window region, characterized in that, The bottom profile is a horizontally arranged planar structure, the side profile is an arc-shaped structure, and the arc-shaped structure faces away from the substrate, and the sum of the horizontal length L1 of the bottom profile and the horizontal length L2 of the side profile is 10-50 μm; The anti-reflection structure comprises a waveguide layer, an isolation layer, and InP cladding layer two, wherein, The material of the waveguide layer adopts an InGaAsP quaternary compound, the waveguide layer comprises a first part and a second part connected with the first part, the first part and the second part correspond to the bottom profile and the side profile respectively, one end of the first part extends to the light emitting end face, one end of the second part extends to the top profile, the first part is horizontally arranged and corresponds to the active layer, the thickness H4 of the first part is 150 nm-1000 nm, the lower edge of the first part is lower than or flush with the lower edge of the active layer, and the upper edge of the first part is higher than or flush with the upper edge of the active layer, and the second part is an arc-shaped structure; the shape of the waveguide layer is adapted to the shape composed of the bottom profile and the side profile of the anti-reflection window area; The isolation layer is arranged along the profile of the anti-reflection window area, and the isolation layer is arranged between the side profile and the waveguide layer and between the bottom profile and the waveguide layer, for separating the active region and the waveguide layer, the height of the isolation layer between the bottom profile and the waveguide layer is 200 nm-1 μm, and the isolation layer adopts InP cladding layer one of InP material; InP cladding layer two is arranged between the waveguide layer and the top profile.

2. The semiconductor laser of claim 1, wherein, The n-type cladding layer is arranged below the active layer, and the depth H1 of the bottom profile below the lower edge of the n-type cladding layer is 200 nm.

3. The semiconductor laser of claim 1, wherein, A second anti-reflection area is further arranged above the substrate, the second anti-reflection area is arranged in the side profile of the anti-reflection window area and communicates with the anti-reflection window area, the second anti-reflection area corresponds to at least the active layer, and the second anti-reflection area is filled with the isolation layer.

4. The semiconductor laser of claim 3, wherein, The second anti-reflection area comprises a bottom edge and a side edge facing away from the light emitting end face and connected with the active region, the side edge is connected with the bottom edge, the upper end of the side edge is higher than the active layer, and the lower end of the bottom edge is lower than the active layer.

5. The semiconductor laser of claim 4, wherein, The active region further comprises the n-type cladding layer arranged below the active layer and the p-type cladding layer arranged above the active layer, the upper end of the side edge is higher than or flush with the upper edge of the p-type cladding layer, and the lower end of the bottom edge is lower than or flush with the lower edge of the n-type cladding layer; The bottom edge is a horizontally arranged planar structure, and the side edge is an arc-shaped structure.

6. A method of manufacturing the semiconductor laser according to any one of claims 1 to 2, characterized by, Comprising, Step S1, forming a first epitaxial structure on a substrate; Step S2, forming a mask pattern of an anti-reflection window area on the basis of the first epitaxial structure; Step S3, performing isotropic etching of the end face window area to form an anti-reflection window area, and the end face etching area of the anti-reflection window area comprises an arc-shaped structure; Step S4, performing protection treatment on the end face etching area of the anti-reflection window area; Step S5, sequentially growing an isolation layer, a waveguide layer, and InP cladding layer two on the end face etching area of the anti-reflection window area to form an anti-reflection structure; Step S6, performing secondary epitaxial growth.

7. A method of manufacturing a semiconductor laser as claimed in any one of claims 3-5, characterized in that Comprising, Step S1, forming a first epitaxial structure on a substrate; Step S2, forming a mask pattern of the anti-reflection window region on the basis of a first epitaxial structure; Step S3, performing anisotropic etching on the facet window region to form the anti-reflection window region, and the facet etching area of the anti-reflection window region comprises an arc-shaped structure; Step S4, performing area etching on the facet active region, and forming a second anti-reflection region in communication with the anti-reflection window region at a position corresponding to the active layer; Step S5, performing a protection treatment on the facet etching area of the anti-reflection window region; Step S6, sequentially growing a separation layer, a waveguide layer and an InP cladding layer two on the facet etching area of the anti-reflection window region to form an anti-reflection structure; Step S7, performing a second epitaxial growth.

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