Active power factor correction circuit based on inductance average current compensation, corrector and electric appliance

Abstract

The application provides an active power factor correction circuit based on inductance average current compensation, a corrector and a user, solves the problem of poor linearity between average current and input voltage caused by inductance negative current in the resonant state of the CrM APFC circuit, samples the maximum negative current during the resonance, controls the compensation on time through the detection of the current signal when conducting, realizes the complete compensation of the negative current influence, and especially the compensation mode and the compensation circuit provided by the application are especially prominent in effect and practical value in the application inconvenient for detecting the input voltage.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of critical current mode (CrM) active power factor correction (APFC) circuit, in particular to an active power factor correction circuit based on inductance average current compensation, a corrector and an electrical appliance. BACKGROUND

[0002] For electrical appliances connected to AC mains, there are often requirements for power factor (PF) and total harmonic distortion (THD), and with increasingly stringent national regulations, the PF and THD performance requirements for electrical appliances are more common. Electronic devices often need a power factor correction circuit to meet the PF and THD requirements in the certification standard. In small power applications such as LED lighting fixtures, simple active power factor correctors are widely used due to considerations of size, cost, and structure.

[0003] The active power factor correction (APFC) circuit structure of the critical mode (CrM) of inductance current is simple, has small electromagnetic interference, and is high in efficiency, and is the mainstream APFC structure for small and medium power supplies. In general, there are mainly two structures for CrM APFC controllers:

[0004] One structure is to use a multiplier and a peak current control structure. The controller of this structure samples the rectified AC voltage through a voltage dividing resistor, multiplies the control voltage with the multiplier to obtain a current signal, and achieves the purpose of tracking the change of the input voltage by the current signal. The APFC controller using this structure can obtain good PF indicators due to the use of the multiplier, and can compensate the input inductance with the input voltage signal to achieve good THD indicators because the input voltage can be sampled. However, this structure is relatively complex due to the use of the multiplier and the external voltage dividing resistor network, and has a slightly higher cost compared with the structure without the multiplier.

[0005] The other structure is a CrM APFC controller using fixed on-time control. The on-time remains constant during operation, and the relationship between the inductance current and the on-time and the input voltage in the CrM mode is used to realize the natural following of the input current to the change of the input voltage, achieving high PF. The APFC controller using this structure has the characteristics of no need to sample the input voltage, no multiplier, simple structure, and low cost, but the inductance current is followed by the input voltage and the on-time, and the non-ideal factors of the input voltage will affect the relationship between the inductance current and the input voltage, so the PF performance is slightly inferior to that of the multiplier structure, and since the input voltage is not sampled, it is difficult to effectively compensate the on-time, so the THD performance is also relatively poor.

[0006] The input capacitor of the PFC circuit is an important factor affecting the THD index. The main influence of the input capacitor on the THD is due to the charging and discharging factors. Since the inductor current becomes small when the rectified AC voltage approaches the valley, the capacitor voltage discharges at a speed that cannot keep up with the falling speed of the input line voltage, causing the so-called crossover distortion. The smaller the power supply power is, the greater the input capacitor is, and the greater the influence on the THD is.

[0007] Figure 1 A PFC circuit of a typical boost structure is shown, which includes an APFC integrated controller 101, an input capacitor 102, an inductor 103, a diode 104, an output capacitor 105, a power MOS tube 106, and a current sampling resistor 107. The gate end of the APFC integrated controller 101 is connected to the gate G of the power switch 106, and the sampling current cs end of the APFC integrated controller 101 is connected to the source of the power switch 106. The source of the power switch 106 is also connected to one end of the current sampling resistor 107, and the other end of the current sampling resistor 107 is grounded. The drain of the power switch 106 is connected to the anode of the diode 104 and one end of the inductor 103. The other end of the inductor 103 is connected to the input voltage Vin and one end of the input capacitor 102. The other end of the input capacitor 102 is grounded. The cathode of the diode 104 is connected to the output voltage Vout and one end of the output capacitor 105. The other end of the output capacitor 105 is grounded. In normal operation, the input voltage Vin is the DC voltage obtained by rectifying the sinusoidal voltage, the output voltage Vout is the stable DC voltage, the inductor works in CrM mode, and the high level duration Ton of the gate signal remains unchanged.

[0008] Figure 2 The waveforms of the gate drive signal gate, the power MOS drain drain, the inductor current iL, and the current signal cs in the normal working state are shown. Figure 2The left part of the dividing line is the waveform diagram when Vin is at a higher voltage Vinh, and the right part is the waveform diagram when Vin is at a lower voltage Vinl, and the on time Ton remains unchanged. At Vinh, the inductor current reaches iLpk at the end of Ton, and reaches -iLnpk during the resonance, and the average inductor current in a switching cycle is iL(avg) = 0.5*(iLpk-iLnpk). Similarly, at Vinl, the cycle average current is iL(avg)1 = 0.5*(iLpk1-iLnpk1). Due to the characteristics of the circuit, the lower Vin is, the smaller -iLnpk is, i.e. -iLnpk1 <-iLnpk (the absolute value of the inductor current is larger), which causes that if the on time Ton remains unchanged, the linearity of the average inductor current with respect to Vin is poor, and due to the negative inductor current, the average inductor current has already decreased to zero when Vin has not yet decreased to zero, which has an adverse effect on THD.

[0009] In order to achieve the compensation purpose, the existing method needs to use an input voltage signal, which is more suitable for an APFC controller with a multiplier structure, and for an APFC controller with a fixed on time structure, a better inductor current compensation method is needed. SUMMARY

[0010] In view of the above-mentioned disadvantages of the prior art, the present application provides an active power factor correction circuit based on inductor average current compensation, a corrector and an electrical appliance, which are used to solve the problem that the existing inductor current compensation method is not suitable for an APFC circuit with a fixed on time.

[0011] In order to achieve the above-mentioned purpose, the present application provides an active power factor correction circuit based on inductor average current compensation, comprising: an integrated controller with an inductor average compensation circuit, including a control voltage port connected to a control voltage signal vctrl, a gate drive output port outputting a gate drive signal gate, and a sampling current port inputting a current signal cs; a power inductor, a first end of which is connected to a direct current input voltage, and a second end of which is coupled to an output end; a power MOS tube, a drain of which is connected to the second end of the power inductor, a gate of which is connected to the gate drive output port of the integrated controller, and a source of which is connected to a first end of a sampling resistor and connected to the sampling current port of the integrated controller, and a second end of the sampling resistor is grounded.

[0012] In some embodiments of the present application, the inductance average compensation circuit comprises: a conduction time adjustment circuit, a switch logic circuit, a gate drive circuit, a zero current detection circuit, a leading edge blanking circuit, a negative current sampling and compensation circuit; wherein: the first input terminal of the conduction time adjustment circuit is connected with a control voltage signal vctrl, the second input terminal is connected with the first output terminal of the switch logic circuit to input a switch signal on, the third input terminal is connected with the output terminal of the negative current sampling and compensation circuit to input a conduction time timing enable signal en_ton, and the output terminal is connected with the first input terminal of the switch logic circuit to output a conduction time end signal tout; the first input terminal of the switch logic circuit is connected with the conduction time end signal tout, the second input terminal is connected with the output terminal of the zero current detection circuit to input a zero current signal zcs, the first output terminal outputs the switch signal on, the second output terminal is connected with the second input terminal of the negative current sampling and compensation circuit to output a negative current sampling control signal smp_cs, and the third output terminal is connected with the third input terminal of the negative current sampling and compensation circuit to output an inductance discharge signal tdis; the input terminal of the gate drive circuit is connected with the switch signal on, and the output terminal outputs a gate drive signal gate; the first input terminal of the zero current detection circuit is connected with the switch signal on, the second input terminal is connected with the gate drive signal gate, and the output terminal is connected with the second input terminal of the switch logic circuit to output the zero current signal zcs; the input terminal of the leading edge blanking circuit is connected with the switch signal on, and the output terminal is connected with the sixth input terminal of the negative current sampling and compensation circuit to output a leading edge blanking signal leb; the first input terminal of the negative current sampling and compensation circuit is connected with a current signal cs, the second input terminal is connected with the negative current sampling control signal smp_cs, the third input terminal is connected with the inductance discharge signal tdis, the fourth input terminal is connected with the switch signal on, the fifth input terminal is connected with the control voltage signal vctrl, the sixth input terminal is connected with the leading edge blanking signal leb, and the output terminal outputs the conduction time timing enable signal en_ton.

[0013] In some embodiments of the present application, the on-time adjusting circuit generates an on-time end signal tout according to the input control voltage signal vctrl, a switch signal on and an on-time timing enable signal en_ton; the switch logic circuit generates the switch signal on, a negative current sampling control signal smp_cs and an inductor discharge signal tdis according to a zero current signal zcs and the on-time end signal tout, to control the negative voltage of the sampled and held current signal cs; the gate drive circuit generates a gate drive signal gate according to the input switch signal on, to drive the gate of the power MOSFET; the zero current detection circuit detects the zero crossing state of the inductor current through the gate drive signal gate, and generates the zero current signal zcs; the negative current detection and compensation circuit samples and holds the minimum negative voltage of the current signal cs under the control of the negative current sampling control signal smp_cs and the inductor discharge signal tdis, and generates a reference voltage signal min_cs; after the switch signal on is turned on and the leading edge blanking signal leb is delayed, the min_cs and the current signal cs are compared by a voltage comparator to generate an enable signal cs_en, to control the on-time adjusting circuit to form on-time compensation; to prevent the on-time from being too long, the control voltage signal vctrl and the switch signal on generate a maximum on-time control signal max_ton related to the size of vctrl, to limit the on-time, and after the logical operation of max_ton and cs_en, the on-time timing enable signal en_ton is generated.

[0014] In some embodiments of the present application, the on-time adjusting circuit comprises: a logic gate I101, an input end of which is connected to a switch signal on, and an output end of which is connected to a gate of an NMOSFET M101; a logic gate I102, an input end of which is connected to an on-time timing enable signal en_ton, and an output end of which is connected to a gate of an NMOSFET M102; the NMOSFET M101, a drain of which is connected to a positive input end of a logic gate I104, and a source of which is grounded; the NMOSFET M102, a drain of which is connected to a drain of the NMOSFET M101, and a source of which is grounded; a capacitor C101, a first end of which is connected to the drains of the NMOSFET M101 and the NMOSFET M102, and a second end of which is grounded; a current source I103, a first end of which is connected to a power supply voltage vdd, and a second end of which is connected to the first end of the capacitor C101; a comparator I104, a negative input end of which is connected to a control voltage signal vctrl, a positive input end of which is connected to the first end of the capacitor C101, and an output end of which outputs an on-time end signal tout; wherein when the switch signal on and the on-time timing enable signal en_ton are flipped from low level to high level, the NMOSFET M101 and the NMOSFET M102 are turned off, the constant current source I103 charges the capacitor C101, and when the voltage at the first end of the capacitor C101 reaches the control voltage signal vctrl, the comparator I104 flips to output the on-time end signal tout, thereby generating a timing signal related to the control voltage signal vctrl.

[0015] In some embodiments of the present application, the negative current sampling and compensation circuit comprises: an amplifier I601, comparators I602 and I605, resistors R601 and R602, NMOSFET M601, M602, M603, M604 and M605, capacitors C601 and C602, a current source I603, logic gates I604 and I606.

[0016] The positive input terminal of the amplifier I601 is grounded, the negative input terminal is connected to the second terminal of the resistor R601, and the output terminal is connected to the gate of the NMOSFET M603; the first terminal of the resistor R601 is connected to the current signal cs, and the second terminal is connected to the first terminal of the resistor R602; the second terminal of the resistor R602 is connected to the source of the NMOSFET M604 and the negative input terminal of the comparator I602; the drain of the NMOSFET M601 is connected to the common terminal of the resistors R601 and R602, the gate is connected to the negative current sampling control signal smp_cs, and the source is grounded; the drain of the NMOSFET M602 is connected to the first terminal of the capacitor C601 and the gate of the NMOSFET M604 and is connected to the source of the NMOSFET M603; the second terminal of the capacitor C601 is grounded; the drains of the NMOSFET M603 and M604 are connected to the power voltage vdd; the positive input terminal of the comparator I602 is connected to the current signal cs, the I602 enable control terminal is connected to the front porch blanking signal leb, and the output terminal is connected to the first input terminal of the logic gate I606 to output the signal cs_en; the input terminal of the logic gate I604 is connected to the switch signal on, and the output terminal is connected to the gate of the NMOSFET M605; the drain of the NMOSFET M605, the first terminal of the capacitor C602 and the second terminal of the current source I603 are connected together and connected to the positive input terminal of the comparator I605; the first terminal of the current source I603 is connected to the power voltage vdd; the second terminal of the capacitor C602 is grounded; the negative input terminal of the comparator I605 is connected to the control voltage signal vctrl, and the output terminal is connected to the second input terminal of the logic gate I606 to output the signal max_ton; and the output terminal of the logic gate I606 outputs the turn-on time timing enable signal en_ton.

[0017] In some embodiments of the present application, the amplifier I601, the resistors R601 and R602, the MOSFET M601-M604 and the capacitor C601 in the negative current sampling and compensation circuit constitute a voltage conversion and peak sampling and holding circuit; the peak sampling and holding circuit is divided into a sampling mode and a holding mode when working; when the signal tdis is a logic high level, the MOSFET 602 is turned on to discharge C601 to zero, and the smp_cs is at a low level in the sampling mode; after the sampling mode ends, the smp_cs is flipped from a low level to a high level to enter the holding mode.

[0018] In some embodiments of the present application, in the sampling mode, the amplifier I601, the MOSFET M603-604, the resistors R601-R602 form a negative feedback circuit, the cs voltage is a negative voltage, under the action of the amplifier I601, the MOSFET M603-604 drives min_cs to generate a positive voltage to maintain the negative phase terminal voltage of the amplifier I601 equal to the zero voltage of the positive phase terminal; the voltage of the output signal min_cs at the second end of the resistor R602 is recorded as Vmin_cs, and the cs voltage is recorded as V_cs, then the size of Vmin_cs is:

[0019]

[0020] In some embodiments of the present application, in the holding mode, the MOSFET M601 connects the resistor R601 and the common terminal of the resistor R601 to the ground, Vmin_cs keeps the maximum value sampled unchanged and is sent to the negative phase input terminal of the comparator I602 to compare with the cs signal voltage.

[0021] In some embodiments of the present application, under the action of the compensation circuit, the periodic average value of the inductor current is:

[0022]

[0023] Then:

[0024] By adjusting the proportion of the resistors R602 and R601, the compensation amount is set, if the size of R602 is equal to that of R601, then:

[0025]

[0026] Wherein, -iLnpk is the maximum negative current of the inductor during resonance, iLpk is the inductor current at the end of Ton, L is the inductor value; Ton is the fixed on time of the on-time adjustment circuit; Vin is the voltage after rectification to the inductor before the boost circuit; ΔiL+ refers to the increase of the inductor current within the on-time Ton from the moment when the cs signal reaches the min_cs signal; vin refers to the voltage applied to the inductor during the on time of the switch; the inductor current increases linearly within the Ton time

[0027] To achieve the above object, the present application provides an active power factor corrector, comprising the active power factor correction circuit based on inductor average current compensation.

[0028] To achieve the above object, the present application provides a user connected to AC mains, comprising the active power factor corrector.

[0029] As described above, the application relates to an active power factor correction circuit, a corrector and an electrical appliance based on inductance average current compensation, which has the following beneficial effects: the application solves the problem of poor linearity between average current and input voltage caused by negative inductance current in the resonant state of the CrM APFC circuit, the maximum negative current is sampled during the resonance, and the compensation on time is controlled by detecting the current signal during the conduction, so that the influence of the negative current is completely compensated, and the compensation method and the compensation circuit provided by the application do not require additional ports, and the effect and practical value are particularly prominent in applications where it is inconvenient to detect the input voltage. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 A PFC circuit structure schematic diagram is shown as a typical boost structure.

[0031] Figure 2 Waveforms of a gate driving signal gate, a power MOS drain drain, an inductance current iL and a current signal cs are shown in a normal working state.

[0032] Figure 3 A structure schematic diagram of an active power factor correction APFC circuit based on inductance average current compensation in an embodiment of the application is shown.

[0033] Figure 4 An implementation circuit diagram of the inductance average current compensation circuit in an embodiment of the application is shown, which includes a conduction time adjusting circuit and a negative current detecting and compensating circuit.

[0034] Figure 5 A working waveform schematic diagram of the conduction time adjusting circuit in an embodiment of the application is shown.

[0035] Figure 6 A working waveform diagram of the inductance average current compensation circuit in an embodiment of the application is shown.

[0036] ELEMENT NUMBER EXPLANATION

[0037] 101 APFC integrated controller

[0038] 102 input capacitor

[0039] 103 inductance

[0040] 104 diode

[0041] 105 output capacitor

[0042] 106 power MOS tube

[0043] 107 current sampling resistance

[0044] 31 controller

[0045] 32 rectifier bridge

[0046] 33 filter capacitor

[0047] 34 power inductor

[0048] 35 rectifier diode

[0049] 36 power MOSFET

[0050] 37 output capacitor

[0051] 38 current sense resistor

[0052] 3101 turn-on time adjustment circuit

[0053] 3102 switch logic circuit

[0054] 3103 gate drive circuit

[0055] 3104 zero current detection circuit

[0056] 3105 leading edge blanking circuit

[0057] 3106 negative current sense and compensation circuit DETAILED DESCRIPTION

[0058] Embodiments of the present application will be described hereinafter with reference to the drawings, in which specific embodiments of the application are shown. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art.

[0059] It should be understood that the structures, proportions, elements, materials and / or appearances of the devices which are depicted herein are by way of example only and should not be construed as limiting the scope of the application. Specific structural and functional details disclosed herein are not to be interpreted as limiting but merely as a basis for the claims and as a representative basis for teaching one skilled in the art to variously employ the application. The terms "coupled" and "connected," as used on this document, are used to

[0060] In the present application, unless specifically defined and limited otherwise, the terms "mounting", "connected", "connection", "fixed", "holding" and the like should be interpreted broadly, for example, can be fixed connection, can also be detachable connection, or integrally connected; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium, can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0061] Furthermore, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", when used herein, specify the presence of stated features, operations, elements, components, items, and / or groups thereof, but do not preclude the presence or addition of one or more other features, operations, elements, components, items, and / or groups thereof. As used herein, the terms "or" and "and / or" are to be interpreted as inclusive, i.e., as meaning one or any combination of items. Thus, "A, B or C" or "A, B and / or C" means any of the following: A; B; C; A and B; A and C; B and C; A, B and C. An exception to this definition will occur only when two or more sequentially connected terms are in some way inherently mutually exclusive.

[0062] To solve the problems in the background art, the present application provides an inductance average current compensation circuit, which is used to solve the problem that the THD is deteriorated due to the decrease of the average current caused by the negative current when the inductance resonates in the CrM mode APFC circuit. Considering that the inductance average current has decreased to zero before the Vin decreases to zero due to the negative inductance current, which has an adverse effect on the THD, in order to overcome the above adverse effect, the on-time Ton needs to be compensated to appropriately increase the Ton when the Vin decreases, so that the increased inductance current can offset the negative current, thereby improving the linearity of the inductance current and the Vin and reducing the cross distortion. Therefore, the present application uses a sampling circuit to sample the maximum negative current of the inductance during the resonance, and uses it to control the increase of the on-time to compensate for the negative current during the on-time, so as to solve the problem that the inductance average current decreases and the linearity with the input voltage deteriorates due to the influence of the negative resonant current when the input voltage changes, and can effectively improve the THD performance of the CrM APFC circuit.

[0063] In order to make the objectives, technical solutions and advantages of the present application clearer, the technical solutions in the embodiments of the present application are further described in detail below with reference to the following embodiments and in conjunction with the drawings. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0064] As Figure 3As shown, a structure schematic diagram of an active power factor correction (APFC) circuit based on inductance average current compensation is shown.

[0065] It can be understood that APFC is the abbreviation of Active Power Factor Correction, which means active power factor correction. The APFC technology has the advantages of improving the power electronic device network side power factor, reducing line loss, saving energy, reducing power grid harmonic pollution, and improving power supply quality.

[0066] In this embodiment, the APFC circuit includes a controller 31, a rectifier bridge 32, a filter capacitor 33, a power inductor 34, a rectifier diode 35, a power MOS tube 36, an output capacitor 37, and a current sampling resistor 38.

[0067] Among them, the two AC input ends of the rectifier bridge 32 are connected to the AC input ACin, the positive output end is connected to the first end of the filter capacitor 33, and the negative output end is connected to the second end of the filter capacitor and grounded. The first end of the power inductor 34 is connected to the first end of the filter capacitor 33, the second end of the power inductor 34 is connected to the anode of the rectifier diode 35 and the drain of the power MOS tube 36, the cathode of the rectifier diode 35 is connected to the first end of the output capacitor 37 as the output end vbus, and the second end of the output capacitor 37 is grounded. The gate of the power MOS tube 36 is connected to the gate drive end gate of the controller 31, the source is connected to the first end of the sampling resistor 38 and the current sampling end cs of the controller, and the second end of the sampling resistor 38 is connected to the second end of the output capacitor 37 and grounded.

[0068] In this embodiment, the inductance average compensation circuit is part of the controller 31, and the inductance average compensation circuit includes a conduction time adjustment circuit 3101, a switch logic circuit 3102, a gate drive circuit 3103, a zero current detection circuit 3104, a front porch blanking circuit 3105, and a negative current sampling and compensation circuit 3106. The structure of each circuit module in the inductance average compensation circuit is described in detail as follows:

[0069] The conduction time adjustment circuit 3101 includes three input ends and an output end, which are a first input end vctrl, a second input end on, a third input end en_ton, and an output end tout. The first input end vctrl is connected to the control voltage signal vctrl, the second input end is connected to the switch signal on, the third input end is connected to the conduction time timing enable signal en_ton, and the output end is connected to the conduction time end signal tout.

[0070] The switch logic circuit 3102 includes two input terminals and three output terminals, which are a first input terminal i1, a second input terminal i2, a first output terminal o1, a second output terminal o2 and a third output terminal o3. The first input terminal is connected with the turn-on time end signal tout, and the second input terminal is connected with the zero current signal zcs. The first output terminal o1 is connected with the switch signal on, the second output terminal o2 is connected with the negative current sampling control signal smp cs, and the third output terminal o3 is connected with the inductance discharge signal tdis.

[0071] The gate drive circuit 3103 includes one input terminal and one output terminal, which are an input terminal i1 and an output terminal o1. The input terminal i1 is connected with the switch signal on, and the output terminal o1 is connected with the gate drive signal gate.

[0072] The zero current detection circuit 3104 includes two input terminals and one output terminal, which are a first input terminal i1, a second input terminal i2 and an output terminal o1. The first input terminal i1 is connected with the switch signal on, the second input terminal i2 is connected with the gate drive signal gate, and the output terminal o1 is connected with the zero current signal zcs.

[0073] The leading edge blanking circuit 3105 includes an input terminal i1 and an output terminal o1. The input terminal i1 is connected with the switch signal on, and the output terminal o1 outputs the leading edge blanking signal leb.

[0074] The negative current sampling and compensation circuit 3106 includes six input terminals and one output terminal, which are a first input terminal cs, a second input terminal smp cs, a third input terminal tdis, a fourth input terminal on, a fifth input terminal vctrl, a sixth input terminal leb and an output terminal en_ton. The first input terminal is connected with the current signal cs, the second input terminal is connected with the negative current sampling control signal smp cs, the third input terminal is connected with the inductance discharge signal tdis, the fourth input terminal is connected with the switch signal on, the fifth input terminal is connected with the control voltage signal vctrl, the sixth input terminal is connected with the leading edge blanking signal leb, and the output terminal is connected with the turn-on time timing enable signal en_ton.

[0075] It is worth mentioning that the functions of each part of the inductance average current compensation circuit are described as follows:

[0076] The turn-on time adjustment circuit 3101 generates a timing signal related to the size of the control voltage signal vctrl to control the size of the turn-on time. According to the control voltage signal vctrl, the switch signal on and the turn-on time timing enable signal en_ton, the turn-on time end signal tout is generated.

[0077] The switch logic circuit 3102 generates a switch signal on, a negative current sampling control signal smp cs and an inductor discharge signal tdis according to the zero current signal zcs and the turn-on time end signal tout to control the negative voltage of the sampling and holding current signal cs.

[0078] The gate drive circuit 3103 generates a gate drive signal gate according to the switch signal on to drive the gate of the power MOS tube 36.

[0079] The zero current detection circuit 3104 detects the zero crossing state of the inductor current through the gate drive signal gate and generates the zero current signal zcs.

[0080] The negative current detection and compensation circuit 3106 samples and holds the minimum negative voltage of the current signal cs under the control of the negative current sampling control signal smp cs and the inductor discharge signal tdis, and generates a turn-on time timing enable signal cs en according to the sampled minimum negative voltage of cs, the voltage of cs after turn-on and the control voltage signal vctrl to control the turn-on time compensation for compensating the negative inductor current.

[0081] Hereinafter, the structure and principle of each component circuit of the inductor average current compensation circuit in the controller will be explained and described in detail in combination with specific drawings.

[0082] As shown in the figure, the inductor average current compensation circuit in an embodiment of the present application includes a turn-on time adjustment circuit and a negative current detection and compensation circuit. Figure 4

[0083] The turn-on time adjustment circuit 3101 includes a logic gate I101, a logic gate I102, an NMOSFET M101, an NMOSFET M102, a current source I103, a capacitor C101 and a comparator I104. The input end of the logic gate I101 is connected to the switch signal on, and the output end is connected to the gate of the NMOSFET M101. The input end of the logic gate I102 is connected to the turn-on time timing enable signal en ton, and the output end is connected to the gate of the M102. The drain of the NMOSFET M101 is connected to a reference voltage vramp and to the non-inverting input end of the comparator I104, and the source is connected to the ground. The drain of the NMOSFET M102 is connected to the reference voltage vramp, and the source is connected to the ground. The first end of the capacitor C101 is connected to the reference voltage vramp, and the second end is connected to the ground. The first end of the current source I103 is connected to a power supply voltage vdd, and the second end is connected to the reference voltage vramp. The non-inverting input end of the comparator I104 is connected to the control voltage signal vctrl, the inverting input end is connected to the reference voltage vramp, and the output end outputs the turn-on time end signal tout.​

[0084] The working principle of the on-time adjustment circuit 3101 includes: when either the switch signal on or the on-time timing enable signal en_ton is at a logic low level, the reference voltage vramp is set to zero voltage by the NMOSFET M101 or the NMOSFET M102; and when both the switch signal on and the on-time timing enable signal en_ton are flipped from a logic low level to a logic high level, the constant current source I103 charges the capacitor C101 to increase the reference voltage vramp over time, and when the reference voltage vramp reaches the control voltage vctrl, the comparator I104 flips the output timing end signal tout to control the switch logic circuit 3102 to form the switch signal on.

[0085] As shown in Figure 5 , the working waveforms of the on-time adjustment circuit in an embodiment of the application are shown. In combination with Figure 4 , the working process of the on-time adjustment circuit is described. The on is the on terminal signal, the vctrl is the vctrl terminal signal, the vramp is the node vramp signal, and the en_ton is the en_ton terminal signal.

[0086] At t0, the on signal is flipped from a low level to a high level, at which time the M102 sets the vramp to zero voltage because the en_ton is at a low level; after Δt1, at t1, the en_ton is flipped from a low level to a high level, and the capacitor C101 is charged under the current source I103, and the vramp voltage begins to rise; at t2, the vramp rises to vctrl, the comparator I104 flips to set the on signal to a low level, and after the on signal becomes low, the en_ton is flipped to a low level, and the vramp is discharged to zero voltage.

[0087] In normal stable operation, the high level duration of the switch signal on is composed of the delay time Δt of the on signal to the en_ton and the fixed time Ton, where Δt is variable and controlled by the en_ton, and Ton is controlled by the vctrl and remains unchanged. Figure 5 In the waveform diagram shown, two different on-times are shown, Ton1 between t0 and t2 and Ton2 between t3 and t5, and the difference lies in that Δt1 and Δt2 are different.

[0088] The negative current sampling and compensation circuit 3106 comprises: an amplifier I601, comparators I602 and I605, resistors R601 and R602, NMOSFET M601, M602, M603, M604 and M605, capacitors C601 and C602, a current source I603, logic gates I604 and I606; wherein the non-inverting input terminal of the amplifier I601 is connected to ground, the inverting input terminal is connected to the second end of R601, and the output terminal is connected to the gate of M603; the first end of R601 is connected to the current signal cs, and the second end is connected to the first end of R602; the second end of R602 outputs the signal min_cs which is connected to the source of M604 and the inverting input terminal of comparator I602; the drain of M601 is connected to the common end of R601 and R602, the gate is connected to the negative current sampling control signal smp_cs, and the source is connected to ground; the drain of M602 is connected to the first end of C601 and the gate of M604 and to the source of M603; the second end of C601 is connected to ground; the drains of M603 and M604 are connected to the power supply voltage vdd; the non-inverting input terminal of comparator I602 is connected to the current signal cs, the enable terminal of I602 is connected to the leading edge blanking signal leb, and the output terminal is connected to the first input terminal of I606 to output the signal cs_en; the input terminal of logic gate I604 is connected to the switch signal on, and the output terminal is connected to the gate of M605; the drain of M605, the first end of C602 and the second end of I603 are connected together and connected to the non-inverting input terminal of comparator I605; the first end of current source I603 is connected to the power supply voltage vdd; the second end of C602 is connected to ground; the inverting input terminal of comparator I605 is connected to the control voltage signal vctrl, and the output terminal is connected to the second input terminal of logic gate I606 to output the signal max_ton; and the output terminal of logic gate I606 is connected to the on-time timing enable signal en_ton.

[0089] The working principle of the negative current sampling and compensation circuit 3106 comprises: the amplifier I601, MOSFET M603, M604, resistors R601, R602 and capacitor C601 form a negative voltage to positive voltage conversion and sampling holding circuit. During the inductive resonance period from the moment when the inductive current drops to zero to the opening of the power MOS tube, the sampling circuit samples the negative voltage of the current signal cs under the control of the sampling signal, converts the negative voltage of the current signal cs into a positive voltage through the negative voltage to positive voltage conversion circuit, and holds the maximum value of the converted positive voltage (corresponding to the minimum value of the negative voltage of cs) on the capacitor C601 as the minimum current reference signal min_cs to control the compensation time; in addition, after the switch signal on controls the gate drive signal gate to change from low to high voltage to open the power MOS tube, after the leading edge blanking time leb, a comparator is used to compare the current signal cs and the sampled minimum current reference signal min_cs, and when the current signal cs reaches min_cs, the comparator flips, and the on-time timing enable signal en_ton follows to enable the on-time timing, and the compensation of the negative inductive current is realized through the increased on-time.

[0090] Specifically, the amplifier I601, resistors R601, R602, MOSFETs M601-M604 and capacitor C601 in the negative current sampling and compensation circuit constitute a voltage conversion and peak sampling and holding circuit. When the signal tdis is a logic high level, MOSFET 602 is turned on to discharge C601 to zero, and smp_cs is a low level, which is a sampling mode. In the sampling mode, I601, M603, M604, R601 and R602 form a negative feedback circuit, and the cs voltage is a negative voltage. Under the action of the amplifier, M603 and M604 drive min_cs to generate a positive voltage to maintain the negative phase voltage of I601 equal to the zero voltage of the positive phase. The voltage of min_cs is denoted as Vmin_cs, and the voltage of cs is denoted as V_cs. Then, the size of Vmin_cs is:

[0091]

[0092] If V_cs increases in the negative voltage direction, Vmin_cs will increase accordingly. When the negative voltage of V_cs decreases, Vmin_cs cannot decrease accordingly because C601 has no discharge path. In this way, the maximum value of V_cs is saved on C601. After the sampling mode ends, when smp_cs is flipped from low to high, it enters the holding mode. In the holding mode, M601 connects the common end of R601 and R601 to the ground, and Vmin_cs maintains the maximum value sampled and is sent to the negative phase input terminal of the comparator I602 for comparison with the voltage of cs. To prevent the occurrence of a spike voltage at the cs end during conduction from causing a false action, the comparator I602 increases an enable end and is connected to the leading edge blanking signal leb. During the duration of leb, the comparator I602 is disabled. After the leb time ends, when the voltage of cs reaches Vmin_cs, I602 flips, and the cs_en signal flips from low to high. After passing through the logic gate I606, the en_ton signal flips from low to high to enable the conduction time timing.

[0093] Specifically, to prevent the situation that the conduction time of the switch is too long due to the slow rise of the voltage of cs signal not reaching Vmin_cs during compensation, a maximum conduction time limit is set in the negative current sampling and compensation circuit. The circuit composed of the logic gate I604, current source I603, NMOSFET M605, capacitor C602 and comparator I605 is as follows. When the on signal flips to high, M605 is closed, I603 charges C602 to make the voltage at the positive phase terminal of I605 rise. When the voltage at the positive phase terminal of I605 reaches vctrl, the output signal max_ton of comparator I605 changes from low to high, and en_ton is controlled to be high to enable the conduction time timing.

[0094] As Figure 6 shown, the working waveform diagram of the inductance average current compensation circuit in an embodiment of the application is shown. The working process of the inductance average current compensation circuit is described as follows in combination with Figure 4 and Figure 3 . Figure 6 The drain in the middle is Figure 3 the MOS drain signal, iL is Figure 3 the inductance current iL in the circuit, on is the switch signal on, cs is the cs end signal, leb is the leb signal, zcs is the zcs signal, tdis is the tdis signal, smp_cs is the smp_cs signal, en_ton is the en_ton signal, cs_en is the cs_en node signal in the 3106 circuit, and max_ton is the max_ton node signal in the 3106 circuit.

[0095] At t0, the on signal is flipped from high to low, the external MOS switch is closed, the drain voltage rises to the output voltage, then the inductor current iL starts to decrease from the maximum value iLpk, tdis is flipped from low to high. At t1, iL decreases to zero, the inductor and the parasitic capacitance of node drain start to resonate, tdis is flipped from high to low. During t0-t1, tdis high discharges the sampling hold capacitor C601 in the negative current sampling and compensation circuit, and resets it, preparing for the sampling mode. At t1, smp_cs is flipped from low to high when the resonance starts, the negative current sampling and compensation circuit enters the sampling state. Due to the resonance, iL decreases to zero and then continues to decrease in the opposite direction, becoming negative, and the drain voltage decreases. At t2, iL reaches the maximum negative value -iLnpk, and then starts to increase. Before t2, the drain voltage decreases to zero, and due to the negative current flowing through the sampling resistor, the current signal cs voltage follows iL and reaches the maximum -ncspk at t2, which is converted to a positive voltage min_cs by the sampling and holding circuit. After t2, the direction of iL changes and starts to increase. The zero current detection circuit detects this state and outputs the zcs signal at t3, the switch logic circuit sets the on signal to high to open the power MOS, and at the same time, the smp_cs signal is set to low to end the sampling mode and enter the hold mode. After the on signal becomes high, the leading blanking circuit outputs the leb signal to prevent the comparator I602 in the negative current sampling and compensation circuit from malfunctioning. After leb, at t4, the cs signal voltage rises to min_cs, the comparator I602 flips, making cs_en flip from low to high, and after the logic circuit I606, en_ton follows and flips to high. At t3, the negative current sampling and compensation circuit starts timing, and at t5, it reaches the maximum on time limit max_ton and outputs high. Normally, the max_ton time is long, and max_ton appears after cs_en. In some conditions, such as when the input voltage is very low, the cs rises too slowly and does not reach min_cs in time, so max_ton may appear first to limit the on time. At t6, the on time adjustment circuit timing ends, the switch logic circuit sets the on signal to low, and the process repeats from t0.

[0096] Reference Figure 3 As shown in the figure, if the voltage after rectification to the inductor of the boost circuit is vin, the inductance value is L, the fixed on time of the on time adjustment circuit is Ton, and the maximum negative current of the inductor during resonance is -iLnpk, then under the action of the compensation circuit, the period average value of the inductor current is:

[0097]

[0098] After compensation, iLpk is composed of two parts, the first part is determined by the sample and hold compensation voltage min_cs, and the size is The second part is the increase of inductance current ΔiL+ in the on time Ton since the cs signal reaches the min_cs signal, and the voltage added to the inductance during the switch opening is vin, and the inductance current increases linearly in Ton time After adding the two parts, iLpk can be written as:

[0099]

[0100] Put formula (3) into formula (2) to obtain:

[0101]

[0102] The compensation amount can be set by adjusting the ratio of R602 and R601, if R602 and R601 are set to be equal in size, then:

[0103]

[0104] As can be known from the above embodiments, the compensation method and circuit of the present application can well compensate the influence of negative inductance current on average current during resonance, so that the average inductance current after compensation and the input voltage present an ideal linear proportional relationship, thereby realizing better THD performance.

[0105] In summary, the active power factor correction circuit based on inductance average current compensation, corrector and electric appliance provided by the present application solve the problem of poor linearity of average current and input voltage caused by negative inductance current during circuit resonance in CrM APFC circuit, by sampling the maximum negative current during resonance and controlling the compensation on time by detecting the current signal during conduction, complete compensation of the influence of negative current is realized, especially the compensation method and compensation circuit provided by the present application do not need additional ports, and the effect and practical value are particularly prominent in applications where it is inconvenient to detect the input voltage, therefore the present application effectively overcomes the shortcomings in the prior art and has high industrial utilization value.

[0106] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.

Claims

1. An active power factor correction circuit based on inductance average current compensation, characterized by, include: An integrated controller with an inductor averaging compensation circuit includes a control voltage port for receiving the control voltage signal vctrl, a gate drive output port for outputting the gate drive signal gate, and a sampling current port for input current signal cs. The power inductor has a DC input voltage connected to its first terminal and a second terminal coupled to the output terminal. The power MOSFET has its drain connected to the second terminal of the power inductor, its gate connected to the gate drive output port of the integrated controller, its source connected to the first terminal of the sampling resistor and connected to the sampling current port of the integrated controller, and the second terminal of the sampling resistor grounded. The inductance averaging compensation circuit includes: an on-time adjustment circuit, a switching logic circuit, a gate drive circuit, a zero-current detection circuit, a leading-edge blanking circuit, and a negative current sampling and compensation circuit; wherein: The first input terminal of the conduction time adjustment circuit is connected to the control voltage signal vctrl, the second input terminal is connected to the first output terminal of the switching logic circuit to receive the switch signal on, the third input terminal is connected to the output terminal of the negative current sampling and compensation circuit to receive the conduction time timing enable signal en_ton, and the output terminal is connected to the first input terminal of the switching logic circuit to output the conduction time end signal tout. The first input terminal of the switching logic circuit is connected to the conduction time end signal tout, the second input terminal is connected to the output terminal of the zero current detection circuit to receive the zero current signal zcs, the first output terminal outputs the switch signal on, the second output terminal is connected to the second input terminal of the negative current sampling and compensation circuit to output the negative current sampling control signal smp_cs, and the third output terminal is connected to the third input terminal of the negative current sampling and compensation circuit to output the inductor discharge signal tdis. The input terminal of the gate drive circuit is connected to the switch signal on, and the output terminal is connected to the gate drive signal gate. The first input terminal of the zero current detection circuit is connected to the switch signal on, the second input terminal is connected to the gate drive signal gate, and the output terminal is connected to the second input terminal of the switch logic circuit to output the zero current signal zcs. The input terminal of the leading edge blanking circuit is connected to the switch signal on, and the output terminal is connected to the sixth input terminal of the negative current sampling and compensation circuit to output the leading edge blanking signal leb. The negative current sampling and compensation circuit has a first input terminal connected to the current signal cs, a second input terminal connected to the negative current sampling control signal smp_cs, a third input terminal connected to the inductor discharge signal tdis, a fourth input terminal connected to the switch signal on, a fifth input terminal connected to the control voltage signal vctrl, a sixth input terminal connected to the leading edge blanking signal leb, and an output terminal connected to the conduction time timing enable signal en_ton.

2. The active power factor correction circuit based on inductor average current compensation according to claim 1, characterized in that: The conduction time adjustment circuit generates a conduction time end signal tout based on the input control voltage signal vctrl, switch signal on, and conduction time timing enable signal en_ton. The switch logic circuit generates a switch signal on, a negative current sampling control signal smp cs and an inductor discharge signal tdis to control the negative voltage of the sampling and holding current signal cs according to the zero current signal zcs and the turn-on time end signal tout; The gate drive circuit generates a gate drive signal gate to drive the gate of the power MOS tube according to the switch signal on connected thereto; The zero current detection circuit detects the zero crossing state of the inductor current through the gate drive signal gate and generates the zero current signal zcs; The negative current sampling and compensation circuit samples and holds the minimum negative voltage of the cs signal and generates a reference voltage signal min cs under the control of the negative current sampling control signal smp cs and the inductor discharge signal tdis according to the current signal cs connected thereto; after the switch signal on is turned on and the leading edge blanking signal leb is delayed, the min cs and the current signal cs are compared through a voltage comparator to generate an enable signal cs_en to control the turn-on time adjustment circuit to form a turn-on time compensation; to prevent the turn-on time from being too long, a maximum turn-on time control signal max_ton related to the control voltage signal vctrl is generated through the switch signal on to limit the turn-on time, and the max_ton and the cs_en are logically operated to generate a turn-on time timing enable signal en_ton.

3. The active power factor correction circuit based on inductance average current compensation according to claim 1, characterized in that, The turn-on time adjustment circuit comprises: a logic gate I101, the input end of which is connected to the switch signal on, and the output end of which is connected to the gate of an NMOSFET M101; a logic gate I102, the input end of which is connected to the turn-on time timing enable signal en_ton, and the output end of which is connected to the gate of an NMOSFET M102; the NMOSFET M101, the drain of which is connected to the positive input end of a logic gate I104, and the source of which is connected to the ground; the NMOSFET M102, the drain of which is connected to the drain of the NMOSFET M101, and the source of which is connected to the ground; a capacitor C101, the first end of which is connected to the drains of the NMOSFET M101 and the NMOSFET M102, and the second end of which is connected to the ground; a current source I103, the first end of which is connected to a power supply voltage vdd, and the second end of which is connected to the first end of the capacitor C101; a comparator I104, the negative input end of which is connected to a control voltage signal vctrl, the positive input end of which is connected to the first end of the capacitor C101, and the output end of which outputs a turn-on time end signal tout; When the switch signal on and the turn-on time timing enable signal en_ton are flipped from low level to high level, the NMOSFET M101 and the NMOSFET M102 are turned off, and the constant current source I103 charges the capacitor C101; when the voltage at the first end of the capacitor C101 reaches the control voltage signal vctrl, the comparator I104 flips to output the turn-on time end signal tout, thereby generating a timing signal related to the control voltage signal vctrl.

4. The active power factor correction circuit based on inductance average current compensation according to claim 1, characterized in that, The negative current sampling and compensation circuit comprises an amplifier I601, comparators I602 and I605, resistors R601 and R602, NMOSFET M601, M602, M603, M604 and M605, capacitors C601 and C602, a current source I603, logic gates I604 and I606; The positive input end of the amplifier I601 is grounded, the negative input end is connected to the second end of the resistor R601, and the output end is connected to the gate of the NMOSFET M603; the first end of the resistor R601 is connected to the current signal cs, and the second end is connected to the first end of the resistor R602; the second end of the resistor R602 is connected to the source of the NMOSFET M604 and the negative input end of the comparator I602; the drain of the NMOSFET M601 is connected to the common end of the resistors R601 and R602, the gate is connected to the negative current sampling control signal smp_cs, and the source is grounded; the drain of the NMOSFET M602 is connected to the first end of the capacitor C601 and the gate of the NMOSFET M604 and is connected to the source of the NMOSFET M603; the second end of the capacitor C601 is grounded; the drains of the NMOSFET M603 and M604 are connected to the power supply voltage vdd; the positive input end of the comparator I602 is connected to the current signal cs, the enable control end of I602 is connected to the leading edge blanking signal leb, and the output end is connected to the first input end of the logic gate I606 to output the signal cs_en; the input end of the logic gate I604 is connected to the switch signal on, and the output end is connected to the gate of the NMOSFET M605; the drain of the NMOSFET M605, the first end of the capacitor C602 and the second end of the current source I603 are connected together and connected to the positive input end of the comparator I605; the first end of the current source I603 is connected to the power supply voltage vdd; the second end of the capacitor C602 is grounded; the negative input end of the comparator I605 is connected to the control voltage signal vctrl, and the output end is connected to the second input end of the logic gate I606 to output the signal max_ton; and the output end of the logic gate I606 outputs the on-time timing enable signal en_ton.

5. The active power factor correction circuit based on inductance average current compensation according to claim 4, characterized in that, The amplifier I601, the resistors R601 and R602, the MOSFET M601-M604 and the capacitor C601 in the negative current sampling and compensation circuit constitute a voltage conversion and peak sampling and holding circuit; the peak sampling and holding circuit is divided into a sampling mode and a holding mode when working; when the signal tdis is a logic high level, the MOSFET 602 is turned on to discharge C601 to zero, and the smp_cs is in the sampling mode when it is at a low level; when the smp_cs is flipped from a low level to a high level, the holding mode is entered after the sampling mode ends.

6. The active power factor correction circuit based on inductance average current compensation according to claim 5, characterized in that, In the sampling mode, the amplifier I601, MOSFET M603-604, resistors R601-R602 form a negative feedback circuit, the cs voltage is a negative voltage, under the action of the amplifier I601, the MOSFET M603-604 drives min_cs to generate a positive voltage to maintain the negative phase terminal voltage of the amplifier I601 equal to the zero voltage of the positive phase terminal; the voltage of the output signal min_cs at the second end of the resistor R602 is recorded as Vmin_cs, and the cs voltage is recorded as V_cs, then the size of Vmin_cs is:

7. The active power factor correction circuit based on inductance average current compensation according to claim 5, characterized in that, In the holding mode, the MOSFET M601 connects the common end of the resistor R601 and the resistor R601 to the ground, Vmin_cs keeps the maximum value sampled and is sent to the negative phase input end of the comparator I602 to compare with the cs signal voltage.

8. The active power factor correction circuit based on inductance average current compensation according to claim 5, characterized in that, Under the action of the compensation circuit, the period average value of the inductor current is: then: By adjusting the proportion of the resistors R602 and R601, the compensation amount is set, and the size of R602 is set to be equal to R601, then: Wherein, -iLnpk is the maximum negative current of the inductor during resonance, iLpk is the inductor current at the end of Ton, L is the inductance value; Ton is the fixed conduction time of the time adjustment circuit; Vin is the voltage after rectification to the inductor of the boost circuit; ΔiL+ refers to the increase of the inductor current during the on time Ton from the time when the cs signal reaches the min cs signal; vin refers to the voltage applied across the inductor during the on time of the switch; the inductor current increases linearly during the Ton time 9. An active power factor corrector characterized by, The active power factor correction circuit based on inductance average current compensation comprises the active power factor correction circuit based on inductance average current compensation according to any one of claims 1-8.

10. An electrical consumer for accessing an alternating current mains supply, characterised in that, The active power factor corrector according to claim 9.

Images