A hybrid active clamp three-level inverter circuit and control method

Abstract

The disclosure provides a hybrid active clamp three-level inverter circuit and a control method, which comprises six switching tubes S1-S6, the switching tubes S1 and S4 are composed of a triode; the switching tubes S2, S3, S5 and S6 are composed of a field effect tube and a triode in parallel, the rated current of the field effect tube is less than the rated current of the triode, the respective advantages of the triode and the field effect tube are fully utilized, through the control mode of simultaneous driving and staggered driving, the switching loss and the on-state loss can be greatly reduced, and the circuit cost is reduced.

Description

Technical Field

[0001] This disclosure belongs to the field of inverter circuit technology, specifically relating to a hybrid active clamp three-level inverter circuit and its control method. Background Technology

[0002] The statements in this section are merely background information relating to this disclosure and do not necessarily constitute prior art.

[0003] As people's requirements for power quality continue to increase, high-power multilevel inverters are being used more and more widely in the industrial and new energy fields. In particular, the three-level inverter circuit with active neutral clamp structure can achieve a balanced distribution of losses of each power device, taking into account both system performance and complexity. It is an ideal choice for achieving high efficiency, high reliability and low harmonics.

[0004] However, the inventors discovered that although many studies have proposed using a combination of SiIGBT and SiC MOSFET devices in active clamp three-level inverter circuits, in practical applications, the high hard switching losses of Si IGBTs and the high cost of high-rated-current SiC MOSFETs limit the application of the circuits. Furthermore, existing circuits still have high switching and conduction losses. Summary of the Invention

[0005] To address the aforementioned problems, this disclosure proposes a hybrid active clamp three-level inverter circuit and control method. This disclosure uses a transistor with a larger rated current and a field-effect transistor with a smaller rated current connected in parallel to form a hybrid device. It fully utilizes the advantages of both transistors and field-effect transistors, reduces the switching losses and conduction losses of the circuit, and can significantly reduce the circuit cost.

[0006] According to some embodiments, the present disclosure adopts the following technical solutions:

[0007] A hybrid active clamping three-level inverter circuit includes six switching transistors S1 to S6. Each switching transistor is connected in anti-parallel with a diode. The first terminal of switching transistor S1 is connected to the positive terminal of the bus, the second terminal of switching transistor S4 is connected to the negative terminal of the bus, the second terminal of switching transistor S1 is connected to the first terminals of switching transistors S2 and S5, the first terminal of switching transistor S4 is connected to the second terminals of switching transistors S3 and S6, the second terminal of switching transistor S5 and the first terminal of switching transistor S6 are both connected to the midpoint of the bus, and the second terminal of switching transistor S2 and the first terminal of switching transistor S3 are connected together to form a bridge arm.

[0008] The switching transistors S1 and S4 are composed of a single transistor.

[0009] The switching transistors S2, S3, S5 and S6 are composed of a field-effect transistor and a transistor connected in parallel, and the rated current of the field-effect transistor is less than the rated current of the transistor.

[0010] As an alternative implementation, a first capacitor is connected between the positive terminal of the busbar and the midpoint of the busbar, and a second capacitor is connected between the negative terminal of the busbar and the midpoint of the busbar.

[0011] Preferably, the transistor is an IGBT and the field-effect transistor is a MOSFET.

[0012] Furthermore, in the switching transistors S2, S3, S5, and S6, the drain of the MOSFET is connected to the collector of the IGBT, the source of the MOSFET is connected to the emitter of the IGBT, and the gate of the MOSFET is not connected to the gate of the IGBT.

[0013] The control method based on the above-mentioned hybrid active clamp three-level inverter circuit includes:

[0014] The commutation process between the P state and the O state in the positive half-cycle is as follows:

[0015] When the circuit is in state P, switches S1, S2, and S6 are turned on, and current flows out through switches S1 and S2, while no current flows through switch S6.

[0016] Subsequently, switch S2 turns off and enters the dead zone. The anti-parallel diode D3 of switch S3 naturally turns on, and the current freewheels through switch S6 and diode D3. At this time, the field-effect transistor and the transistor in switch S6 are simultaneously turned on.

[0017] When switch S3 is turned on at zero voltage, current flows through switch S6 and diode D3, and the circuit is in the OL state.

[0018] When switch S1 is turned off with zero current, the circuit is in a dead zone, and current still flows through switch S6 and diode D3.

[0019] With zero voltage, switching transistors S2 and S5 are turned on, and current flows through the two parallel loops of S5 and S2, and S6 and S3, and the circuit is in the 0UL state.

[0020] Furthermore, the driving methods of the switching transistors S2 and S3 include staggered driving and simultaneous driving; when the switching transistors S2 or S3 generate hard switching losses, the staggered driving method is used, otherwise the simultaneous driving method is used.

[0021] The switching transistors S5 and S6 are driven simultaneously.

[0022] Furthermore, the time-shifting drive is as follows: the transistor is turned on only after the field-effect transistor is fully turned on, achieving lossless turn-on; the transistor is turned off before the field-effect transistor, achieving lossless turn-off;

[0023] The simultaneous driving refers to the simultaneous conduction of the transistor and the field-effect transistor.

[0024] Furthermore, when the circuit is in the 0UL state, switches S5 and S2, S6 and S3 are all turned on, and the transistors and field-effect transistors in switches S2 and S6 are also turned on.

[0025] Furthermore, a carrier-in-direction PWM modulation method is used to drive the circuit. When the carrier wave is less than the signal wave, the circuit is determined to be in the P state; otherwise, it is in the O state.

[0026] Furthermore, if the signal wave is in the negative half-cycle, the image of the negative half-cycle is shifted to the positive half-cycle for judgment.

[0027] Compared with the prior art, the beneficial effects of this disclosure are as follows:

[0028] In the circuit and circulating process disclosed herein, hard switching losses are concentrated on S2 and S3. Since S2 and S3 use composite switching transistors, switching losses and conduction losses can be significantly reduced.

[0029] The commutation process disclosed herein includes two O states, where OL is the transition state and the primary O state is OUL. During OUL, all four intermediate transistors are turned on, and current flows through two parallel loops. Furthermore, the SiCMOSFET and SiIGBT in the composite switching transistors are simultaneously turned on, fully utilizing the low cost, low conduction loss, and high current capacity of the IGBT, and the low switching loss and synchronous rectification characteristics of the MOSFET. The method of turning on all four intermediate transistors also balances the switching transistor temperature, reducing the size of the heatsink.

[0030] In this disclosure, since Si IGBTs have no switching losses, the switching losses are mainly concentrated in SiC MOSFETs. Compared to directly selecting a high-rated-current SiC MOSFET, selecting a composite switch of a low-rated-current SiC MOSFET and a high-rated-current Si IGBT can reduce circuit costs while maintaining similar switching losses; in fact, the main circuit cost can be reduced to less than half.

[0031] To make the above-mentioned objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0032] The accompanying drawings, which form part of this disclosure, are used to provide a further understanding of this disclosure. The illustrative embodiments of this disclosure and their descriptions are used to explain this disclosure and do not constitute an undue limitation of this disclosure.

[0033] Figure 1 This is a schematic diagram of the circuit structure disclosed herein;

[0034] Figure 2(a) is a schematic diagram of the time-shifting driving method disclosed in this invention;

[0035] Figure 2(b) is a schematic diagram of the simultaneous driving method of this disclosure;

[0036] Figure 3 (a)-(c) are schematic diagrams of the commutation process in the positive half-cycle P state of this disclosure;

[0037] Figure 4 This is a schematic diagram of the dead zone state during the transition from the P state to the OL state in the positive half-cycle of this disclosure;

[0038] Figure 5 This is a schematic diagram of the positive half-cycle OL state of this publication;

[0039] Figure 6 This is a schematic diagram of the dead zone state during the transition from the OL state to the OUL state in the positive half-cycle of this disclosure;

[0040] Figure 7 This is a schematic diagram of the OFL state during the positive half-cycle of this publication;

[0041] Figure 8 (a)-(c) are schematic diagrams of the commutation process in the N state of the negative half-cycle of this disclosure;

[0042] Figure 9 This is a schematic diagram of the dead zone state during the transition from the N state to the OL state in the negative half-cycle of this disclosure;

[0043] Figure 10 This is a schematic diagram of the OL state during the negative half-cycle of this publication;

[0044] Figure 11 This is a schematic diagram of the dead zone state during the transition from the OL state to the OUL state in the negative half-cycle of this disclosure;

[0045] Figure 12 This is a schematic diagram of the negative half-cycle OFL state of this publication;

[0046] Figure 13 This is the publicly available driver flowchart;

[0047] Figure 14 This is a schematic diagram of the drive signals disclosed herein;

[0048] Figures 15(a)-(b) are schematic diagrams of the P-state and N-state switching signals of this disclosure. Detailed implementation method:

[0049] The present disclosure will be further described below with reference to the accompanying drawings and embodiments.

[0050] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this disclosure. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains.

[0051] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this disclosure. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms “comprising” and / or “including” are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0052] In this disclosure, terms such as "upper," "lower," "left," "right," "front," "back," "vertical," "horizontal," "side," and "bottom" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are merely relational terms determined for the convenience of describing the structural relationship of the various components or elements in this disclosure, and do not specifically refer to any component or element in this disclosure, nor should they be construed as limiting this disclosure.

[0053] In this disclosure, terms such as "fixed connection," "connected," and "linked" should be interpreted broadly, indicating a fixed connection, an integral connection, or a detachable connection; a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can determine the specific meaning of these terms in this disclosure based on the specific circumstances, and they should not be construed as limitations on this disclosure.

[0054] A hybrid active clamp three-level inverter circuit, such as Figure 1 As shown, it includes six switching transistors S1 to S6, wherein each switching transistor is connected in anti-parallel with a diode (D1 to D6). The first end of switching transistor S1 is connected to the positive terminal of the bus, the second end of switching transistor S4 is connected to the negative terminal of the bus, the second end of switching transistor S1 is connected to the first end of switching transistors S2 and S5, the first end of switching transistor S4 is connected to the second end of switching transistors S3 and S6, the second end of switching transistor S5 and the first end of switching transistor S6 are both connected to the midpoint of the bus, and the second end of switching transistor S2 and the first end of switching transistor S3 are connected together to form a bridge arm end;

[0055] A first capacitor is connected between the positive terminal of the busbar and the midpoint of the busbar, and a second capacitor is connected between the negative terminal of the busbar and the midpoint of the busbar.

[0056] The switching transistors S1 and S4 are composed of a single transistor (G1, G4);

[0057] The switching transistors S2, S3, S5 and S6 are composed of a field-effect transistor (M2, M3, M5, M6) and a transistor (G2, G3, G5, G6) connected in parallel, wherein the rated current of the field-effect transistor is less than the rated current of the transistor.

[0058] Preferably, the transistor is an IGBT and the field-effect transistor is a MOSFET, more preferably a SiC MOSFET.

[0059] The drain of the SiC MOSFET is connected to the collector of the IGBT, the source of the SiC MOSFET is connected to the emitter of the IGBT, and the gate of the SiC MOSFET is not connected to the gate of the IGBT.

[0060] Because Si IGBTs have high hard switching losses, while SiC MOSFETs have low switching losses, directly using SiC MOSFETs with high rated current is costly. In order to make full use of the advantages of the two devices, this disclosure replaces the traditional scheme of using a single IGBT or SiC MOSFET in the four internal transistors S2, S3, S5, and S6 in the existing active clamp three-level inverter circuit with a combination of a SiC MOSFET with a low rated current and a Si IGBT with a high rated current connected in parallel. Different signals are used to control staggered driving or simultaneous driving according to the state of different switching transistors during the commutation process.

[0061] Specifically, as shown in Figure 2(a), the time-delayed drive utilizes the low switching loss characteristic of SiC MOSFETs. The IGBT is turned on only after the SiC MOSFET is fully turned on, resulting in zero voltage between the emitter and collector of the IGBT, achieving lossless turn-on. The IGBT turns off before the SiC MOSFET, again resulting in zero voltage between the emitter and collector, allowing for lossless turn-off. In this case, the IGBT only experiences conduction losses, with no switching losses. While MOSFETs generate higher conduction losses during the turn-on and turn-off delays, SiC MOSFETs effectively reduce these losses. After the IGBT is turned on, the conduction loss of the Si IGBT is lower than that of the SiC MOSFET, further reducing the switching losses.

[0062] Simultaneous drive refers to the simultaneous conduction of the IGBT and the SiC MOSFET. If the switching transistor is in a zero-voltage state, the switching loss of the IGBT is zero, and thus simultaneous drive is adopted, as shown in Figure 2(b). The advantages of simultaneous drive are that the control method is simple, easy to implement, low in implementation cost, and high in reliability.

[0063] Since the hard switching loss of this circuit is only generated in S2 or S3 when switching between P and OL states, the switching process of S2 from P to OL and the switching process of S3 from N to OL are driven in a staggered manner, while the other working states of S5, S6 and S2, S3 are driven simultaneously.

[0064] The commutation process of the circuit disclosed herein is as follows:

[0065] Due to the symmetry of the upper and lower arms of the ANPC, the commutation process of the P and O states in the positive half-cycle is similar to the switching process of the N and O states in the negative half-cycle. We will first take the direction of current flowing into the load as an example for explanation.

[0066] like Figure 3 As shown, in the P state, S1, S2, and S6 are turned on, and current flows through S1 and S2; no current flows through S6. Because S2 incurs hard switching losses, G2 and M2 must be driven at different times. Based on the switching sequence of SiC MOSFETs and IGBTs, the P state can be further divided into three processes: a, b, and c, corresponding to... Figure 3 (a)- Figure 3 (c) After the OUL state ends, the circuit begins to switch to the P state, and the circuit enters process a, such as... Figure 3 As shown in (a), M2 is turned on, and current flows only through M2. After the SiC MOSFET M2 is fully turned on, it enters process b, as follows. Figure 3 As shown in (b), G2 is turned on, and current flows through G2 and M2. The process is as follows: Figure 3 As shown in (c), G2 is off, and current flows only through M2. The circuit is preparing to switch to the OL state through the dead zone. During processes a, b, and c, G6 and M6 are always in the on state, but no current flows through them.

[0067] Subsequently, S2 is shut down, entering a dead zone, as... Figure 4 As shown, the anti-parallel diode D3 of S3 is naturally turned on, and the current freewheels through diodes G6, M6 and D3.

[0068] S3 conducts at zero voltage, current flows through M6, G6 and D3, and the circuit is in the OL state. Figure 5 As shown.

[0069] Subsequently, S1 turns off with zero current, and the circuit is in a dead zone, such as Figure 6 As shown, the current still flows through G6, M6 and D3 at this time.

[0070] like Figure 7 As shown, the circuit is in the 0UL state, with S2 and S5 conducting at zero voltage, and current flowing through the two parallel loops of S5 and S2, and S6 and S3.

[0071] It can be seen that during this commutation process, the hard switching losses are concentrated on S2 and S3. Since S2 and S3 use composite switching transistors of SiCMOSFET and Si IGBT, the switching losses and conduction losses can be significantly reduced.

[0072] The commutation process described above includes two O states, where OL is the transition state and OUL is the primary O state. Compared to commutation directly from the P state to OUL, the commutation method via the OL transition state only generates one hard switching loss.

[0073] During the OFL process, all four intermediate transistors are turned on. At this time, the current in the two circuits mainly flows through the Si IGBT. However, considering the synchronous rectification characteristics of the MOSFET, the SiC MOSFET and Si IGBT are turned on simultaneously, and the current can also flow through the SiC MOSFET. That is, in this process, the current not only flows through the two parallel circuits S5 and S2, and S6 and S3, but also through the two parallel devices G2 and M2 and G6 and M6 in S2 and S6. This fully utilizes the low cost, low conduction loss, and high current of the IGBT, and the low switching loss and synchronous rectification characteristics of the MOSFET. The method of turning on all four intermediate transistors also balances the temperature of the switching transistors, reducing the size of the heatsink.

[0074] Since Si IGBTs have no switching losses, the switching losses are mainly concentrated in SiC MOSFETs. Compared to directly selecting a high-rated-current SiC MOSFET, selecting a composite switching transistor of a low-rated-current SiC MOSFET and a high-rated-current Si IGBT can reduce circuit costs while maintaining similar switching losses; in fact, the main circuit cost can be reduced to less than half.

[0075] The switching process between the N state and the O state in the negative half-cycle is similar.

[0076] like Figure 8 As shown, the circuit is in state N, with S4, S3, and S5 conducting, and current flowing through S4 and S5; no current flows through S5. Because S3 incurs hard switching losses, G3 and M3 must be driven at different times. Based on the switching sequence of SiC MOSFETs and IGBTs, state N can be further divided into three processes: a, b, and c, corresponding to... Figure 8 (a)- Figure 8 (c) After the OUL state ends, the circuit begins to switch to the N state, and the circuit enters process a, such as... Figure 8 As shown in (a), M3 is turned on, and current flows only through M3. After the SiC MOSFET M3 is fully turned on, it enters process b, as follows. Figure 8 As shown in (b), G3 is turned on, and current flows through G3 and M3. The process is as follows: Figure 8As shown in (c), G3 is off, and current flows only through M3. The circuit is preparing to switch to the OL state through the dead zone. During processes a, b, and c, G5 and M5 are always in the on state, but no current flows through them.

[0077] Subsequently, S3 is shut down, entering a dead zone, as... Figure 9 As shown, the anti-parallel diode D2 of S2 is naturally turned on, and the current freewheels through diodes G5, M5 and D2.

[0078] S2 conducts at zero voltage, current flows through M5, G5 and D2, and the circuit is in the OL state. Figure 10 As shown.

[0079] Subsequently, S2 turns off with zero current, and the circuit is in a dead zone, such as Figure 11 As shown, the current still flows through G5, M5 and D2 at this time.

[0080] like Figure 12 As shown, the circuit is in the 0UL state, with S3 and S6 conducting at zero voltage, and current flowing through the two parallel loops of S6 and S3, and S5 and S2.

[0081] It can be seen that during this commutation process, the hard switching losses are concentrated on S2 and S3. Since S2 and S3 use composite switching transistors of SiCMOSFET and Si IGBT, the switching losses and conduction losses can be significantly reduced.

[0082] The commutation process described above includes two O states, where OL is the transition state and the primary O state is OUL. Compared to commutation directly from the N state to OUL, the commutation method via the OL transition state only generates one hard switching loss.

[0083] During the OFL process, all four intermediate transistors are turned on. At this time, the current in the two circuits mainly flows through the Si IGBT. However, considering the synchronous rectification characteristics of the MOSFET, the SiC MOSFET and Si IGBT are turned on simultaneously, and the current can also flow through the SiC MOSFET. That is, in this process, the current not only flows through the two parallel circuits S5 and S2, and S6 and S3, but also through the two parallel devices G3 and M3 and G5 and M5 in S3 and S5. This fully utilizes the low cost, low conduction loss, and high current of the IGBT, and the low switching loss and synchronous rectification characteristics of the MOSFET. The method of turning on all four intermediate transistors also balances the temperature of the switching transistors, reducing the size of the heatsink.

[0084] The operating states of a circuit in one cycle are: Pa—Pb—Pc—dead zone—OL—dead zone—OUL or Na—Nb—Nc—dead zone—OL—dead zone—OUL. The flowchart for determining the circuit's operating state is as follows: Figure 13 As shown.

[0085] Let the signal wave be Ur, where Ur is a sine wave with an amplitude of A. The carrier wave is Uc, and the modulation index is m. The carrier -同向PWM modulation method is adopted, and the carrier ratio should be set as a multiple of 3 to cancel more harmonic energy and obtain better harmonic output characteristics. First, determine whether Ur is in the positive half - cycle or the negative half - cycle. If it is in the positive half - cycle, compare the magnitudes of Uc and Ur. When Uc < Ur, the circuit is in the P state; otherwise, it is in the O state.

[0086] When it is determined that the circuit is in the P state, further determine which process in the P state the circuit is in. If the circuit has just completed commutation to the P state and G2 is not in the zero - voltage state, then the circuit enters the Pa state at this time; if G2 is in the zero - voltage state, the circuit enters the Pb state; if the circuit is preparing to commutate to the O state, it is in the Pc state.

[0087] When the circuit is in the O state, determine whether the circuit is in the commutation state. If so, it enters the OL state; otherwise, it enters the OUL state.

[0088] If the circuit has just completed commutation from the O state to the P state, and at this time the Si IGBT tube G2 is not in the zero - voltage state, a time - staggered driving method needs to be used to control the Si C MOSFET tube M2 and the Si IGBT tube G2 to conduct successively. The specific process is that in the Pa state, M2 conducts first. After M2 is fully turned on and the voltage drop across G2 becomes 0, it enters the Pb state, and then G2 conducts. When the circuit is preparing to commutate to the O state, it is in the Pc state. To ensure that G2 is turned off under zero voltage, a time - staggered driving method needs to be used to control G2 and M2 to turn off successively. Since there is no current passing through S6, during the entire P state, G6 and M6 are driven simultaneously. If the circuit is in the O state and is in the state of just finishing the P state and preparing to commutate to the O state, to prevent hard - switching losses in G1 and reverse - recovery losses in D3 and D5, an OL transition state needs to be introduced. At this time, G3 and M3, G6 and M6 conduct simultaneously. The reason for simultaneous driving is that G3 and G6 are already in the zero - voltage state, G1 is not turned off but there is no current flowing through it. Until G5 and G2 are in the zero - voltage state, the circuit enters the main O state OUL, where G2 and M2, G5 and M5 conduct simultaneously, and G1 is turned off. Since the carrier -同向PWM modulation method is adopted in this disclosure, if Ur is in the negative half - cycle, the image of the negative half - cycle needs to be translated to the positive half - cycle, that is, compare Uc with Ur + m*A, and the remaining judgment process is similar to that in the P state, so it will not be elaborated here.

[0089] After the circuit working state is judged, a dead - time is set for the circuit. The setting of the dead - time depends on the parameters of the selected switching tubes. In this embodiment, 5 times the switching time is selected. Finally, drive signals are sent to each switching tube to control the operation of the main circuit. The drive signal timing diagram is as Figure 14 shown, and the switch state table is shown in Figures 15(a) and (b).

[0090] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

[0091] While the specific embodiments of this disclosure have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of this disclosure. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solutions of this disclosure are still within the scope of protection of this disclosure.

Claims

1. A hybrid active clamping three-level inverter circuit, comprising six switching transistors S1~S6, each of which is connected in anti-parallel to a diode. The first terminal of switching transistor S1 is connected to the positive terminal of the bus, the second terminal of switching transistor S4 is connected to the negative terminal of the bus, the second terminal of switching transistor S1 is connected to the first terminals of switching transistors S2 and S5, the first terminal of switching transistor S4 is connected to the second terminals of switching transistors S3 and S6, the second terminal of switching transistor S5 and the first terminal of switching transistor S6 are both connected to the midpoint of the bus, and the second terminal of switching transistor S2 and the first terminal of switching transistor S3 are connected together to form a bridge arm. Its characteristic is: The switching transistors S1 and S4 are composed of a single IGBT. The switching transistors S2, S3, S5 and S6 are composed of a field-effect transistor and an IGBT connected in parallel, and the rated current of the field-effect transistor is less than the rated current of the IGBT.

2. The hybrid active clamp three-level inverter circuit as described in claim 1, characterized in that: A first capacitor is connected between the positive terminal of the busbar and the midpoint of the busbar; a second capacitor is connected between the negative terminal of the busbar and the midpoint of the busbar.

3. The hybrid active clamp three-level inverter circuit as described in claim 1, characterized in that: The field-effect transistor is a MOSFET.

4. The hybrid active clamp three-level inverter circuit as described in claim 3, characterized in that: In the switching transistors S2, S3, S5, and S6, the drain of the MOSFET is connected to the collector of the IGBT, the source of the MOSFET is connected to the emitter of the IGBT, and the gate of the MOSFET is not connected to the gate of the IGBT.

5. A control method for a hybrid active clamp three-level inverter circuit based on any one of claims 1-4, characterized in that: The commutation process between the P state and the O state in the positive half-cycle is as follows: When the circuit is in state P, switches S1, S2, and S6 are turned on, and current flows out through switches S1 and S2, while no current flows through switch S6. Subsequently, switch S2 turns off and enters the dead zone. The anti-parallel diode D3 of switch S3 naturally turns on, and the current freewheels through switch S6 and diode D3. At this time, the field-effect transistor in switch S6 and IGBT are turned on simultaneously. When switch S3 is turned on at zero voltage, current flows through switch S6 and diode D3, and the circuit is in the OL state. When switch S1 is turned off with zero current, the circuit is in a dead zone, and current still flows through switch S6 and diode D3. With zero voltage, switching transistors S2 and S5 are turned on, and current flows through the two parallel loops of S5 and S2, and S6 and S3, and the circuit is in the 0UL state.

6. The control method as described in claim 5, characterized in that: The driving methods of the switching transistors S2 and S3 include staggered driving and simultaneous driving; when the switching transistors S2 or S3 generate hard switching losses, the staggered driving method is used, otherwise the simultaneous driving method is used. The switching transistors S5 and S6 are driven simultaneously.

7. The control method as described in claim 6, characterized in that: The staggered driving method is as follows: the IGBT is turned on only after the field-effect transistor is fully turned on, achieving lossless turn-on; the IGBT is turned off before the field-effect transistor, achieving lossless turn-off. or, The simultaneous driving refers to the simultaneous conduction of the IGBT and the field-effect transistor.

8. The control method as described in claim 5, characterized in that: When the circuit is in the 0UL state, switches S5 and S2, S6 and S3 are all turned on, and the IGBTs and MOSFETs in switches S2 and S6 are also turned on.

9. The control method as described in claim 5, characterized in that: The circuit is driven by a carrier-in-phase PWM modulation method. When the carrier wave is less than the signal wave, the circuit is in the P state; otherwise, it is in the O state.

10. The control method as described in claim 6, characterized in that: If the signal wave is in the negative half-cycle, the image of the negative half-cycle is shifted to the positive half-cycle for judgment.

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