Display panel, manufacturing method thereof and display device

Abstract

A display panel, a manufacturing method thereof, and a display device. The display panel has a display area and a frame area located at the periphery of the display area, the frame area including a peripheral circuit area and a peripheral area, and the peripheral circuit area being arranged between the display area and the peripheral area. The display panel includes a substrate, a barrier structure, a peripheral circuit, an encapsulation substrate, and an encapsulation adhesive. At least part of the barrier structure is located in the peripheral circuit area on the substrate and includes an organic barrier layer and an inorganic barrier layer. The organic barrier layer includes an opening extending through the organic barrier layer, and the extending direction of the opening is substantially the same as the extending direction of the edge of the display panel close to the opening in the display panel. The inorganic barrier layer covers the organic barrier layer and fills the opening. The peripheral circuit is located on the substrate and in the peripheral circuit area. The encapsulation substrate is arranged on the side of the barrier structure away from the substrate. The encapsulation adhesive is filled between the substrate and the encapsulation substrate, covering the display area and the peripheral circuit area.

Description

[0001] This application is a divisional application of the PCT national phase application filed on October 21, 2019, entering the Chinese national phase on October 22, 2019, with national application number 201980002052.3, entitled "Display panel and method of manufacturing the same, display device". Technical Field

[0002] At least one embodiment of this disclosure relates to a display panel and a method for manufacturing the same, as well as a display device. Background Technology

[0003] The performance and lifespan of OLED devices are easily affected by moisture and oxygen, making it crucial to use effective sealing technologies to prevent moisture and oxygen from contacting the OLED devices. Meanwhile, narrow bezels are a trend in OLED display development; for example, this can typically be achieved by reducing the distance between the display area's encapsulation bezel and the light-emitting area (AA area). Summary of the Invention

[0004] At least one embodiment of this disclosure provides a display panel having a display area and a border area surrounding the display area. The border area includes a peripheral circuit area and a peripheral area, with the peripheral circuit area disposed between the display area and the peripheral area. The display panel includes a substrate, a barrier structure, peripheral circuitry, an encapsulation substrate, and encapsulating adhesive. At least a portion of the barrier structure is located in the peripheral circuit area on the substrate and includes an organic barrier layer and an inorganic barrier layer. The organic barrier layer includes an opening penetrating the organic barrier layer, the extension direction of which is substantially the same as the extension direction of the display panel edge near the opening. The inorganic barrier layer covers the organic barrier layer and fills the opening. The peripheral circuitry is located on the substrate and in the peripheral circuit area. The encapsulation substrate is disposed on the side of the barrier structure away from the substrate. The encapsulating adhesive fills the space between the substrate and the encapsulation substrate, covering the display area and the peripheral circuit area.

[0005] For example, a display panel provided in one embodiment of this disclosure further includes: a sealing adhesive located in the peripheral area and connected to the substrate and the encapsulation substrate respectively, wherein the encapsulation adhesive fills the area enclosed by the sealing adhesive, the substrate and the encapsulation substrate.

[0006] For example, in a display panel provided in one embodiment of this disclosure, the organic barrier layer is located on the side of the sealant near the display area, and the inorganic barrier layer includes a portion located between the organic barrier layer and the sealant.

[0007] For example, in a display panel provided in one embodiment of this disclosure, there is a gap between the inorganic barrier layer and the sealing adhesive.

[0008] For example, in a display panel provided in one embodiment of this disclosure, the direction from the display area to the frame area is a first direction, and the peripheral circuit includes a first signal line and a functional element; the first signal line extends along a second direction intersecting the first direction; the orthographic projection of the first signal line on the substrate is located within the orthographic projection of the organic barrier layer on the substrate, and the orthographic projection of the opening on the substrate does not overlap with the orthographic projection of the first signal line on the substrate.

[0009] For example, in a display panel provided in one embodiment of this disclosure, the peripheral circuit includes a plurality of first signal lines, wherein the plurality of first signal lines are disposed on the same layer, and there is a gap between two adjacent first signal lines, and the orthographic projection of the opening on the substrate is located within the orthographic projection of the gap between two adjacent first signal lines on the substrate.

[0010] For example, a display panel provided in one embodiment of this disclosure further includes a protective layer covering the first signal line and located between the first signal line and the organic barrier layer.

[0011] For example, in a display panel provided in one embodiment of this disclosure, the protective layer is located in the border area and is spaced apart from the display area, and the inorganic barrier layer covers the protective layer.

[0012] For example, in a display panel provided in one embodiment of this disclosure, the direction from the display area to the frame area is a first direction, and the peripheral circuit includes a second signal line extending from the display area along the first direction to the frame area; the second signal line includes a first part and a second part connected in series with each other, the first part being exposed by the opening, and the second part not being exposed by the opening; the first part includes at least two traces connected in parallel, and the second part is a single trace.

[0013] For example, in one embodiment of the present disclosure, the display panel further includes an encapsulation layer that covers the display area and the inorganic barrier layer.

[0014] For example, in a display panel provided in one embodiment of this disclosure, the opening includes a closed annular first opening surrounding the display area; the closed annular first opening divides the organic barrier layer into an inner portion close to the display area and an outer portion away from the display area, the inner portion being a closed annulus surrounding the display area, and the outer portion being a closed annulus surrounding the first opening.

[0015] For example, in a display panel provided in one embodiment of this disclosure, the organic barrier layer includes a plurality of openings located in the border area.

[0016] For example, in a display panel provided in one embodiment of this disclosure, the opening further includes a non-annular opening spaced apart from the first opening, the non-annular opening being located within at least one of the outer portion and the inner portion.

[0017] For example, in a display panel provided in one embodiment of this disclosure, the width of the opening in the direction from the border area to the display area is 1 μm to 5000 μm.

[0018] For example, a display panel provided in one embodiment of this disclosure further includes: a planarization layer, comprising a portion located in the display area and a portion located in the border area, wherein the planarization layer serves as the organic barrier layer.

[0019] For example, a display panel provided in one embodiment of this disclosure further includes: a light-emitting device located on the portion of the planarization layer located in the display area.

[0020] For example, in a display panel provided in one embodiment of this disclosure, the direction from the display area to the border area is a first direction, and the width of the border area in the first direction is ≥5mm.

[0021] At least one embodiment of this disclosure also provides a display device, including any of the display panels provided in the embodiments of this disclosure.

[0022] This disclosure provides at least one embodiment of a method for manufacturing a display panel, the display panel having a display area and a border area surrounding the display area. The method includes: providing a substrate; forming a barrier structure on the substrate, including: forming an organic barrier layer, wherein the organic barrier layer includes an opening penetrating the organic barrier layer, wherein the extending direction of the opening is substantially the same as the extending direction of the display panel edge near the opening in the display panel; and forming an inorganic barrier layer covering the organic barrier layer and filling the opening; the method for manufacturing the display panel further includes: forming peripheral circuitry on the substrate, wherein the border area includes a peripheral circuitry area, the peripheral circuitry being located in the peripheral circuitry area; providing an encapsulation substrate; forming an encapsulating adhesive covering the display area and the peripheral circuitry area; and mating the encapsulation substrate with the substrate such that the barrier structure is away from the substrate, and the encapsulating adhesive is filled between the substrate and the encapsulation substrate.

[0023] For example, a method for manufacturing a display panel provided in one embodiment of this disclosure further includes: forming a sealing adhesive on the substrate, wherein the sealing adhesive is located in the border area and surrounds at least a portion of the blocking structure, and the opening of the organic blocking layer is located between the sealing adhesive and the display area.

[0024] For example, in a method for manufacturing a display panel provided in an embodiment of this disclosure, the organic barrier layer is located on the side of the sealant near the display area, and the inorganic barrier layer includes a portion located between the organic barrier layer and the sealant.

[0025] For example, in a method for manufacturing a display panel provided in an embodiment of this disclosure, the opening includes a closed annular first opening surrounding the display area; the closed annular first opening divides the organic barrier layer into an inner portion close to the display area and an outer portion away from the display area, the inner portion being a closed annulus surrounding the display area, and the outer portion being a closed annulus surrounding the first opening.

[0026] For example, in a method for manufacturing a display panel provided in one embodiment of this disclosure, the opening further includes a non-annular opening spaced apart from the first opening.

[0027] For example, a method for manufacturing a display panel according to an embodiment of this disclosure includes: forming a planarization layer, wherein the planarization layer includes a portion located in the display area and a portion located in the border area, and performing a patterning process on a material layer for forming the planarization layer to form the organic barrier layer.

[0028] For example, a method for manufacturing a display panel according to an embodiment of the present disclosure further includes forming a light-emitting device on the portion of the planar layer located in the display area.

[0029] For example, in a method for manufacturing a display panel according to an embodiment of this disclosure, the direction from the display area to the frame area is a first direction, and forming the peripheral circuit includes: forming a first signal line and a functional element, wherein the first signal line extends along a second direction intersecting the first direction; the orthographic projection of the first signal line on the substrate is located within the orthographic projection of the organic barrier layer on the substrate, and the orthographic projection of the opening on the substrate does not coincide with the orthographic projection of the first signal line on the substrate.

[0030] For example, in a method for manufacturing a display panel provided in an embodiment of this disclosure, the direction from the display area to the frame area is a first direction, and forming the peripheral circuit further includes: forming a second signal line extending along the first direction signal line, wherein the second signal line includes a first part and a second part connected in series with each other, the first part being exposed by the opening, and the second part not being exposed by the opening; the first part includes at least two traces connected in parallel, and the second part is a single trace. Attached Figure Description

[0031] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0032] Figure 1 A plan view of a display panel provided according to an embodiment of this disclosure;

[0033] Figure 2A For along Figure 1 A schematic diagram of a cross-section of line I-I' in the diagram;

[0034] Figure 2B For along Figure 1 Another cross-sectional diagram of line I-I' in the diagram;

[0035] Figure 2C For along Figure 1 Another cross-sectional diagram of the I-I' line in the diagram;

[0036] Figure 2D For along Figure 1 Another cross-sectional diagram of the I-I' line in the diagram;

[0037] Figure 2E A schematic diagram of a peripheral circuit provided in an embodiment of this disclosure;

[0038] Figure 3 A plan view of a display panel provided according to an embodiment of this disclosure;

[0039] Figure 4 For along Figure 3 A schematic diagram of the cross-section of the G-G' line in the diagram;

[0040] Figure 5 This is a schematic diagram of a display device provided according to an embodiment of the present disclosure. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. The embodiments described below are some, but not all, embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0042] Unless otherwise defined, the technical or scientific terms used herein should be understood in their ordinary sense by one of ordinary skill in the art to which this invention pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as “comprising” or “including” indicate that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0043] At least one embodiment of this disclosure provides a display panel having a display area and a border area surrounding the display area, and including a substrate, peripheral circuitry, and a blocking structure. The peripheral circuitry is located on the substrate and in the border area; the blocking structure is located on the substrate, and its orthographic projection on the substrate at least partially coincides with the orthographic projection of the peripheral circuitry on the substrate; the blocking structure includes an organic blocking layer and an inorganic blocking layer, the organic blocking layer including an opening in the border area, the organic blocking layer being interrupted at the opening; the inorganic blocking layer covering the organic blocking layer and filling the opening.

[0044] For example, Figure 1 This is a plan view of a display panel provided according to an embodiment of the present disclosure. Figure 2A For along Figure 1 A schematic cross-sectional view of line I-I' in the diagram. Combined with... Figure 1 and Figure 2A The display panel 10 has a display area 101 and a border area 102 surrounding the display area 101. It should be noted that the display area 101 refers to a light-emitting area with display function, such as having multiple pixel units arranged in an array. The border area 102 refers to a non-light-emitting area, for example, the border area 102 surrounds the entire display area 101.

[0045] The display panel 10 includes a substrate 1, peripheral circuits 2, a barrier structure 3, an encapsulation substrate 15, and encapsulating adhesive 13. The bezel area 102 includes a peripheral circuit area 1020, with the peripheral circuits 2 located on the substrate 1 and within the peripheral circuit area 1020. The barrier structure 3 is located on the substrate 1 and includes an organic barrier layer 31 and an inorganic barrier layer 32. The organic barrier layer 31 includes an opening 3101 penetrating through it, the extension direction of which is approximately the same as the extension direction of the edge of the display panel near the opening 3101. The organic barrier layer 31 is interrupted at the opening 3101, meaning the opening 3101 divides the organic barrier layer 31 into multiple spaced-apart portions. The inorganic barrier layer 32 covers the organic barrier layer 31 and fills the opening 3101. The inorganic barrier layer 32 and the organic barrier layer 31 can prevent external moisture and oxygen from entering the display area. Organic materials have weaker barrier capabilities against moisture and oxygen, while inorganic materials have stronger barrier capabilities against moisture and oxygen. Since the opening 3101 breaks the inorganic barrier layer 32 in the frame area 102, and the organic barrier layer 31 covers and fills the opening 3101, alternating inorganic and organic barrier layers are formed in the direction from the frame area 102 to the display area 101, thereby enhancing the barrier structure 3's ability to block water vapor and oxygen in the direction from the frame area 102 to the display area 101. The encapsulation substrate 15 is disposed on the side of the barrier structure 3 away from the substrate 1; the encapsulating adhesive 13 is filled between the substrate 1 and the encapsulation substrate 15, covering the display area 101 and the peripheral circuit area 1020.

[0046] Furthermore, the orthographic projection of the blocking structure 3 on the substrate 1 at least partially overlaps with the orthographic projection of the peripheral circuit region 1020 on the substrate 1, for example, as Figure 1 and Figure 2A As shown, a portion of the orthographic projection of the blocking structure 3 on the substrate 1 overlaps with the orthographic projection of the peripheral circuit region 1020 on the substrate 1. Furthermore, the orthographic projection of the opening 3101 on the substrate 1 lies within the orthographic projection of the peripheral circuit region 1020 on the substrate 1, so that the blocking structure 3 at least partially overlaps with the peripheral circuit 2 in a direction perpendicular to the substrate 1. This enhances the blocking capability of the organic blocking layer 31 while reducing the bezel of the display panel 10. For example, the peripheral circuit 2 is a driving circuit (e.g., a GOA driving circuit) that provides scanning signals for driving the pixel units arranged in an array in the display area 101.

[0047] It should be noted that the organic barrier layer 31 is not a sealing adhesive (dam adhesive) used for sealing. For example, the display panel also includes a sealing adhesive 11 located in the peripheral area and surrounding the barrier structure 3. The opening 3101 of the organic barrier layer 31 is located between the sealing adhesive 11 and the display area 101 to better block moisture and oxygen that are not absorbed by the sealing adhesive 11. The sealing adhesive 11 is connected to the substrate 1 and the encapsulation substrate 15 respectively, and the encapsulation adhesive 13 fills the area enclosed by the sealing adhesive 11, the substrate 1, and the encapsulation substrate 15. For example, the sealing adhesive 11 is a U-shaped dam adhesive surrounding the barrier structure 3.

[0048] For example, the organic barrier layer 31 is located on the side of the sealant 11 near the display area 101, and the inorganic barrier layer 32 includes a portion 321 located between the organic barrier layer 31 and the sealant 11, so as to achieve a better effect of blocking water vapor and oxygen in the direction from the frame area 102 to the display area 101.

[0049] For example, there is a gap 14 between the inorganic barrier layer 32 and the sealant 11 to increase the transmission path of water vapor and oxygen from the sealant 11 to the display area 101. The gap 14 has a buffering effect, thereby achieving a better effect of blocking water vapor and oxygen in the direction from the frame area 102 to the display area 101.

[0050] Figure 2D For along Figure 1 Another cross-sectional view of the I-I' line. For example, display panel 10 employs face seal (or Dam & Fill). Exemplarily, as... Figure 2D As shown, the display panel 10 also includes an encapsulation layer 4, which covers the display area 101 and the inorganic barrier layer 32. The encapsulation layer 4 covers the upper surface of the inorganic barrier layer 32 away from the substrate 1 and the side facing the sealant 11. Thus, the encapsulation layer 4 covers and seals the display area 101 and at least a portion of the border area 102. For example, the encapsulation layer 4 includes an inorganic encapsulation layer. For example, in some embodiments, the encapsulation layer 4 may also include an organic encapsulation layer stacked with the inorganic encapsulation layer. Those skilled in the art can design the material structure of the encapsulation layer 4 according to conventional techniques, and this disclosure does not limit this aspect. In the case of surface encapsulation, the display panel 10 may also include a sealant 11 disposed around the edge of the encapsulation layer to provide a sealing effect. The sealant 11 may also include water-absorbing materials, oxygen-absorbing materials, etc., to reduce the amount of water vapor and oxygen entering the display area 101 from the outside.

[0051] Figure 2D The other structural and technical effects of the display panel shown are the same as those of the previous version. Figure 2A For the same information, please refer to the description of 2A.

[0052] For example, in Figure 2AIn the illustrated embodiment, the inorganic barrier layer 32 can serve as an encapsulation layer to simplify the structure of the display panel 10. For example, the inorganic barrier layer 32 covers the display area 101 and the organic barrier layer 31. For example, the inorganic barrier layer 32 covers the upper surface of the organic barrier layer 31 away from the substrate 1 and the side surface facing the sealant 11, thereby the encapsulation layer 4 seals the display area 101 and at least part of the frame area 102.

[0053] For example, such as Figure 1 As shown, opening 3101 is a closed annulus surrounding display area 101, that is, the opening includes a closed annular first opening surrounding display area, which is opening 3101. The closed annular first opening 3101 divides the organic barrier layer 31 into an inner portion 311 close to display area 101 and an outer portion 312 away from display area 101. The inner portion 311 is a closed annulus surrounding display area 101, and the outer portion 312 is a closed annulus surrounding the first opening 3101. This achieves a tight sealing effect, thereby enhancing the barrier structure's effect of blocking water vapor and oxygen in the direction from frame area 102 to display area 101 at various locations surrounding display area 101.

[0054] For example, the width l of the first opening 3101 in the direction from the bezel area to the display area is 1 μm to 5000 μm. Those skilled in the art can design it according to the actual required width of the bezel area of ​​the display panel.

[0055] For example, in Figure 2AIn the illustrated embodiment, the display panel 10 further includes a planarization layer 5, which comprises a portion located in the display area 101 and a portion located in the border area 102. The portion of the planarization layer 5 located in the display area 101 can form a flat surface to facilitate the formation of a light-emitting device on the flat surface. For example, the display panel 10 also includes a light-emitting device 6 located in the display area 101 and on the portion of the planarization layer 5 located in the display area 101. For example, the light-emitting device 6 is an electroluminescent device, such as an OLED light-emitting device, a Micro LED light-emitting device, etc. The light-emitting device 6 includes an anode, a light-emitting layer, and a cathode in a direction perpendicular to the substrate 1. For example, the cathode is a single layer, and the material of the single-layer cathode is aluminum (Al), magnesium / silver (Mg:Ag, i.e., stacked magnesium and silver films) indium tin oxide (IZO), aluminum-doped zinc oxide (AZO), etc. For example, the cathode may also include multiple layers stacked in a direction perpendicular to the substrate 1, such as a transparent conductive layer and a light-transmitting metal film stacked in a direction perpendicular to the substrate 1. The transparent conductive layer is made of materials such as IZO or AZO, and the transparent metal film is made of materials such as Ag or Mg:Ag. For example, the display panel 10 also includes a pixel driving circuit 9 located in the display area 101 for controlling the light emission state of the pixel unit, which can be designed by those skilled in the art according to conventional techniques.

[0056] For example, the planarization layer 5 may be made of resin, photoresist, or other similar materials. The thickness of the planarization layer 5 in the direction perpendicular to the substrate 1 is 0.2 μm to 3 μm. Of course, the materials and thicknesses of the planarization layer 5 described above are merely exemplary, and this disclosure does not limit their application; they can be selected as needed.

[0057] Of course, the encapsulation layer 4 is not limited to only one inorganic barrier layer 32. For example, it may include other organic and inorganic encapsulation layers stacked with the inorganic barrier layer 32 in a direction perpendicular to the substrate 1. Those skilled in the art can design it according to conventional techniques.

[0058] Figure 2B For along Figure 1 Another cross-sectional diagram of the I-I' line. For example, in Figure 2B In the embodiment shown, the planarization layer 5 serves as the organic barrier layer 31. That is, the organic barrier layer 31 with the opening is formed by performing a patterning process on the material layer used to form the planarization layer 5, without the need to form an additional organic barrier layer 31, thereby simplifying the structure and manufacturing process of the display panel 10.

[0059] Figure 2B Other features of the illustrated embodiments and Figure 2A The same applies to [the text], please refer to [the text]. Figure 2A The description.

[0060] like Figure 1and Figure 2A As shown, the direction from the display area 101 to the border area 102 is the first direction (e.g., Figure 1 The peripheral circuit 2, as indicated by the arrow in the figure, also includes a first signal line 21 and functional devices (not shown). The first signal line 21 extends along a second direction intersecting the first direction. These functional devices may include, for example, thin-film transistors and capacitors. For example, the second direction may be perpendicular to the first direction, and the first signal line 21 may extend along the border of the display panel 10. The orthographic projection of the first signal line 21 onto the substrate 1 lies within the orthographic projection of the organic barrier layer 31 onto the substrate 1, and the orthographic projection of the opening (e.g., the first opening 3101) onto the substrate 1 does not overlap with the orthographic projection of the first signal line 21 onto the substrate 1. In other words, the first signal line 21 does not overlap with the opening in the direction perpendicular to the substrate 1, and the entire first signal line 21 is not exposed by the first opening 3101. For example, in OLED display panels, especially large-size OLED display panels, masks are required during the evaporation, construction, and chemical deposition (CVD) processes of the organic light-emitting layer and the metal film layers used to form circuit traces or electrodes for light-emitting devices. During the mask deposition process, metal traces (e.g., the first signal line 21) of the peripheral circuits located between the display area and the encapsulant are easily scratched. Therefore, if the first signal line 21 is placed at the location corresponding to the aforementioned opening, it is easily damaged during the manufacturing process of the display panel 10, potentially causing signal short circuits and other display issues. To reduce or avoid scratches on the metal traces of surrounding circuits, such as the first signal line 21, in this embodiment, since the organic barrier layer 31 covers the first signal line 21 in a direction perpendicular to the substrate 1, and the orthogonal projection of the first opening 3101 on the substrate 1 does not overlap with the orthogonal projection of the first signal line 21 on the substrate 1, the organic barrier layer 31 can further protect the first signal line 21, preventing the first signal line 21 from being damaged or broken due to its placement at the opening, thereby avoiding the problem that the first signal line 21 is easily damaged during the manufacturing process of the display panel 10.

[0061] For example, such as Figure 2A As shown, the peripheral circuit 2 includes multiple first signal lines 21, which are arranged on the same layer, and two adjacent first signal lines 21 are arranged in a specific order (e.g., two lines with the same name, two lines with the same name, two lines with the same name, and ... Figure 2A Taking adjacent first signal lines 211 and 212 as an example, there is a gap between them. The orthographic projection of the opening (e.g., the first opening 3101) on the substrate 1 is located within the orthographic projection of the gap between two adjacent 211 and 212 of the multiple first signal lines 21 on the substrate 1. In this way, while playing the role of the opening, the problem that the first signal lines 21 are easily damaged during the manufacturing process of the display panel 10 is solved.

[0062] For example, the display panel 10 also includes a protective layer 8, which covers the first signal line 21 and is located between the first signal line 21 and the organic barrier layer 31 to further protect the first signal line 21. At the same time, the protective layer 8 also serves to block moisture and oxygen. For example, the material of the protective layer 8 is an organic material such as resin.

[0063] For example, the protective layer 8 is located in the border area 102 and is spaced apart from the display area 101, and the inorganic barrier layer 32 covers the protective layer 8. The protective layer 8 can be set separately, or it can be set in the same layer as the insulating layer in the display area 101 (such as the interlayer insulating layer in the pixel circuit of the display area) and made of the same material. That is, the protective layer 8 is formed by using the insulating layer in the display area 101 to simplify the manufacturing process and reduce the manufacturing difficulty of the display panel 10.

[0064] For example, such as Figure 1 and Figure 2A As shown, the peripheral circuit 2 includes a second signal line 22 extending from the display area 101 along a first direction to the bezel area 102; the second signal line 22 includes a first portion 221 and a second portion 222 connected in series. The first portion 221 is exposed by the aforementioned opening (e.g., the first opening 3101), while the second portion 222 is not exposed by the opening. That is, the orthographic projection of the first portion 221 on the substrate 1 overlaps with the orthographic projection of the first opening 3101 on the substrate 1, while the orthographic projection of the second portion 222 on the substrate 1 does not overlap with the orthographic projection of the first opening 3101 on the substrate 1 (there is no overlapping portion). The first portion 221 includes at least two traces connected in parallel, and the second portion is a single trace. For example, in Figure 1 In the first part 221, there are two parallel traces 2211 and 2212. The second part 222 includes a first segment 2221 and a second segment 2222. At the position corresponding to the inner part 311 of the organic barrier layer 31, the first segment 2221 is a single trace. At the position corresponding to the first opening 3101, the second signal line 22 is divided into two parallel traces 2211 and 2212, both of which are connected in series with the first segment 2221. At the position corresponding to the outer part 312 of the organic barrier layer 31, the two traces 2211 and 2212 merge back into a single trace, namely, the second segment 2222. Since the second signal line 22, which overlaps with the orthographic projection of the first opening 3101 on the substrate 1, is easily broken or damaged during the manufacturing process of the display panel 10, the fact that the first part 221 includes at least two parallel traces can avoid the problem that the signal line exposed by the first opening 3101 is easily damaged.

[0065] In other embodiments, the second signal line 22 may also include a portion located in the display area 101, integrally formed with the gate lines in the display area 101, the gate lines being a part of the second signal line 22. For example, the second signal line 22 may be electrically connected to the gate lines in the display area 101.

[0066] refer to Figure 2A The display panel 10 also includes an insulating layer 7, which is located between the first signal line 21 and the second signal line 22 to insulate the first signal line 21 from the second signal line 22.

[0067] For example, in Figure 2A In the illustrated embodiment, the first signal line 21 is located on the side of the second signal line 22 away from the substrate 1. Of course, in other embodiments, the first signal line 21 may also be located on the side of the second signal line 22 closer to the substrate 1.

[0068] The first signal line 21 can be a signal line of any function. For example, the peripheral circuit 2 is a gate drive circuit (GOA drive circuit), and the first signal line 21 is a clock signal line in the GOA drive circuit.

[0069] For example, Figure 2E This is a schematic diagram of a peripheral circuit provided according to an embodiment of the present disclosure. For example... Figure 2E As shown, the gate driving circuit 2 includes multiple cascaded shift register units 100, wherein any one or more shift register units 100 can adopt the structure of the shift register unit 100 provided in any embodiment of this disclosure or a variation thereof. For example, the gate driving circuit 2 can be directly integrated on the array substrate of the display device using the same semiconductor process as thin-film transistors to realize progressive or interlaced scanning driving functions.

[0070] Except for the first-level shift register unit, the input terminal INT of the remaining shift register units is connected to the output terminal OUT of the shift register unit above it; except for the last shift register unit, the reset terminal RST of the remaining shift register units is connected to the output terminal OUT of the shift register unit below it.

[0071] like Figure 2EAs shown, the gate driving circuit 2 further includes a first clock signal line CLK1 and a second clock signal line CLK2. For example, the first signal line 21 includes the first clock signal line CLK1 and the second clock signal line CLK2. For example, the first clock signal line CLK1 and the second clock signal line CLK2 are respectively connected to the clock signal terminals CLK of multiple cascaded shift register units to provide clock signals. For example, the reset control signal includes the clock signal provided by the first clock signal line CLK1 and the second clock signal line CLK2. It should be noted that the gate driving circuit 2 may also include four, six, eight, or more clock signal lines. The number of clock signal lines depends on the specific situation, and the embodiments of this disclosure are not limited thereto. The first signal line 21 may include the four, six, eight, or more clock signal lines.

[0072] For example, such as Figure 2E As shown, each of the shift register units also includes a clock signal terminal CLK, configured to be connected to a first clock signal line CLK1 or a second clock signal line CLK2 to receive a first clock signal or a second clock signal. The first clock signal line CLK1 is connected to the clock signal terminal CLK of the (2n-1)th stage shift register unit (n is an integer greater than 0), and the second clock signal line CLK2 is connected to the clock signal terminal CLK of the (2n-1)th stage shift register unit. It should be noted that embodiments of this disclosure include, but are not limited to, the above connection method. For example, the following connection method may also be used: the first clock signal line CLK1 is connected to the clock signal terminal CLK of the (2n-1)th stage shift register unit, and the second clock signal line CLK2 is connected to the clock signal terminal CLK of the (2n-1)th stage shift register unit.

[0073] It should be noted that, Figure 2E In the diagram, OUT_m (where m is an integer greater than 0) represents the output of the m-th shift register unit, OUT_m+1 represents the output of the (m+1)-th shift register unit, OUT_m+2 represents the output of the (m+2)-th shift register unit, and so on. The reference numerals in the following embodiments are similar and will not be repeated.

[0074] For example, the input terminal INT of the first-stage shift register unit can be configured to receive the trigger signal STV, and the reset terminal RST of the last-stage shift register unit can be configured to receive the reset signal. For simplicity, the trigger signal STV and the reset signal are... Figure 2E Not shown in the image.

[0075] For example, the gate drive circuit 2 further includes a first voltage line, a second voltage line, a third voltage line, and a fourth voltage line (not shown in the figure). For example, the first voltage line is connected to the first voltage terminal VDD and configured to provide a first voltage; the second voltage line is connected to the second voltage terminal VSS and configured to provide a second voltage; the third voltage line is connected to the third voltage terminal VGH1 and configured to provide a third voltage; and the fourth voltage line is connected to the fourth voltage terminal VGH2 and configured to provide a fourth voltage.

[0076] For example, the first signal line can also be the first voltage line or the second voltage line mentioned above.

[0077] For example, such as Figure 2E As shown, the gate drive circuit 2 may further include a timing controller 300. For example, the timing controller 300 may be configured to be connected to the first clock signal line CLK1 and the second clock signal line CLK2 to provide clock signals to each shift register unit; the gate drive circuit 10 may also be configured to be connected to a first voltage line, a second voltage line, a third voltage line, and a fourth voltage line to provide the first voltage to the fourth voltage to each shift register unit 100 respectively. For example, the timing controller 300 may also be configured to provide a trigger signal STV and a reset signal.

[0078] For example, the pixel circuit of each pixel unit in the display area includes a display signal line (Data line) configured to provide a signal for controlling the display grayscale of the light-emitting device. The peripheral circuit may also include a portion of the display signal line extending into the peripheral circuit area, and the first signal line may also be a portion of the display signal line extending into the peripheral circuit area.

[0079] For example, the second signal line 22 is a scan signal line used to provide scan signals to the pixel units arranged in an array in the display area 101. It is connected to the gate lines in the display area 101 and is integrally formed with the gate lines. The second signal line 22 has a bent portion in the bezel area, and the bent portion is connected to another part 12 of the gate drive circuit. This other part 12 is, for example, a scan signal integrated chip. For example, as... Figure 2E As shown, the second signal line 22 includes an m-th level scan signal line extending from the output terminal OUT_m (m is an integer greater than 0) of the m-th level shift register unit to the display area (AA), an (m+1)-th level scan signal line extending from the output terminal OUT_m+1 of the (m+1)-th level shift register unit to the display area, an (m+2)-th level scan signal line extending from the output terminal OUT_m+2 of the (m+2)-th level shift register unit to the display area, and so on. The embodiments of this disclosure do not limit the number of scan signal lines included in the second signal line 22.

[0080] For example, the first signal line 21 and the second signal line 22 are metal traces.

[0081] For example, in Figure 2A In the illustrated embodiment, the width d of the border area 102 in the first direction is less than 5 mm, thereby achieving a narrower border. In this case, the aforementioned effective blocking of water vapor and oxygen is achieved simultaneously through the cooperation of the organic barrier layer 31 including the opening and the inorganic barrier layer 32.

[0082] For example, in another embodiment of this disclosure, the width d of the border area 102 in the first direction is ≥ 5mm. By increasing the width of the border area 102, the transmission path of water vapor and oxygen from the sealing adhesive 11 to the display area 101 is increased, thereby achieving a better effect of blocking water vapor and oxygen in the direction from the border area 102 to the display area 101. The width of the border area 102 in the first direction can be determined according to requirements, and this embodiment of the disclosure does not limit it.

[0083] For example, in this embodiment, the organic barrier layer 31 may be made of organic materials such as resin, including oxygen-absorbing or water-absorbing materials. For example, the inorganic barrier layer 32 may be made of at least one of silicon oxide, silicon nitride, or silicon oxynitride. The materials of the organic barrier layer 31 and the inorganic barrier layer 32 are not limited to the types listed above, and this embodiment does not impose any limitations on them.

[0084] Figure 2C For along Figure 1 Another cross-sectional diagram of the I-I' line. For example, in Figure 2C In the illustrated embodiment, the display panel 10 can also be encapsulated using a sealing adhesive 11, an encapsulating adhesive 13, and an encapsulation substrate 15. The encapsulation substrate 15 is disposed opposite to the substrate 1, and the sealing adhesive 11 bonds the encapsulation substrate 15 and the substrate 1 together. The encapsulating adhesive 13 fills the space between the inorganic barrier layer 4 and the encapsulation substrate 15, and the encapsulating adhesive 13 includes water-absorbing materials, oxygen-absorbing materials, or heat-insulating materials, etc., to prevent the light-emitting devices 6 of the display area 101 from being damaged by external moisture, oxygen, and heat.

[0085] Figure 2C Other features of the illustrated embodiments and Figure 2A The same applies to [the text], please refer to [the text]. Figure 2A The description.

[0086] Figure 3 This is a plan view of a display panel provided according to an embodiment of the present disclosure. Figure 4 For along Figure 3 A schematic diagram of the cross-section of the G-G' line. (See diagram below.) Figure 3 and Figure 4 As shown, the display panel 10 and Figure 2AThe display panel shown has the following differences. The organic barrier layer 31 includes a plurality of openings located in the bezel area 102. For example, the openings include the first opening 3101 described above and a non-annular opening 3102 spaced apart from the first opening 3101. The non-annular opening 3102 is located in the outer portion 312 or the inner portion 311 of the organic barrier layer 31. For example, in this embodiment, the non-annular opening 3102 is located in the outer portion 312 of the organic barrier layer 31. In other embodiments, a non-annular opening may also be provided in the inner portion 311, or non-annular openings may be provided in both the inner portion 311 and the outer portion 312.

[0087] like Figure 4 As shown, the first portion 221 of the second signal line 22 includes a first interval and a second interval, which are exposed by the first opening 3101 and the non-annular opening 3102, respectively. The second portion 222 of the second signal line 22 includes a first segment 2221, a second segment 2222, and a third segment 2223 that are not exposed by the first opening 3101 and the non-annular opening 3102. That is, the orthographic projection of the first interval on the substrate 1 overlaps with the orthographic projection of the first opening 3101 on the substrate 1, the orthographic projection of the second interval on the substrate 1 overlaps with the orthographic projection of the non-annular opening 3102 on the substrate 1, and the orthographic projections of the first segment 2221, the second segment 2222, and the third segment 2223 on the substrate 1 do not overlap with the orthographic projections of the first opening 3101 and the non-annular opening 3102 on the substrate 1 (there is no overlapping portion). Reference Figure 3 and Figure 4 The first and second intervals each include at least two parallel traces, while the first segment 2221, the second segment 2222, and the third segment 2223 of the second part 22 are all single traces. The first interval of the first part 221 includes two parallel traces 2211 and 2212, and the second interval of the first part 221 includes two parallel traces 2213 and 2214. The first segment 2221, the two traces 2211 and 2212, the second segment 2222, the two traces 2213 and 2214, and the third segment 2223 are connected in series. The technical effect of this design is described above.

[0088] At least one embodiment of this disclosure also provides a display device, which includes any of the display panels provided in the embodiments of this disclosure.

[0089] For example, Figure 5 This is a schematic diagram of a display device provided according to an embodiment of the present disclosure. Figure 5As shown, the display device 100 includes any of the display panels 10 provided in the embodiments of this disclosure. The display device 100 may be, for example, an OLED display device or a Micro LED display device. For example, the display device 100 may be any device with display functionality, such as a mobile phone, tablet computer, television, laptop computer, digital photo frame, or navigator. Other structures of the display device 100 besides the display panel can be designed by those skilled in the art according to specific needs and conventional techniques in the field.

[0090] At least one embodiment of this disclosure also provides a method for manufacturing a display panel, the display panel having a display area and a border area surrounding the display area, the method comprising: providing a substrate; forming a barrier structure on the substrate, including: forming an organic barrier layer, wherein the organic barrier layer includes an opening penetrating the organic barrier layer, wherein the extending direction of the opening is substantially the same as the extending direction of the edge of the display panel near the opening; and forming an inorganic barrier layer covering the organic barrier layer and filling the opening; the method for manufacturing the display panel further comprising: forming peripheral circuitry on the substrate, wherein the border area includes a peripheral circuitry area, the peripheral circuitry being located in the peripheral circuitry area; providing an encapsulation substrate; forming an encapsulating adhesive covering the display area and the peripheral circuitry area; and mating the encapsulation substrate with the substrate such that the barrier structure is located away from the substrate, and the encapsulating adhesive is filled between the substrate and the encapsulation substrate.

[0091] This manufacturing method can form alternating inorganic and organic barrier layers in the direction from the bezel area to the display area, thereby enhancing the barrier structure's ability to block water vapor and oxygen in the direction from the bezel area to the display area.

[0092] For example, in one embodiment, such as Figure 1 and Figure 2A The method for manufacturing the display panel 10 shown further includes: forming a sealant 11 on a substrate 1, wherein the sealant 11 is located in the peripheral area of ​​the border area 102, and the opening 3101 of the organic barrier layer 31 is located between the sealant 11 and the display area 101. For example, the organic barrier layer 31 is located on the side of the sealant 11 closer to the display area 101, and the inorganic barrier layer 32 includes a portion 321 located between the organic barrier layer 31 and the sealant 11.

[0093] For example, such as Figure 1As shown, the formed opening 3101 is a closed annulus surrounding the display area 101, that is, the opening includes a closed annular first opening surrounding the display area, which is opening 3101. The closed annular first opening 3101 divides the organic barrier layer 31 into an inner portion 311 close to the display area 101 and an outer portion 312 away from the display area 101. The inner portion 311 is a closed annulus surrounding the display area 101, and the outer portion 312 is a closed annulus surrounding the first opening 3101. This achieves a tight sealing effect, thereby enhancing the barrier structure's effect of blocking water vapor and oxygen in the direction from the frame area 102 to the display area 101 at various locations surrounding the display area 101.

[0094] For example, Figure 2B The method for manufacturing the display panel 10 shown includes: forming a planarization layer 5, which includes a portion located in the display area 101 and a portion located in the border area 102. The portion of the planarization layer 5 located in the display area 101 can form a flat surface to facilitate the formation of the light-emitting device 6 on the flat surface. The planarization layer 5 serves as an organic barrier layer 31, that is, an organic barrier layer 31 with the opening is formed by performing a patterning process on the material layer used to form the planarization layer 5, eliminating the need to form a separate organic barrier layer 31, thereby simplifying the manufacturing process of the display panel 10.

[0095] For example, the method of manufacturing the display panel further includes forming a light-emitting device 6 on the portion of the planarization layer 5 located in the display area 101. For example, the light-emitting device 6 is an electroluminescent device, such as an OLED light-emitting device or a Micro LED light-emitting device. The light-emitting device 6 includes an anode, a light-emitting layer, and a cathode in a direction perpendicular to the substrate 1. For example, the display panel 10 also includes a pixel driving circuit 9 located in the display area 101 for controlling the light-emitting state of the pixel units, which can be designed by those skilled in the art according to conventional techniques.

[0096] The method for manufacturing a display panel further includes providing an encapsulation substrate 15; forming an encapsulating adhesive 13 covering the display area 101 and the peripheral circuit area 102; and mating the encapsulation substrate 15 with a substrate 1 such that the barrier structure 31 is away from the side of the substrate 1, and the encapsulating adhesive 13 is filled between the substrate 1 and the encapsulation substrate 15. A frame sealant 11 is respectively connected to the substrate 1 and the encapsulation substrate 15, and the encapsulating adhesive 13 fills the area enclosed by the frame sealant 11, the substrate 1, and the encapsulation substrate 15.

[0097] like Figure 1 and Figure 2A As shown, the direction from the display area 101 to the border area 102 is the first direction (e.g., Figure 1The peripheral circuit 2, as shown by the arrow in the figure, includes forming a first signal line 21 and functional devices (not shown). The first signal line 21 extends along a second direction intersecting the first direction. The functional devices include, for example, thin-film transistors and capacitors. For example, the second direction is perpendicular to the first direction, and the first signal line 21 extends along the border of the display panel 10. The orthographic projection of the first signal line 21 onto the substrate 1 lies within the orthographic projection of the organic barrier layer 31 onto the substrate 1, and the orthographic projection of the opening (e.g., the first opening 3101) onto the substrate 1 does not overlap with the orthographic projection of the first signal line 21 onto the substrate 1. That is, the first signal line 21 does not overlap with the opening in the direction perpendicular to the substrate 1, and the first signal line 21 is not exposed by the opening. For example, in OLED display panels, especially large-size OLED display panels, masks are required during the evaporation, construction, and chemical vapor deposition (CVD) processes of the organic light-emitting layer and the metal film layers used to form circuit traces or electrodes for light-emitting devices. During the mask deposition process, the metal traces of the peripheral circuits (e.g., the first signal line 21) located between the display area and the encapsulant can easily be scratched. Therefore, if the first signal line 21 is placed at the position corresponding to the opening mentioned above, the first signal line 21 is easily damaged during the manufacturing process of the display panel 10, which can lead to display defects such as signal short circuits. In order to reduce or avoid scratches on the metal traces of the surrounding circuits, such as the first signal line 21, in this embodiment of the present disclosure, since the organic barrier layer 31 covers the first signal line 21 in a direction perpendicular to the substrate 1, and the orthographic projection of the opening (e.g., the first opening 3101) on the substrate 1 does not overlap with the orthographic projection of the first signal line 21 on the substrate 1, the organic barrier layer 31 can further protect the first signal line 21, prevent the first signal line 21 from being damaged or broken due to the first signal line 21 being placed at the opening, thereby avoiding the problem that the first signal line 21 is easily damaged during the manufacturing process of the display panel 10.

[0098] For example, such as Figure 2A As shown, forming the peripheral circuit 2 includes forming a plurality of first signal lines 21, wherein the plurality of first signal lines 21 are arranged on the same layer, and two adjacent first signal lines 21 are arranged in a row (with the first signal line 21 being the first signal line 21). Figure 2A Taking adjacent first signal lines 211 and 212 as an example, there is a gap between them. The orthographic projection of the opening (e.g., the first opening 3101) on the substrate 1 is located within the orthographic projection of the gap between two adjacent 211 and 212 of the multiple first signal lines 21 on the substrate 1. In this way, while playing the role of the opening, the problem that the first signal lines 21 are easily damaged during the manufacturing process of the display panel 10 is solved.

[0099] For example, such as Figure 2AAs shown, the manufacturing method of the display panel 10 also includes forming a protective layer 8, wherein the protective layer 8 covers the first signal line 21 and is located between the first signal line 21 and the organic barrier layer 31 to further protect the first signal line 21, while the protective layer 8 also serves to block moisture and oxygen. For example, the material of the protective layer 8 is an organic material such as resin.

[0100] For example, the protective layer 8 is located in the border area 102 and is spaced apart from the display area 101, and the inorganic barrier layer 32 covers the protective layer 8. The protective layer 8 can be set separately, or it can be set in the same layer as the insulating layer in the display area 101 (such as the interlayer insulating layer in the pixel circuit of the display area) and made of the same material. That is, the protective layer 8 is formed by using the insulating layer in the display area 101 to simplify the manufacturing process and reduce the manufacturing difficulty of the display panel 10.

[0101] For example, such as Figure 1 and Figure 2A As shown, forming the peripheral circuit 2 includes forming a second signal line 22 extending from the display area 101 along a first direction to the bezel area 102. The second signal line 22 includes a first portion 221 and a second portion 222 connected in series. The first portion 221 is exposed by the aforementioned opening (e.g., the first opening 3101), while the second portion 222 is not exposed by the opening. That is, the orthographic projection of the first portion 221 onto the substrate 1 overlaps with the orthographic projection of the first opening 3101 onto the substrate 1, while the orthographic projection of the second portion 222 onto the substrate 1 does not overlap with the orthographic projection of the first opening 3101 onto the substrate 1 (there is no overlapping portion). The first portion 221 includes at least two traces connected in parallel, and the second portion is a single trace. For example, in... Figure 1 In the first part 221, there are two parallel traces 2211 and 2212. The second part 222 includes a first segment 2221 and a second segment 2222. At the position corresponding to the inner part 311 of the organic barrier layer 31, the first segment 2221 is a single trace. At the position corresponding to the first opening 3101, the second signal line 22 is divided into two parallel traces 2211 and 2212, both of which are connected in series with the first segment 2221. At the position corresponding to the outer part 312 of the organic barrier layer 31, the two traces 2211 and 2212 merge back into a single trace, namely, the second segment 2222. Since the second signal line 22, which overlaps with the orthographic projection of the first opening 3101 on the substrate 1, is easily broken or damaged during the manufacturing process of the display panel 10, the fact that the first part 221 includes at least two parallel traces can avoid the problem that the signal line exposed by the first opening 3101 is easily damaged.

[0102] For example, such as Figure 3 and Figure 4The method of manufacturing the display panel 10 shown includes forming a plurality of the openings. For example, forming the first opening 3101 and a non-annular opening 3102 spaced apart from the first opening 3101. The non-annular opening 3102 is located within the outer portion 312 of the organic barrier layer 31 or within the inner portion 311 of the organic barrier layer 31. For example, in this embodiment, the non-annular opening 3102 is located within the outer portion 312 of the organic barrier layer 31. In other embodiments, the non-annular opening may also be formed within the inner portion 311, or non-annular openings may be formed in both the inner portion 311 and the outer portion 312.

[0103] like Figure 3 and Figure 4 As shown, the first portion 221 of the second signal line 22 includes a first interval and a second interval, which are exposed by the first opening 3101 and the non-annular opening 3102, respectively. The second portion 222 of the second signal line 22 includes a first segment 2221, a second segment 2222, and a third segment 2223 that are not exposed by the first opening 3101 and the non-annular opening 3102. That is, the orthographic projection of the first interval on the substrate 1 overlaps with the orthographic projection of the first opening 3101 on the substrate 1, the orthographic projection of the second interval on the substrate 1 overlaps with the orthographic projection of the non-annular opening 3102 on the substrate 1, and the orthographic projections of the first segment 2221, the second segment 2222, and the third segment 2223 on the substrate 1 do not overlap with the orthographic projections of the first opening 3101 and the non-annular opening 3102 on the substrate 1 (there is no overlapping portion). Reference Figure 3 and Figure 4 The first and second intervals each include at least two parallel traces. The first segment 2221, the second segment 2222, and the third segment 2223 of the second part 22 are all single traces. The first interval of the first part 221 includes two parallel traces 2211 and 2212, and the second interval of the first part 221 includes two parallel traces 2213 and 2214. The first segment 2221, the two traces 2211 and 2212, the second segment 2222, the two traces 2213 and 2214, and the third segment 2223 are connected in series.

[0104] For example, the aforementioned structures of the display panel can be formed using photolithography and semiconductor processes. For instance, the light-emitting layer of the light-emitting device can be fabricated using inkjet printing (IJP), vapor deposition, or other methods; the cathode of the light-emitting device can be formed using thermal evaporation, sputtering, or other methods; and the inorganic barrier layer and inorganic encapsulation layer can be formed using chemical vapor deposition (CVD). Those skilled in the art can select from conventional techniques.

[0105] For example, the manufacturing method of a display panel also includes a packaging process, which can be achieved by, for example, using... Figure 2AThe thin-film encapsulation shown utilizes encapsulation layer 4 for face sealing, or employs methods such as... Figure 2C The sealing adhesive 11, encapsulating adhesive 13, and encapsulation substrate 15 shown are used to encapsulate the display area to further prevent external moisture, oxygen, etc. from entering.

[0106] The structures and technical effects not mentioned in the embodiments of the display panel manufacturing method are the same as those in the embodiments concerning the display panel; please refer to the previous description.

[0107] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. The scope of protection of this disclosure is determined by the scope defined in the claims.

Claims

1. A display panel, comprising: a substrate, having a main surface, wherein the main surface comprises a display area and a bezel area located at a periphery of the display area, the bezel area comprises a peripheral circuit area and a peripheral area, the peripheral circuit area is disposed between the display area and the peripheral area; a barrier structure, at least partially located on the peripheral circuit area on the substrate and comprising: an organic barrier layer and an inorganic barrier layer covering the organic barrier layer, wherein the organic barrier layer comprises an opening penetrating the organic barrier layer in a direction perpendicular to the main surface of the substrate, an extending direction of the opening is substantially the same as an extending direction of an edge of the display panel close to the opening in the display panel; the inorganic barrier layer covers the organic barrier layer and fills the opening; a peripheral circuit, located on the substrate and located in the peripheral circuit area, wherein a normal projection of the organic barrier layer and the inorganic barrier layer on the substrate at least partially overlaps with a normal projection of the peripheral circuit area on the substrate; a packaging substrate, disposed on a side of the barrier structure away from the substrate; a sealant, located in the peripheral area and connected with the substrate and the packaging substrate respectively; and a packaging adhesive, at least located in the peripheral circuit area, filling an area surrounded by the sealant, the substrate and the packaging substrate, and covering at least the organic barrier layer, the inorganic barrier layer and the opening in the peripheral circuit area; a direction from the display area to the bezel area is a first direction, the peripheral circuit comprises a second signal line extending from the display area to the bezel area along the first direction; the second signal line comprises a first part and a second part connected with each other in series, a normal projection of the first part on the substrate overlaps with a normal projection of the opening on the substrate, a normal projection of the second part on the substrate does not overlap with a normal projection of the opening on the substrate; the first part comprises at least two wires connected in parallel, the second part is a single wire. an end of the sealant connected with the substrate directly contacts the substrate, and an end of the sealant connected with the packaging substrate directly contacts the packaging substrate. the organic barrier layer is located on a side of the sealant close to the display area, the inorganic barrier layer comprises a part located between the organic barrier layer and the sealant; the packaging adhesive covers and contacts the part of the inorganic barrier layer located between the organic barrier layer and the sealant. the packaging adhesive covers and contacts an upper surface of the inorganic barrier layer away from the substrate, and / or the packaging adhesive covers the entire inorganic barrier layer. 5.The display panel of claim 1, further comprising: a packaging layer, covering and sealing the display area and at least part of the bezel area, and comprising an inorganic packaging layer, wherein the inorganic packaging layer overlaps with the inorganic barrier layer in a direction perpendicular to the main surface of the substrate. the packaging layer further comprises an organic packaging layer laminated with the inorganic packaging layer in a direction perpendicular to the main surface of the substrate. ​ ​ ​ 2. The display panel of claim 1, wherein, ​ 3. The display panel of claim 1, wherein, ​ ​ 4. The display panel of claim 3, wherein, ​ ​ ​ 6. The display panel of claim 5, wherein, ​ 7. The display panel of any of claims 1-6, wherein, The opening includes a closed annular first opening surrounding the display area.

8. The display panel of claim 7, wherein, The closed annular first opening separates the organic barrier layer into an inner portion close to the display area and an outer portion away from the display area, the inner portion being closed annular and surrounding the display area, and the outer portion being closed annular and surrounding the first opening.

9. The display panel of claim 7, wherein, A width of the first opening in a direction from the frame area to the display area is 1 μm to 5000 μm.

10. The display panel of any of claims 1-6, wherein, A direction from the display area to the frame area is a first direction, and the peripheral circuit includes a first signal line and a functional element. The first signal line extends in a second direction intersecting the first direction.

11. The display panel of claim 10, wherein, A projection of the first signal line on the substrate is located within a projection of the organic barrier layer on the substrate, and a projection of the opening on the substrate does not overlap with a projection of the first signal line on the substrate.

12. The display panel of claim 11, wherein, The peripheral circuit includes a plurality of the first signal lines, and there is a gap between adjacent two of the plurality of the first signal lines, and a projection of the gap between adjacent two of the plurality of the first signal lines on the substrate is located within a projection of the opening on the substrate.

13. The display panel of claim 1, wherein, The second signal line is electrically connected to a gate line in the display area, and the gate line is a scanning signal line providing a scanning signal to a pixel unit in the display area.

14. The display panel of claim 13, wherein, The second signal line also includes a portion located in the display area, and the second signal line is integrally formed with the gate line in the display area.

15. The display panel of any of claims 1-6, wherein, A direction from the display area to the frame area is a first direction, and a width of the frame area in the first direction is d ≥ 5 mm.

16. The display panel of any of claims 1-6, wherein, A material of the organic barrier layer includes an organic material, and the organic material includes a resin, and the organic barrier layer includes an oxygen absorbing material or a water absorbing material. A material of the inorganic barrier layer includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.

17. The display panel of any of claims 1-6, wherein, The encapsulation adhesive includes a water absorbing material, an oxygen absorbing material, or a thermal insulation material.

18. The display panel according to any one of claims 1 to 6, further comprising: a planar layer including a portion located in the display area and a portion located in the frame area, wherein the portion of the planar layer located in the frame area is the organic barrier layer of the barrier structure.

19. A display panel, comprising: a substrate having a main surface, wherein the main surface includes a display area and a frame area located at a periphery of the display area, the frame area including a peripheral circuit area and a peripheral area, the peripheral circuit area being disposed between the display area and the peripheral area; a planar layer including a portion located in the display area and a portion located in the frame area; a light emitting device located in the display area and located on a side of the planar layer facing away from the substrate; a pixel circuit located in the display area and configured to control a light emitting state of the light emitting device; and a barrier structure including an organic barrier layer and an inorganic barrier layer. A barrier structure at least partially located in a bezel region on the substrate and comprising: an organic barrier layer and an inorganic barrier layer covering the organic barrier layer, wherein the organic barrier layer comprises an opening extending through the organic barrier layer in a direction perpendicular to a main surface of the substrate, and the extending direction of the opening is substantially the same as the extending direction of a display panel edge of the display panel close to the opening; and the inorganic barrier layer covers the organic barrier layer and fills the opening; A package substrate disposed on a side of the barrier structure away from the substrate; A sealant located in the bezel region and connected with the substrate and the package substrate respectively; A package adhesive at least located in the bezel region and filled in a region surrounded by the sealant, the substrate and the package substrate, and covering at least the organic barrier layer, the inorganic barrier layer and the opening in the peripheral circuit region; and A peripheral circuit located on the substrate and in the peripheral circuit region, wherein the orthographic projection of the organic barrier layer and the inorganic barrier layer on the substrate at least partially overlaps with the orthographic projection of the peripheral circuit region on the substrate; A direction from the display region to the bezel region is a first direction, and the peripheral circuit comprises a second signal line extending from the display region to the bezel region along the first direction; The second signal line comprises a first part and a second part connected with each other in series, the orthographic projection of the first part on the substrate overlaps with the orthographic projection of the opening on the substrate, and the orthographic projection of the second part on the substrate does not overlap with the orthographic projection of the opening on the substrate; The first part comprises at least two tracks connected in parallel, and the second part is a single track.

20. The display panel of claim 19, wherein, The part of the planar layer located in the bezel region serves as the organic barrier layer of the barrier structure.

21. A display device comprising the display panel of any one of claims 1-20.

Images