Method for preparing semiconductor structure

Abstract

The present application provides a method for fabricating a semiconductor structure, comprising the following steps: providing a substrate; sequentially forming a first etch stop layer, a first dielectric layer, a second etch stop layer, and a second dielectric layer on the substrate surface; forming a first photoresist layer to define a through-hole pattern; forming a through-hole; filling the through-hole with a bottom anti-reflection layer; performing back etching to ensure that the height of the bottom anti-reflection layer is lower than the depth of the through-hole; forming a second photoresist layer, forming a trench pattern in the second photoresist layer, the trench pattern being located directly above the through-hole and having a size larger than the through-hole; forming a trench located above the through-hole and stopping at the second etch stop layer; removing the remaining bottom anti-reflection layer, the first etch stop layer, and the second etch stop layer within the through-hole to form a funnel structure with a trench formed above the through-hole; and filling the funnel structure with an interconnect metal layer. The present application helps improve interconnect metal filling and enhance device performance.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a method for preparing a semiconductor structure. Background Art

[0002] With the rapid development of semiconductor technology, device feature sizes are shrinking while device integration is increasing. This has resulted in a shrinking space occupied by individual devices and an increasing number of structural layers. Consequently, the aspect ratios (depth to width ratios) of interconnect structures used to connect different conductive layers, such as various contact holes and vias, are increasing. This has made the deep hole filling process for manufacturing interconnect structures increasingly difficult. On the one hand, deep holes with too narrow openings are not conducive to filling with interconnect metal. On the other hand, deep hole filling is prone to defects such as gaps or voids, which can lead to a decrease in device electrical performance. In severe cases, this can even cause device leakage, affecting device reliability. Summary of the Invention

[0003] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a method for preparing a semiconductor structure, which is used to solve the problems in the prior art that the deep hole filling process becomes more difficult due to the increasing aspect ratio of the interconnect structure, and defects such as gaps or voids are easily generated, which affects the reliability of the device.

[0004] To achieve the above-mentioned and other related purposes, the present application provides a method for preparing a semiconductor structure, comprising the steps of:

[0005] providing a substrate;

[0006] forming a first etch stop layer, a first dielectric layer, a second etch stop layer and a second dielectric layer in sequence on the surface of the substrate;

[0007] forming a first photoresist layer on the surface of the second dielectric layer and performing patterning processing to define a through-hole pattern in the first photoresist layer;

[0008] Performing etching to form a through hole, wherein the through hole sequentially penetrates the second dielectric layer, the second etch stop layer, and the first dielectric layer downward until the first etch stop layer is exposed;

[0009] filling a bottom anti-reflection layer in the through hole;

[0010] Carving back the bottom anti-reflection layer so that the height of the bottom anti-reflection layer is lower than the depth of the through hole;

[0011] forming a second photoresist layer covering the through hole and the second dielectric layer, and performing patterning to form a groove pattern in the second photoresist layer, wherein the groove pattern is located directly above the through hole and has a size larger than that of the through hole;

[0012] Etching to form a trench, wherein the trench is located at an upper portion of the through hole and stops at the second etch stop layer, and an upper opening size of the trench is larger than a lower opening size;

[0013] Removing the bottom anti-reflection layer, the first etch stop layer, and the second etch stop layer remaining in the through hole to form a funnel structure with the groove formed on the upper portion of the through hole;

[0014] The funnel structure is filled with an interconnect metal layer.

[0015] Optionally, a top anti-reflection layer is further formed between the second dielectric layer and the first photoresist layer.

[0016] More optionally, the top anti-reflection layer includes a SiON layer, the bottom anti-reflection layer is an organic material layer including a cross-linked resin, a thermal acid generator, a surfactant and a solvent, the first etch stop layer and the second etch stop layer both include a silicon nitride layer, and the first dielectric layer and the second dielectric layer both include a silicon oxide layer.

[0017] Optionally, the process of performing etching to form a through hole includes:

[0018] Etching the top anti-reflection layer using CF4, CHF3 and O2 gases, and ensuring an overetching amount of 10%, so as to form an opening in the top anti-reflection layer to expose the second dielectric layer;

[0019] Etching the second dielectric layer using C4F8 and O2 gases and stopping at the second etch stop layer;

[0020] Etching the second etch stop layer using CF4, CHF3 and O2 gases, and ensuring an overetching amount of 10%, so as to form an opening in the second etch stop layer to expose the first dielectric layer;

[0021] The first dielectric layer is etched using C4F8 and O2 gases, and the etching stops at the first etch stop layer.

[0022] Optionally, etching back the bottom anti-reflection layer comprises the steps of:

[0023] Using 150sccm-200scmm of O2, the bottom anti-reflection layer located on the second dielectric layer is removed by ashing. During this process, the end point of the etching is controlled by an end point etching detection system.

[0024] 150sccm-200sccm of O2 is used for ashing and argon is used for bombardment. The bottom anti-reflection layer in the through hole is etched under a bias voltage of 100W. During this process, the etching time is controlled to control the bottom anti-reflection layer in the through hole to a preset height.

[0025] Optionally, the trench is formed by dry etching using C4F8 or C4F6 gas.

[0026] Optionally, the top width of the formed trench is 300 nm-500 nm, the trench depth is 800 nm, the width of the through hole is 150 nm-300 nm, and the depth of the through hole below the trench is 400 nm.

[0027] Optionally, in the process of forming the groove by dry etching, the flow rate of C4F8 gas is 22 sccm, the flow rate of oxygen gas is 13 sccm, the flow rate of argon gas is 350 sccm, and the angle of the formed groove is 83°-84°.

[0028] Optionally, before filling the interconnect metal layer in the funnel structure, the method further includes forming an adhesive layer on the surface of the funnel structure.

[0029] In an alternative solution, the interconnect metal layer is a tungsten layer, and the formed adhesion layer includes a TiN layer.

[0030] In another alternative, the interconnect metal layer is a copper layer, and the formed adhesion layer includes a TaN layer and / or a Ta layer.

[0031] As described above, the method for preparing a semiconductor structure of the present application has the following beneficial effects: the method for preparing a semiconductor structure provided by the present application divides the dielectric layer where the through hole is located into multiple layers by an etching barrier layer, so that etching can be performed step by step during the etching process, and the etching rate of each interval can be better controlled; after etching the through hole structure, the through hole is filled and etched back by utilizing the easy filling characteristic of the bottom anti-reflection layer, and then the photoresist layer is re-formed, and after development, a pattern of a groove located at the upper position of the through hole and having a size larger than the through hole size is formed, and the etching product (such as a polymer) generated during the etching process is accumulated on the side wall to obtain a structure with an inverted trapezoidal groove, and the etching stops on the etching barrier layer, and then the photoresist and the bottom anti-reflection layer are removed in situ, and finally the etching barrier layer is etched, and finally a funnel structure of an upper inverted trapezoidal groove + a lower through hole is formed. Under the same aspect ratio, the funnel structure is more convenient for filling the bonding layer and metal, which helps to improve the metal deposition capability, prevent the metal from generating voids and gaps during the deposition process, reduce the risk of defects during metal filling and grinding, and help improve the electrical performance of the device and enhance device reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A flow chart showing a method for preparing a semiconductor structure provided by the present application is shown.

[0033] Figure 2 Shown is a schematic diagram of a cross-sectional structure obtained after patterning the first photoresist layer.

[0034] Figure 3 Shown is a schematic diagram of the cross-sectional structure for forming a through hole.

[0035] Figure 4 Shown is a schematic diagram of the cross-sectional structure of the filled bottom anti-reflection layer.

[0036] Figure 5 It shows a schematic diagram of the cross-sectional structure after the bottom anti-reflection layer is etched back.

[0037] Figure 6 Shown is a schematic diagram of the cross-sectional structure for forming a groove pattern.

[0038] Figure 7 A graph showing the relationship between the trench angle and the oxygen flow rate during the trench etching process.

[0039] Figure 8 Shown is a schematic diagram of the cross-sectional structure of the formed groove.

[0040] Figure 9 Shown is a schematic diagram of the cross-sectional structure forming a funnel structure.

[0041] Figure 10 Shown is a schematic diagram of the cross-sectional structure of the formed adhesive layer.

[0042] Figure 11 Shown is a schematic diagram of the cross-sectional structure filled with interconnect metal.

[0043] Figure 12 Shown as Figure 11 Schematic diagram of the cross-sectional structure after surface flattening treatment.

[0044] Component number description

[0045] 11-substrate; 12-protective layer; 13-first etch stop layer; 14-first dielectric layer; 15-second etch stop layer; 16-second dielectric layer; 17-first photoresist layer; 18-via pattern; 19-via; 20-bottom anti-reflective layer; 21-second photoresist layer; 22-groove pattern; 23-groove; 24-top anti-reflective layer; 25-interconnect metal layer; 26-adhesion layer; 27-funnel structure DETAILED DESCRIPTION

[0046] The following describes the implementation methods of the present application through specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific implementation methods. The details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. For example, when describing the embodiments of the present application in detail, for the sake of convenience, the cross-sectional views showing the device structure will not be partially enlarged according to the general proportion, and the schematic views are only examples, which should not limit the scope of protection of the present application. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0047] For convenience, spatially relative terms such as "under," "below," "below," "below," "above," and "on" may be used herein to describe the relationship of one element or feature to other elements or features shown in the drawings. It will be understood that these spatially relative terms are intended to encompass orientations of the device in use or operation in addition to the orientation depicted in the drawings. Additionally, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0048] In the context of the present application, a structure described as a first feature being "above" a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features, such that the first and second features may not be in direct contact.

[0049] It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of this application. Therefore, the diagrams only show components relevant to this application and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be varied arbitrarily, and the component layout may be more complex. To minimize the illustrations, not all structures are labeled in the drawings.

[0050] One problem brought about by the increasing integration of semiconductor devices is that more and more structural layers are required, and the aspect ratio of the contact holes / through holes used to connect different conductive layers is getting larger and larger, making it increasingly difficult to fill the contact holes / through holes with metal. In addition, defects such as slits and / or voids are prone to occur during filling, resulting in device performance degradation or even complete failure. In the prior art, the dielectric layer that forms the contact holes / through holes is usually a single structural layer, and the etching method is single-step etching. Since the thickness of the single dielectric layer is relatively large, it is relatively difficult to maintain the consistency of the upper and lower opening sizes during the etching process, which exacerbates the difficulty of metal filling. In this regard, the inventors of the present application have proposed an improvement plan after long-term research.

[0051] The flowchart of the method for preparing the semiconductor structure provided in this application is as follows Figure 1 As shown, the following will be combined with the Figures 1 to 12 This method is described in detail.

[0052] like Figure 1 As shown, the present application provides a method for preparing a semiconductor structure, comprising the steps of:

[0053] First, step S1 is performed to provide a substrate 11; the substrate 11 can be a wafer of semiconductor materials such as silicon, germanium, silicon germanium, silicon on insulator, silicon carbide, etc. The substrate 11 is usually pre-prepared with circuit structures such as transistors, a bottom metal layer for electrically leading out the relevant circuit structure, and a protective layer 12 located on the surface of the substrate 11 for protecting the substrate 11. The protective layer 12 is, for example, a titanium layer and / or a titanium nitride layer. The protective layer 12 comprising titanium material can also act as an adhesion layer, which is beneficial for better adhesion of the structural layer in the subsequent process to the substrate 11 and reduces interlayer stress. After providing the substrate 11, the substrate 11 can be cleaned, for example, by cleaning with diluted hydrofluoric acid, and then dried to remove impurities on the surface of the substrate 11.

[0054] Next, step S2 is performed to sequentially form a first etch stop layer 13, a first dielectric layer 14, a second etch stop layer 15, and a second dielectric layer 16 on the surface of the substrate 11. Each layer can be formed, for example, using a chemical vapor deposition process. Thus, each layer can be formed continuously in the same chemical vapor deposition equipment, simplifying the fabrication process. In one example, the first etch stop layer 13 and the second etch stop layer 15 are made of the same material, such as silicon nitride, and their thicknesses can be the same or different, for example, 200 nm to 500 nm. The first dielectric layer 14 and the second dielectric layer 16 are made of the same material, such as silicon oxide. This not only simplifies the fabrication process, but also allows the same materials to be etched using the same etching method in subsequent etching processes, further simplifying the fabrication process and reducing production costs. The thicknesses of the first dielectric layer 14 and the second dielectric layer 16 can be the same or different. The key point is that the thicknesses of the first dielectric layer 14 and the second dielectric layer 16 can be set based on the size of the interconnect structure to be formed. In this embodiment, there is no limitation on their thicknesses. During the subsequent etching process, the first dielectric layer 14 and the second dielectric layer 16 are etched separately under the etch barrier effect of the first etch barrier layer 13 and the second etch barrier layer 15. This not only greatly reduces the etching difficulty but also allows for more flexible adjustment of the etching window to obtain the desired interconnect structure. The first dielectric layer 14 and the second dielectric layer 16 can be a single structural layer, such as a single silicon oxide layer, which has the advantage of simplifying the preparation process. In other alternatives, the first dielectric layer 14 and the second dielectric layer 16 may be made of different materials. The first dielectric layer 14 and the second dielectric layer 16 may also be a composite layer comprising multiple structural layers. For example, the first dielectric layer 14 may comprise two material layers with different etch selectivities, such as a pure silicon oxide layer or a low-doped (boron-doped and / or phosphorus-doped) silicon oxide layer at the top and a highly-doped (boron-doped and / or phosphorus-doped) silicon oxide layer (i.e., the doping concentration of the lower layer is greater than the doping concentration of the upper layer) silicon oxide layer at the bottom. During etching, an anisotropic dry etch is first performed, followed by an isotropic wet etch. This allows the highly-doped silicon oxide layer at the bottom to etch faster during the wet etch, thereby compensating for the relatively small amount of etching during the dry etch, ensuring that etched holes with uniform top and bottom opening sizes are formed in the first dielectric layer 14, ensuring that the bottom of the first dielectric layer 14 is fully open. If the second dielectric layer 16 is relatively thick, a similar composite structure with different top and bottom etch selectivities may also be used, which will not be described in detail. If the required aspect ratio of the interconnect structure is large, for example, greater than 10, a third etch stop layer and a third dielectric layer may be further included above the second dielectric layer 16 to reduce the height of each dielectric layer and prevent problems such as uneven film thickness and excessive interlayer stress during the deposition process due to excessive thickness of each dielectric layer, as well as excessive etching difficulty during the subsequent etching process.After forming the second dielectric layer 16, a top anti-reflection layer 24 can be further formed on the surface of the second dielectric layer 16 (i.e., the top anti-reflection layer 24 is located between the second dielectric layer 16 and the subsequent first photoresist layer 17). This helps control the surface reflectivity of the subsequent photoresist layer and improves the photolithography accuracy. The top anti-reflection layer 24 is preferably an inorganic material layer, such as a SiON layer. Not only can it be continuously formed in the same vapor deposition equipment as the aforementioned second dielectric layer 16 and other structural layers, it simplifies the preparation process. At the same time, the SiON layer and the second dielectric layer 16 made of silicon oxide have better adhesion and less stress, which helps improve the interface characteristics of the device. In addition, the inorganic top anti-reflection layer 24 can continue to be used as a protective mask in subsequent processes. In other optional solutions, the top anti-reflection layer 24 can also be made of carbon coating (SOC) material or other organic materials, which are not listed one by one.

[0055] After each structural layer is formed, step S3 is performed to form a first photoresist layer 17 on the surface of the second dielectric layer 16, and perform a patterning process to define a through-hole pattern 18 in the first photoresist layer 17. For example, the first photoresist layer 17 is formed by, but not limited to, a spin coating method, with a thickness of, for example, 5000nm-7000nm, and then exposed and developed to form the through-hole pattern 18. The resulting structure is as shown in FIG. Figure 2 shown.

[0056] Next, step S4 is performed, in which the first photoresist layer 17 with the through-hole pattern 18 is etched downward to form a through-hole 19. The through-hole 19 sequentially penetrates the second dielectric layer 16, the second etch stop layer 15 and the first dielectric layer 14 downward until the first etch stop layer 13 is exposed, i.e., the etching stops at the first etch stop layer 13. The structure obtained after this step is as follows: Figure 3As shown. The specific process of this step varies depending on the materials of the second dielectric layer 16, the second etch stop layer 15 and the first dielectric layer 14. In a preferred embodiment, the first dielectric layer 14 and the second dielectric layer 16 are both silicon oxide layers, and the second etch stop layer 15 and the first etch stop layer 13 are silicon nitride layers (silicon oxide and silicon nitride are both very commonly used materials with very mature preparation processes, which helps to reduce preparation costs). Then, a preferred etching process of this step confirmed by a large number of experiments by the inventors is: first, CF4, CHF3 and O2 gases are used to etch the top anti-reflection layer 24, and an over-etching amount of 10% is ensured to form a second dielectric layer in the top anti-reflection layer 24. The process then proceeds to form an opening in the first dielectric layer 16; then, C4F8 and O2 gases are used to etch the second dielectric layer 16, stopping at the second etch stop layer 15; next, CF4, CHF3, and O2 gases are used to etch the second etch stop layer 15, ensuring a 10% overetch, to form an opening in the second etch stop layer 15 that exposes the first dielectric layer 14. The first dielectric layer 14 is then etched using C4F8 and O2 gases, stopping at the first etch stop layer 13. The remaining first photoresist layer 17 can then be removed in situ within the same etching chamber. In other words, the etching processes in this step are all performed within the same etching equipment, and the etching process using the above parameters ensures that the bottom of the through-hole is fully opened.

[0057] After forming the through hole 19, step S5 is performed to fill the through hole 19 with a bottom anti-reflection layer 20 (BRAC). The bottom anti-reflection layer 20 is preferably an organic material layer, for example, an organic material layer including a cross-linked resin, a thermal acid generator, a surfactant, and a solvent. It can be formed in the through hole 19 and on the surface of the second dielectric layer 16 (if a top anti-reflection layer 24 is formed, it extends to the surface of the top anti-reflection layer 24) by using a process including but not limited to spin coating. The structure obtained after this step is as follows Figure 4 shown.

[0058] Next, step S6 is performed to etch back the bottom anti-reflection layer 20 so that the height of the bottom anti-reflection layer 20 is lower than the depth of the through hole 19. The structure obtained after this step is as follows: Figure 5As shown, this step can be performed on the same etching equipment as the etching in step S4. In the case where the bottom anti-reflection layer 20 adopts the aforementioned organic material layer, the preferred back etching step includes the following process: using 150sccm-200scmm of O2 on the etching machine, the bottom anti-reflection layer 20 located on the second dielectric layer 16 (also on the top anti-reflection layer 24) is removed by ashing. During this process, the end point etching detection system is used to control the etching end point, and then 150sccm-200sccm of O2 is used for ashing and argon gas is used for bombardment. The bottom anti-reflection layer 20 in the through hole 19 is etched under the action of a bias voltage of 100W to partially remove it. During this process, the etching time is controlled to control the bottom anti-reflection layer 20 in the through hole 19 to a preset height. The height after etching back affects the morphology of the subsequently etched trench 23. Therefore, the specific height can be defined based on the morphology of the trench 23. If the height of the bottom anti-reflection layer 20 is too low, the bottom anti-reflection layer 20 will be consumed during the subsequent trench 23 etching process, resulting in the consumption of the first etch stop layer 13 and the premature formation of the through hole 19 structure. Therefore, the height after etching back should not be too low or too high. For example, in one example, the top of the bottom anti-reflection layer 20 after etching back is slightly higher than the second etch stop layer 15, for example, located at 1 / 4 the height of the second dielectric layer 16.

[0059] Then, step S7 is performed to form a second photoresist layer 21 covering the through hole 19 and the second dielectric layer 16, and a patterning process is performed to form a groove pattern 22 in the second photoresist layer 21. The groove pattern 22 is located directly above the through hole 19, and the size of the groove pattern 22 is larger than the size of the through hole 19, so that the through hole is completely exposed in the groove pattern. The process of forming the second photoresist layer 21 and the patterning process will not be repeated. The structure obtained after this step is as follows: Figure 6 shown.

[0060] Next, step S8 is performed, in which the second photoresist layer 21 with the groove pattern 22 is etched to form a groove 23. The groove 23 is located at the upper part of the through hole 19 and stops at the second etch stop layer 15. The upper opening size of the groove 23 is larger than the lower opening size. Preferably, the method for forming the groove 23 is dry etching, so this step can be performed in the etching equipment of step S6. This step of etching preferably uses a high carbon-fluorine ratio gas, for example, a gas including C4F8 or C4F6 for dry etching. A high carbon-fluorine ratio gas and O2 are used as etching gases and stop on the second etch stop layer 15. The high carbon-fluorine ratio gas, such as C4F8 or C4F6 gas, is used to form a polymer. These polymers accumulate on the side walls of the groove 23 and will prevent the side walls from being further etched. O2 can remove part of the polymer to prevent excessive accumulation of the polymer from causing the etching to stop. In addition, by adjusting O2, for example, according to Figure 7By adjusting the relationship diagram of oxygen flow rate and groove 23 angle shown in FIG, a series of inverted trapezoidal grooves 23 with an upper opening size larger than a lower opening size can be obtained, as shown in FIG. Figure 8 The structure shown. It should be noted that, when the carbon fluorine gas is fixed to C4F8 and the pressure and other related process conditions remain unchanged, the angle of the groove 23 can be controlled by adjusting the oxygen flow rate. Within a certain range, as the O2 flow rate increases, the polymer produced during the etching process will be fully removed, so that the angle of the groove 23 gradually tends to 90°. However, when the increase reaches a certain amount, due to the constant amount of polymer produced, increasing O2 will not have much effect; when the O2 flow rate is too small, the polymer cannot be removed in time during the etching process, resulting in excessive polymer accumulation and eventually leading to etching cessation, which will cause electrical failure. Therefore, the gas flow rate is very critical in this step. The inventors have found through extensive experiments that during the process of forming the trench 23 by dry etching, the flow rate of C4F8 gas is preferably 22 sccm, the flow rate of oxygen is 13 sccm, and the flow rate of argon is 350 sccm. In this case, when the angle of the formed trench 23 is 83°-84° (an angle that is too large is not conducive to filling, and a too small angle will cause the trench 23 to occupy too large a size laterally, which is not conducive to device miniaturization), the structure is optimal, most conducive to metal filling, and is also beneficial to subsequent process steps, for example, avoiding short circuits in subsequent processes caused by excessively wide interconnect structures. This angle is also relatively easy to achieve in terms of process. The dimensions of the formed trench 23 are preferably 300nm-500nm wide at the top and 800nm deep at the trench 23, while the width of the through hole 19 is 150nm-300nm and the depth of the through hole 19 below the trench 23 is 400nm.

[0061] After the etching is completed, step S9 is performed to remove the bottom anti-reflection layer 20, the first etch stop layer 13, and the second etch stop layer 15 remaining in the through hole 19, forming a funnel structure 27 with the groove 23 formed on the upper part of the through hole 19, that is, a structure in which the upper opening size of the through hole 19 is larger than the lower opening size. This step is preferably performed directly in situ in the machine. First, O2 is used to remove the second photoresist layer 21 remaining on the surface. Then, oxygen and argon are used under the action of bias to remove the bottom anti-reflection layer 20 remaining in the through hole 19. Then, the first etch stop layer 13 and the second etch stop layer 15 are etched. The resulting structure is as shown in FIG. Figure 9 shown.

[0062] Then, step S10 is performed to fill the funnel structure 27 with an interconnection metal layer 25 . The interconnection metal layer 25 will be electrically connected to electrical structures such as the bottom metal layer in the substrate 11 .

[0063] To ensure good filling of the interconnection metal layer 25, before filling the interconnection metal layer 25 in the funnel structure 27, an adhesion layer 26 can be formed on the surface of the funnel structure 27 (such as its sidewalls and bottom surface). The adhesion layer 26 can be formed by a chemical vapor deposition process, and its material matches the interconnection metal layer 25. For example, if the interconnection metal layer 25 is a tungsten layer, the adhesion layer 26 formed includes a TiN layer; if the interconnection metal layer 25 is a copper layer, the adhesion layer 26 formed includes a TaN layer and / or a Ta layer. The structure obtained after forming the adhesion layer 26 is as follows: Figure 10 Then, metal can be deposited in the funnel structure 27 and on the second dielectric layer 16 by chemical vapor deposition, physical vapor deposition or electroplating. For example, chemical vapor deposition is first used to form a metal seed layer on the surface of the adhesive layer 26, and then electroplating is used to fill the entire funnel structure 27 with metal, so as to obtain the following. Figure 11 The structure is then subjected to surface planarization treatment, such as chemical mechanical polishing (CMP) to remove the metal material located above the second dielectric layer 16, and only the metal located in the funnel structure 27 is retained as the interconnect metal layer 25. The final structure is as follows: Figure 12 shown.

[0064] The present application provides a method for preparing a semiconductor structure, in which the dielectric layer where the through hole is located is separated into multiple layers by an etching barrier layer, so that etching can be performed step by step during the etching process, and the etching rate of each interval can be better controlled. After etching the through hole structure, the through hole is filled and etched back by utilizing the easy-filling characteristic of the bottom anti-reflection layer, and then a photoresist layer is re-formed. After development, a pattern of a groove located above the through hole and having a size larger than the through hole is formed. The etching product (such as a polymer) generated during the etching process is accumulated on the side wall to obtain a structure with an inverted trapezoidal groove, and the etching stops on the etching barrier layer. Thereafter, the photoresist and the bottom anti-reflection layer are removed in situ, and finally the etching barrier layer is etched again, ultimately forming a funnel structure of an upper inverted trapezoidal groove (the upper opening size is larger than the lower opening size) + a lower through hole. Under the same aspect ratio, the funnel structure is more convenient for filling the bonding layer and metal, which helps to improve the metal deposition capability, prevent the metal from generating voids and gaps during the deposition process, reduce the risk of defects during metal filling and grinding, and help improve the electrical performance of the device and enhance device reliability.

[0065] Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial utilization value.

[0066] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical concepts disclosed in this application shall be covered by the claims of this application.

Claims

1. A method for preparing a semiconductor structure, characterized in that: Including steps: providing a substrate (11); forming a first etch stop layer (13), a first dielectric layer (14), a second etch stop layer (15) and a second dielectric layer (16) in sequence on the surface of the substrate (11); forming a first photoresist layer (17) on the surface of the second dielectric layer (14), and performing a patterning process to define a through-hole pattern (18) in the first photoresist layer (17); Etching is performed to form a through hole (19), wherein the through hole (19) sequentially penetrates the second dielectric layer (16), the second etching stop layer (15), and the first dielectric layer (14) downward until the first etching stop layer (13) is exposed; Filling the through hole (19) with a bottom anti-reflection layer (20); Carving back the bottom anti-reflection layer (22) so that the height of the bottom anti-reflection layer (20) is lower than the depth of the through hole (19); forming a second photoresist layer (21) covering the through hole (19) and the second dielectric layer (16), and performing a patterning process to form a groove pattern (22) in the second photoresist layer (21), wherein the groove pattern (22) is located directly above the through hole (19), and the size of the groove pattern is larger than the size of the through hole; Etching is performed to form a groove (23), wherein the groove (23) is located above the through hole (19) and stops at the second etching stopper layer (15), and the upper opening size of the groove (23) is larger than the lower opening size; Removing the bottom anti-reflection layer (20), the first etching stopper layer (13), and the second etching stopper layer (15) remaining in the through hole (19) to form a funnel structure (27) with the groove (23) formed on the upper portion of the through hole (19); An interconnection metal layer (25) is filled in the funnel structure.

2. The method for preparing a semiconductor structure according to claim 1, wherein: A top anti-reflection layer (24) is also formed between the second dielectric layer (16) and the first photoresist layer (17).

3. The method for preparing a semiconductor structure according to claim 2, wherein: The top anti-reflection layer (24) comprises a SiON layer, the bottom anti-reflection layer (20) is an organic material layer comprising a cross-linked resin, a thermal acid generator, a surfactant, and a solvent, the first etch stop layer (13) and the second etch stop layer (15) both comprise silicon nitride layers, and the first dielectric layer (14) and the second dielectric layer (16) both comprise silicon oxide layers.

4. The method for preparing a semiconductor structure according to claim 3, wherein: The process of etching to form the through hole (19) includes: Etching the top anti-reflection layer (24) using CF4, CHF3 and O2 gases, and ensuring an over-etching amount of 10%, so as to form an opening in the top anti-reflection layer (24) to expose the second dielectric layer (16); Etching the second dielectric layer (16) using C4F8 and O2 gases, and stopping at the second etching stop layer (15); The second etch stop layer (15) is etched using CF4, CHF3 and O2 gases, and an over-etching amount of 10% is ensured, so as to form an opening in the second etch stop layer (15) that exposes the first dielectric layer (14); The first dielectric layer (14) is etched using C4F8 and O2 gases, and the etching stops at the first etching stop layer (13).

5. The method for preparing a semiconductor structure according to claim 3, wherein: Carving back the bottom anti-reflection layer (20) comprises the following steps: Using 150 sccm-200 scmm of O2, the bottom anti-reflection layer (20) located on the second dielectric layer (16) is removed by ashing, and an end point etching detection system is used to control the etching end point during the process; 150 sccm-200 sccm of O2 is used for ashing and argon gas is used for bombardment, and the bottom anti-reflection layer (20) in the through hole is etched under a bias voltage of 100 W. During this process, the bottom anti-reflection layer (20) in the through hole is controlled to a preset height by controlling the etching time.

6. The method for preparing a semiconductor structure according to claim 1, wherein: The method for forming the groove (23) is to adopt dry etching including C4F8 or C4F6 gas.

7. The method for preparing a semiconductor structure according to claim 6, wherein: The top width of the formed groove (23) is 300nm-500nm, the groove depth is 800nm, the width of the through hole is 150nm-300nm, and the depth of the through hole located below the groove is 400nm.

8. The method for preparing a semiconductor structure according to claim 6, wherein: In the process of forming the groove (23) by dry etching, the flow rate of C4F8 gas is 22 sccm, the flow rate of oxygen gas is 13 sccm, and the flow rate of argon gas is 350 sccm, and the angle of the formed groove is 83°-84°.

9. The method for preparing a semiconductor structure according to claim 1, wherein: Before the interconnection metal layer (25) is filled in the funnel structure (27), the method further includes forming an adhesive layer (26) on the surface of the funnel structure (27).

10. The method for preparing a semiconductor structure according to claim 9, wherein: The interconnection metal layer (25) is a tungsten layer, and the formed adhesion layer (26) includes a TiN layer; or the interconnection metal layer (25) is a copper layer, and the formed adhesion layer (26) includes a TaN layer and / or a Ta layer.

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