Semiconductor device, manufacturing method thereof, power conversion circuit and vehicle

Abstract

This application discloses a semiconductor device, its fabrication method, a power conversion circuit, and a vehicle. The semiconductor device introduces a channel region at the bottom of the trench, which, in conjunction with a gate splitting structure, provides a low-barrier path for electrons to travel from the epitaxial layer to the second source region. This results in a lower third-quadrant turn-on voltage, suppressing the turn-on of the body diode and solving the bipolar degradation problem. Furthermore, the low-barrier path exhibits excellent reverse recovery characteristics, and the reduced reverse recovery charge significantly lowers the device's turn-on loss.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device, its fabrication method, a power conversion circuit, and a vehicle. Background Technology

[0002] Silicon carbide (SiC) offers advantages over silicon (Si) such as a wider bandgap, higher critical breakdown electric field, higher thermal conductivity, and higher electron saturation drift velocity. Metal-oxide-semiconductor field-effect transistors (MOSFETs) made from SiC exhibit higher breakdown voltage and lower on-state voltage drop compared to insulated-gate bipolar transistors (IGBTs) made from Si. Furthermore, the unipolar conductivity of SiC MOSFETs results in faster switching speeds, lower conduction losses, and lower switching losses compared to Si IGBTs. Therefore, SiC MOSFETs have already replaced Si IGBTs in some applications, such as automotive microcontroller units (MCUs) and on-board battery chargers (OBCs).

[0003] As a core component of power systems, SiC MOSFETs require not only excellent first-quadrant characteristics but also superior third-quadrant performance. Although SiC MOSFETs possess an internal parasitic body diode that allows freewheeling in the third quadrant, the turn-on voltage is as high as 2V–3V, and the body diode introduces significant losses during conduction. Furthermore, due to the presence of basal plane dislocations (BPDs) in the silicon carbide epitaxial layer, the energy released by electron-hole recombination during body diode conduction causes stacking faults to propagate at the BPDs, resulting in bipolar degradation. This leads to a decline in the electrical performance of the SiC MOSFET, such as increased on-resistance and increased leakage current in the off-state, posing a serious challenge to the overall system performance and reliability. Summary of the Invention

[0004] This application provides a semiconductor device, its fabrication method, a power conversion circuit, and a vehicle for reducing the turn-on voltage of the device when operating in the third quadrant and solving the bipolar degradation problem.

[0005] In a first aspect, this application provides a semiconductor device, comprising: a semiconductor substrate, an epitaxial layer disposed on the semiconductor substrate, a trench disposed within the epitaxial layer, a gate electrode disposed within the trench through a gate insulating film, a source electrode disposed on the epitaxial layer, and a drain electrode disposed on the side of the semiconductor substrate away from the epitaxial layer. The trench has a first sidewall and a second sidewall disposed opposite to each other. Exemplarily, the epitaxial layer may include: a first source region disposed outside the trench and in contact with the first sidewall; a well region located below the first source region; a shielding region disposed outside the trench, enclosing the second sidewall of the trench and extending to the bottom of the trench; a second source region disposed between the second sidewall of the trench and the shielding region; and a channel region disposed between the bottom of the trench and the shielding region and in contact with the second source region.

[0006] In this application, the semiconductor substrate can be a single-crystal SiC substrate doped with pentavalent elements, and the epitaxial layer can be SiC material doped with corresponding impurities grown epitaxially. Specifically, the semiconductor substrate and the epitaxial layer are mainly doped with N-type impurities, such as nitrogen (N), phosphorus (P), or arsenic (As). For example, the doping concentration of the semiconductor substrate is generally greater than the doping concentration of the epitaxial layer.

[0007] In this application, the first source region, the second source region, and the channel region can be formed by doping the epitaxial layer using an ion implantation process. Furthermore, the dopants in the first source region, the second source region, and the channel region are primarily N-type impurities, such as nitrogen (N), phosphorus (P), or arsenic (As). For example, the doping concentration of the channel region is generally lower than that of the first and second source regions, while the doping concentrations of the first and second source regions are generally similar.

[0008] In this application, the well region and the shielding region can be formed by doping the epitaxial layer using an ion implantation process. Furthermore, the dopants in the well region and the shielding region are primarily P-type impurities, such as boron (B), aluminum (Al), or gallium (Ga). For example, the doping concentration in the well region is generally lower than that in the shielding region.

[0009] In this application, the gate may include a first gate and a second gate, which are enclosed by a gate insulating film, i.e., the first gate and the second gate are insulated from each other. The channel region may contact the gate insulating film enclosing the second gate, but the channel region and the gate insulating film enclosing the first gate do not contact each other.

[0010] Due to the presence of the second gate and the channel region at the bottom of the trench, a low-barrier path for electrons exists at the interface between the gate insulating film encapsulating the second gate and the channel region. This low-barrier path allows electrons to travel from the epitaxial layer → channel region → second source region. When the device is forward-biased or off, this low-barrier path prevents electrons from the second source region from entering the epitaxial layer through the channel region, ensuring the device's blocking capability. When the device operates in the third quadrant, the negative drain bias increases the electron energy in the epitaxial layer, correspondingly lowering the barrier height. When the electron energy exceeds the barrier, it preferentially conducts over the body diode from the epitaxial layer to the well region, suppressing the body diode's turn-on. Furthermore, when the low-barrier path is on, only electrons participate in conduction, resulting in a lower third-quadrant turn-on voltage and avoiding bipolar degradation. This low-barrier path also exhibits excellent reverse recovery characteristics, and the reduced reverse recovery charge significantly lowers the device's turn-on loss. Specifically, the first gate acts as a gate, so the first gate can be regarded as a real gate, and the second gate is a virtual gate. Splitting the gate into a real gate and a virtual gate can also significantly reduce the gate-drain capacitance and improve the high-frequency performance of the device.

[0011] In some possible implementations of this application, the gate can be a split structure, that is, within the trench, the first gate and the second gate can be stacked, with the second gate located at the bottom of the trench and the first gate located above the second gate, separated by a gate insulating film. Placing the second gate at the bottom of the trench facilitates contact between the channel region and the gate insulating film surrounding the second gate, while ensuring that the channel region does not contact the gate insulating film surrounding the first gate.

[0012] In some possible implementations of this application, the gate can also be a split structure, with the first gate and the second gate arranged side by side in the trench, the first gate being disposed adjacent to the first sidewall and the second gate adjacent to the second sidewall. The second gate can also be in direct contact with the source. Disposing the second gate adjacent to the second sidewall of the trench facilitates contact between the channel region and the gate insulating film encapsulating the second gate. Disposing the first gate adjacent to the first sidewall of the trench ensures that the channel region and the gate insulating film encapsulating the first gate do not contact each other.

[0013] This application does not limit the material of the gate. For example, the gate material can be polycrystalline silicon or other materials with good electrical conductivity, such as metals (e.g., W, Al, Ti, Cu, Mo, or Pt).

[0014] In some possible implementations of this application, the semiconductor device may further include an interlayer dielectric layer covering the epitaxial layer on the side away from the semiconductor substrate. Furthermore, the interlayer dielectric layer may have contact holes, the orthographic projection of which onto the semiconductor substrate does not overlap with the orthographic projection of the first gate onto the semiconductor substrate, and the contact holes expose a first source region, a second source region, and a shielding region, so that the source electrode can contact the shielding region, the first source region, and the second source region respectively through the contact holes, achieving the effect of ohmic contact between the source electrode and the shielding region, the first source region, and the second source region respectively.

[0015] This application does not limit the material used to form the interlayer dielectric layer. For example, the material used to form the interlayer dielectric layer can be a dielectric material, including but not limited to silicon dioxide (SiO2), silicon oxynitride (SiNO), silicon oxycarbide (SiCO), silicon nitride (SiNx), etc.

[0016] This application does not limit the materials used to form the source and drain 13. For example, the materials used to form the source and drain can be metallic materials. Exemplarily, the metallic materials may include W, Al, Ti, Cu, Mo, or Pt, etc.

[0017] In some possible implementations of this application, the epitaxial layer may include a drift layer disposed on a semiconductor substrate and a current spreading layer (CSL) disposed on the drift layer. The current spreading layer reduces the diffusion resistance of the current at the upper end of the drift layer. Trench, first source region, second source region, well region, channel region, and shielding region are generally disposed within the current spreading layer. The current spreading layer and drift layer are primarily doped with N-type impurities, such as nitrogen (N), phosphorus (P), or arsenic (As). Exemplarily, the doping concentration of the semiconductor substrate is generally greater than the doping concentration of the current spreading layer, and the doping concentration of the current spreading layer is generally greater than the doping concentration of the drift layer. Alternatively, in other embodiments of this application, the epitaxial layer may only have a drift layer, i.e., no current spreading layer.

[0018] In some possible implementations of this application, the channel region may be located only at the bottom of the trench, meaning the orthographic projection of the channel region onto the semiconductor substrate may be within the orthographic projection range of the trench onto the semiconductor substrate. The second source region extends from the second sidewall of the trench to the bottom of the trench and contacts the channel region. It is worth noting that, to ensure that the channel region only contacts the gate insulating film surrounding the second gate, and that the channel region does not contact the gate insulating film surrounding the first gate, when the gate has a split structure, the orthographic projection of the channel region onto the semiconductor substrate should be within the orthographic projection range of the second gate onto the semiconductor substrate, and the orthographic projections of the channel region and the first gate onto the semiconductor substrate should not overlap.

[0019] In some possible implementations of this application, the channel region may also extend from the bottom of the trench to the second sidewall of the trench to contact the second source region located on the second sidewall of the trench. It is worth noting that, to ensure that the channel region only contacts the gate insulating film surrounding the second gate, and that the channel region does not contact the gate insulating film surrounding the first gate, when the gate has an upper and lower split structure, the portion of the channel region on the second sidewall of the trench cannot contact the gate insulating film surrounding the first gate. The upper portion of the second sidewall of the second source region contacts the gate insulating film surrounding the first gate, and the lower portion of the second sidewall of the second source region contacts the gate insulating film surrounding the second gate.

[0020] In some possible implementations of this application, in addition to the trench region extending from the bottom of the trench to the second sidewall of the trench, the second source region may also extend from the second sidewall of the trench to the bottom of the trench and contact the trench region.

[0021] The semiconductor device provided in this application introduces a channel region at the bottom of the trench. Combined with a gate splitting structure, this provides a low-barrier path for electrons to travel from the epitaxial layer to the second source region. This results in a lower third-quadrant turn-on voltage, suppressing the turn-on of the body diode and solving the bipolar degradation problem. Furthermore, the low-barrier path exhibits excellent reverse recovery characteristics, and the reduced reverse recovery charge significantly lowers the device's turn-on loss.

[0022] Secondly, embodiments of this application also provide a method for fabricating a semiconductor device, which may include the following steps: epitaxially growing an epitaxial layer on a semiconductor substrate, and forming a well region, a first source region, and a shielding region in the epitaxial layer; etching the epitaxial layer to form a trench in the epitaxial layer, the trench having a first sidewall and a second sidewall disposed opposite to each other, the well region, the first source region, and the shielding region all being located outside the trench, the well region and the first source region both contacting the first sidewall, and the well region being located below the first source region, and the shielding region contacting the second sidewall; forming a second source region on the second sidewall of the trench, and forming a channel region at the bottom of the trench, the channel region contacting the second source region; forming a gate insulating film in the trench, and forming a gate in the trench where the gate insulating film is formed, the gate including a first gate and a second gate, the first gate and the second gate being wrapped by the gate insulating film; forming a source on the epitaxial layer, the source contacting the shielding region, the first source region, and the second source region respectively; and forming a drain on the side of the semiconductor substrate away from the epitaxial layer.

[0023] In some possible implementations, the fabrication method may further include: forming an interlayer dielectric layer covering the entire epitaxial layer on the epitaxial layer; etching the interlayer dielectric layer to form a contact hole, the contact hole exposing a first source region, a second source region and a shielding region, and the orthogonal projection of the contact hole onto the semiconductor substrate and the orthogonal projection of the first gate onto the semiconductor substrate do not overlap, and the source electrode contacts the shielding region, the first source region and the second source region through the contact hole respectively.

[0024] In some possible implementations, the epitaxial growth of an epitaxial layer on a semiconductor substrate in order to form an epitaxial layer may include the following steps:

[0025] First, an epitaxial process can be used to epitaxially grow SiC material doped with N-type impurities on an N-type SiC semiconductor substrate to form a drift layer.

[0026] Subsequently, SiC materials with different concentrations of N-type impurities are epitaxially grown on the drift layer to form a current spreading layer.

[0027] This application does not specify the exact thickness of the drift layer and the current spreading layer. In practical applications, the specific thickness of the drift layer and the current spreading layer can be determined according to the requirements of the actual application environment.

[0028] In some possible implementations, to form a well region, a first source region, and a shielding region in the epitaxial layer, the following steps may be included:

[0029] First, an ion implantation process is used to dop the current spread layer with P-type impurities to form a well region.

[0030] Subsequently, an ion implantation process was used to dope the well region with N-type impurities to form the first source region, so that the retained well region is located below the first source region.

[0031] Subsequently, an ion implantation process was used to dope the current spread layer with P-type impurities to form a shielding region.

[0032] In this embodiment of the application, after the ion implantation process, a trap region, a first source region, and a shielding region are formed in the current spreading layer.

[0033] In some possible implementations, forming trenches in the epitaxial layer may include the following steps:

[0034] First, a trench mask (which can be a photoresist mask or a hard mask) is formed on the current spread layer. This trench mask covers the areas of the current spread layer where trenches are not needed, while exposing the areas where trenches are required. Then, a suitable etching process is selected from plasma etching, ion sputtering etching, and reactive ion etching to etch the areas of the current spread layer not covered by the trench mask, forming trenches in the current spread layer. The trench has a first sidewall and a second sidewall positioned opposite each other. The well region and the first source region are in contact with the first sidewall, and the shielding region is in contact with the second sidewall.

[0035] In some possible implementations, in order to form a second source region on the second sidewall of the trench and a channel region at the bottom of the trench, the following steps may be included:

[0036] First, an N-type impurity doping process is used to dope the surface of the second sidewall of the trench with tilted ion implantation to form a second source region.

[0037] Subsequently, a vertical ion implantation process was used to dope the bottom of the trench with N-type impurities, forming a channel region that contacts the second source region.

[0038] In some possible implementations, forming a gate insulating film within the trench may include the following steps:

[0039] First, the semiconductor device can be activated by annealing and then cleaned.

[0040] Next, a high-temperature (>1150 degrees) oxidation process can be used to oxidize the surface of the trench, so that a grid insulating film is formed on the surface of the trench.

[0041] In some possible implementations, in order to form a gate with an upper and lower split structure in a trench in which a gate insulating film is formed, the following steps may be included:

[0042] First, a polysilicon material is deposited on the entire current spreading layer with trenches using a deposition process, and the polysilicon material fills the trenches. After the trenches are filled with polysilicon material, a polysilicon film is then applied to the entire current spreading layer. Next, a suitable etching process is selected from plasma etching, ion sputtering etching, and reactive ion etching to etch the polysilicon material region to form the second gate.

[0043] Subsequently, a low-temperature (<900 degrees) oxidation process can be used to oxidize a portion of the polysilicon material on the surface of the second gate, so that a gate insulating film is formed on the surface of the second gate, ensuring that the first gate and the second gate are wrapped by the gate insulating film.

[0044] Next, a deposition process is used again to deposit polysilicon material on the entire current spreading layer where the second gate is formed, and the polysilicon material fills the trenches. After the trenches are filled with polysilicon material, a polysilicon film is then applied to the entire current spreading layer. Then, a suitable etching process is selected from plasma etching, ion sputtering etching, and reactive ion etching to etch the polysilicon material region again to form the first gate.

[0045] In some possible implementations, in order to form a gate with a left-right split structure in a trench in which a gate insulating film is formed, the following steps may be included:

[0046] First, a polysilicon material is deposited on the entire current spreading layer with trenches using a deposition process, and the polysilicon material fills the trenches. After the trenches are filled with polysilicon material, a polysilicon film is then applied to the entire current spreading layer. Next, a suitable etching process is selected from plasma etching, ion sputtering etching, and reactive ion etching to etch the polysilicon material region, thereby forming a first gate on one side of the first sidewall.

[0047] Subsequently, a low-temperature (<900 degrees) oxidation process can be used to oxidize a portion of the polysilicon material on the surface of the first gate, so that a gate insulating film is formed on the surface of the first gate, ensuring that the first gate and the second gate are wrapped by the gate insulating film.

[0048] Next, a deposition process is used again to deposit polysilicon material on the entire current spreading layer where the first gate is formed, and the polysilicon material fills the trenches. After the trenches are filled with polysilicon material, a polysilicon film layer is then applied to the entire current spreading layer. Then, a suitable etching process is selected from plasma etching, ion sputtering etching, and reactive ion etching to etch the polysilicon material region again, thereby forming the second gate on one side of the second sidewall.

[0049] In some possible implementations, in order to form a gate with a left-right split structure in a trench in which a gate insulating film is formed, the following steps may be included:

[0050] First, a deposition process is used to deposit polysilicon material onto the entire current spreading layer with trenches, and the polysilicon material fills the trenches. After the trenches are filled with polysilicon material, a polysilicon film layer is then applied to the entire current spreading layer. Next, a suitable etching process is selected from plasma etching, ion sputtering etching, and reactive ion etching to etch the polysilicon material region, thereby forming a second gate on one side of the second sidewall.

[0051] Subsequently, a low-temperature (<900 degrees) oxidation process can be used to oxidize a portion of the polysilicon material on the surface of the second gate, so that a gate insulating film is formed on the surface of the second gate, ensuring that the first gate and the second gate are wrapped by the gate insulating film.

[0052] Subsequently, a deposition process is used again to deposit polysilicon material on the entire current spreading layer where the second gate is formed, and the polysilicon material fills the trenches. After the trenches are filled with polysilicon material, a polysilicon film layer is then applied to the entire current spreading layer. Next, a suitable etching process is selected from plasma etching, ion sputtering etching, and reactive ion etching to etch the polysilicon material region again, thereby forming the first gate on one side of the first sidewall.

[0053] In some possible implementations, in order to form a source on the epitaxial layer and a drain on the side of the semiconductor substrate away from the epitaxial layer, the following steps may be included:

[0054] First, a deposition process can be used to deposit an interlayer dielectric layer on the entire current spread layer, ensuring that the interlayer dielectric layer covers the entire current spread layer.

[0055] Next, a contact hole mask (which can be a photoresist mask or a hard mask) is formed on the current spreading layer. This contact hole mask covers the areas where contact holes do not need to be formed, while exposing the areas where contact holes need to be formed. Then, a suitable etching process is selected from etching processes such as plasma etching, ion sputtering etching, and reactive ion etching to etch the areas of the interlayer dielectric layer not covered by the contact hole mask, exposing the shielding area, the first source region, and the second source region.

[0056] Subsequently, a deposition process is used to deposit metallic material on the interlayer dielectric layer to form the source electrode. The contact holes are then filled with metallic material, allowing the source electrode to contact the shielding region, the first source region, and the second source region, respectively, through the metallic material filling the contact holes.

[0057] For example, a deposition process can be used to deposit metal material on the side of the semiconductor substrate away from the epitaxial layer before forming the source to form the drain. Alternatively, a deposition process can be used to deposit metal material on the side of the semiconductor substrate away from the epitaxial layer after forming the source to form the drain.

[0058] This application does not limit the materials used for the source and drain electrodes. For example, the materials forming the source and drain electrodes can be metallic materials. Exemplarily, the metallic material may include W, Al, Ti, Cu, Mo, or Pt.

[0059] Thirdly, embodiments of this application also provide a power conversion circuit, which can be an AC-to-DC conversion circuit and / or a DC-to-DC conversion circuit. The power conversion circuit may include a circuit board and one or more semiconductor devices, with the semiconductor devices connected to the circuit board. The semiconductor devices may be those used in the first aspect or various possible designs of the first aspect, or those fabricated using the second aspect or various possible designs of the second aspect. Because the aforementioned semiconductor devices have better performance, the power conversion circuit including these semiconductor devices also has better performance. Furthermore, the principle by which this power conversion circuit solves the problem is similar to the principle by which the aforementioned semiconductor devices can solve the problem; therefore, the technical effects of this power conversion circuit can be referred to the technical effects of the aforementioned semiconductor devices, and repetitions will not be repeated.

[0060] Fourthly, embodiments of this application also provide a vehicle, which may include a battery, a power conversion circuit, and a motor connected in sequence. The power conversion circuit may be as described in the third aspect or various possible designs of the third aspect. Because the power conversion circuit described above has good performance, the vehicle including the power conversion circuit also has good circuit performance. Furthermore, the principle by which this vehicle solves the problem is similar to the principle by which the aforementioned power conversion circuit solves the problem; therefore, the technical effects of this vehicle can be referred to the technical effects of the aforementioned power conversion circuit, and repetitions will not be repeated. Attached Figure Description

[0061] Figure 1 This is a schematic diagram of the structure of an electric vehicle provided in one embodiment of this application;

[0062] Figure 2 This is a schematic diagram of the structure of an electronic device provided in one embodiment of this application;

[0063] Figure 3 This is a schematic diagram of the structure of a semiconductor device provided in one embodiment of this application;

[0064] Figure 4 This is a schematic diagram of the structure of a semiconductor device provided in another embodiment of this application;

[0065] Figure 5 This is a schematic diagram of the structure of a semiconductor device provided in another embodiment of this application;

[0066] Figure 6 This is a schematic diagram of the structure of a semiconductor device provided in another embodiment of this application;

[0067] Figure 7 This is a schematic diagram of the structure of a semiconductor device provided in another embodiment of this application;

[0068] Figure 8 This is a schematic diagram of the structure of a semiconductor device provided in another embodiment of this application;

[0069] Figure 9 This is a schematic diagram of the structure of a semiconductor device provided in another embodiment of this application;

[0070] Figure 10 This is a schematic diagram of the structure of a semiconductor device provided in another embodiment of this application;

[0071] Figure 11 Some flowcharts illustrating the fabrication method of the semiconductor device provided in the embodiments of this application;

[0072] Figure 12 A schematic diagram comparing the characteristics of the semiconductor device provided in the embodiments of this application with those of existing structures in the third quadrant;

[0073] Figure 13 A schematic diagram comparing the reverse recovery characteristics of the semiconductor device provided in the embodiments of this application with those of existing structures;

[0074] Figures 14a to 14l These are schematic diagrams illustrating a process for fabricating a semiconductor device according to embodiments of this application.

[0075] Figures 15a to 15c These are schematic diagrams illustrating a process for fabricating a semiconductor device according to an embodiment of this application.

[0076] Figures 16a to 16b These are schematic diagrams illustrating a process for fabricating a semiconductor device according to an embodiment of this application.

[0077] Figure 17 This is a schematic diagram of the structure of a semiconductor device provided in another embodiment of this application.

[0078] Figure label:

[0079] 010-Electric vehicle; 011-Power conversion circuit; 012-Battery; 013-Load; 0100-Electronic device; 0120-Load module; 0200-Power supply; 0111-DC-DC converter; 1-Semiconductor substrate; 2-Epipolar layer; 21-Drift layer; 22-Current spreading layer; 3-Trench; S1-First sidewall; S2-Second sidewall; 4-Gate; 41-First gate; 42-Second gate; 5-Gate insulating film; 6-First source region; 7-Well region; 8-Shielding region; 9-Second source region; 10-Channel region; 11-Interlayer dielectric layer; 12-Source; 13-Drain. Detailed Implementation

[0080] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The specific operational methods in the method embodiments can also be applied to the device embodiments or system embodiments. It should be noted that in the description of this application, "at least one" refers to one or more, where "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / ", unless otherwise specified, generally indicates that the preceding and following related objects have an "or" relationship. Furthermore, it should be understood that in the description of this application, words such as "first" and "second" are only used for distinguishing the purpose of description and should not be construed as indicating or implying relative importance or order.

[0081] It should be noted that in the embodiments of the present application, "connection" refers to electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components. For example, the connection between A and B can also be a direct connection between A and C, and C and B can be directly connected, with A and B connected through C.

[0082] Furthermore, the exemplary embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the figures denote the same or similar structures, and therefore repeated descriptions of them are omitted. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but may be modified as needed, and all such modifications are included within the scope of protection of this application. The accompanying drawings of this application are for illustrating relative positional relationships only and do not represent actual scale.

[0083] It should be noted that specific details are set forth in the following description to provide a full understanding of this application. However, this application can be implemented in many ways other than those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below. The following description is a preferred embodiment for carrying out this application; however, the description is for the purpose of illustrating the general principles of this application and is not intended to limit the scope of this application.

[0084] To facilitate understanding of the semiconductor devices, their fabrication methods, power conversion circuits, and vehicles provided in the embodiments of this application, their application scenarios will be introduced first below.

[0085] The semiconductor devices provided in this application can be used in vehicles (e.g., electric vehicles), such as in onboard microcontroller units (MCUs) and onboard battery chargers (OBCs). It should be noted that the semiconductor devices proposed in this application are intended for use in these and any other suitable types of devices, including but not limited to. The following description uses an electric vehicle as an example.

[0086] Figure 1 This is a schematic diagram of the structure of an electric vehicle provided in an embodiment of this application. (Refer to...) Figure 1 The electric vehicle 010 may include a power conversion circuit 011 and a battery 012.

[0087] In one possible implementation, the power conversion circuit 011 may include an alternating current (AC) to direct current (DC) converter and a DC-DC converter. The power conversion circuit 011 can also be referred to as an inverter. For example, when an electric vehicle is charging, the electric vehicle 010 can be connected to a three-phase power grid and receive three-phase AC power from the grid. By controlling the operation of the power switch in the AC-DC converter in the power conversion circuit 011, the AC-DC converter can convert the three-phase AC power into DC power. Furthermore, by controlling the operation of the power switch in the DC-DC converter in the power conversion circuit 011, the DC-DC converter can regulate the voltage of the DC power output from the AC-DC converter, thereby providing voltage-matched DC power to the battery 012. This allows the battery 012 to store the DC power, thus achieving the charging function.

[0088] In another possible implementation, the power conversion circuit 011 can also be a DC-DC converter circuit, and the electric vehicle 010 can also include a load 013, which can be an on-board device, power system, etc. of the electric vehicle 010. For example, by controlling the operation of the power switch of the DC-DC converter circuit of the power conversion circuit 011, the power conversion circuit 011 can regulate the DC power output from the battery and output it to the load 013, thereby providing voltage-adapted DC power to the load 013.

[0089] For example, the semiconductor device provided in this application embodiment can be applied to the power conversion circuit 011 of a vehicle as a power switch in an AC-DC converter and / or a DC-DC converter. Since the semiconductor device provided in this application embodiment has good device performance, when applied to an AC-DC converter and / or a DC-DC converter, it can improve the performance of the AC-DC converter and / or the DC-DC converter and reduce drive losses, thereby improving the overall circuit performance and reducing drive losses.

[0090] The semiconductor devices provided in this application can also be widely used in various electronic devices, such as those with logic devices or memory devices. For example, such electronic devices can be smartphones, smart TVs, laptops, PDAs (personal digital assistants), wearable devices with wireless communication capabilities (such as smartwatches, smart glasses, and smart bracelets), etc. It should be noted that the semiconductor devices proposed in this application are intended for use in these and any other suitable types of electronic devices, including but not limited to.

[0091] Figure 2This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. (Refer to...) Figure 2 The electronic device 0100 provided in this application embodiment includes a power conversion circuit 011 and a load module 0120, with the power conversion circuit 011 and the load module 0120 electrically connected. Exemplarily, the electronic device 0100 can be any electrical device. Examples include smartphones, smart TVs, laptops, PDAs (personal digital assistants), wearable devices with wireless communication capabilities (such as smartwatches, smart glasses, and smart bracelets), in-vehicle microcontroller units (MCUs), and on-board battery chargers (OBCs). It should be noted that this application does not limit the specific type of electronic device.

[0092] In some embodiments, the power conversion circuit 011 can be a direct current (DC) to direct current (DC) power conversion circuit, used to boost or buck DC power and output DC power to supply power to the load module 0120. For example, the power conversion circuit 011 can convert the DC power (e.g., 48V) output from the power supply 0200 into DC power suitable for all types of load modules 0120 and output it to the load module 0120 for operation. This application does not impose any limitations on the power supply 0200 and the load module 0120. The power supply 0200 can be any device or component capable of outputting DC power. For example, the power supply 0200 can be a battery (e.g., a storage battery). The power conversion circuit 011 can receive the battery voltage provided by the battery, convert the battery voltage into the operating voltage of the load module 0120, and output it to the load module 0120. The load module 0120 can be any functional module that uses DC power, such as a processor, chip, etc.

[0093] Reference Figure 2 The power conversion circuit 011 may include a DC-DC converter 0111. In specific operation, the MOSFETs in the DC-DC converter 0111 operate at a certain switching frequency, causing the DC-DC converter 0111 to boost or buck the DC power from the power supply 0200 before outputting it to the load module 0120 to provide the operating DC voltage. For example, the DC-DC converter may be a Buck converter, a Boost converter, a half-bridge converter, a full-bridge converter, or an inductor-inductor-capacitor (LLC) resonant converter, etc.

[0094] For example, the semiconductor device provided in this application embodiment can be applied to the DC-DC converter 0111 as a MOSFET in the DC-DC converter 0111. Since the semiconductor device provided in this application embodiment has good device performance, when the semiconductor device is applied to the MOSFET in the DC-DC converter 0111, the performance of the DC-DC converter 0111 can be improved and the drive loss can be reduced, thereby improving the performance of the entire electronic device and reducing the drive loss.

[0095] It should be noted that the above scenario descriptions are merely illustrative of some feasible application methods of the semiconductor device of this application. This application does not limit the specific application scenarios of the semiconductor device provided in the embodiments of this application, and can be determined according to the actual application requirements.

[0096] In some embodiments provided in this application, the materials of the semiconductor substrate 1 and the epitaxial layer 2 can be SiC, and the semiconductor device provided in the embodiments of this application is a SiC MOSFET.

[0097] It should be explicitly stated that, in this application, layers and regions prefixed with N or P represent electrons or holes as the majority carriers, respectively. Furthermore, a "+" sign marked with N or P indicates a higher doping concentration than layers or regions without a "+" sign, and the more "+" signs, the higher the doping concentration. The presence of the same number of "+" signs in N or P indicates similar doping concentrations, but is not limited to the same doping concentration. Similarly, a "-" sign marked with N or P indicates a lower doping concentration than layers or regions without a "-" sign, and the more "-" signs, the lower the doping concentration. The presence of the same number of "-" signs in N or P indicates similar doping concentrations, but is not limited to the same doping concentration.

[0098] It should also be noted that the comparison of doping concentration between the two regions in this application refers only to the comparison of the concentration of impurities doped in the two regions. The composition of the impurities is not limited to the substrate used to dope the impurities; that is, the composition of the impurities may be the same or different. The materials of the substrates used to dope the impurities may be the same or different.

[0099] Figure 3 This illustration shows a top view of a semiconductor device according to an embodiment of the present application. Figure 4 A top view of a semiconductor device provided in another embodiment of this application is shown.

[0100] Reference Figure 3 and Figure 4The semiconductor device provided in this application embodiment may specifically include: a semiconductor substrate 1, an epitaxial layer 2 disposed on the semiconductor substrate 1, a trench 3 disposed within the epitaxial layer 2, a gate 4 disposed within the trench 3 separated by a gate insulating film 5, a source 12 disposed on the epitaxial layer, and a drain 13 disposed on the side of the semiconductor substrate 1 away from the epitaxial layer 2. The trench 3 has a first sidewall S1 and a second sidewall S2 disposed opposite to each other. Exemplarily, the epitaxial layer 2 may include: a first source region 6 disposed outside the trench 3 and in contact with the first sidewall S1; a well region 7 located below the first source region 6; a shielding region 8 disposed outside the trench 3, enclosing the second sidewall S2 of the trench 3 and extending to the bottom of the trench 3; a second source region 9 disposed between the second sidewall S2 of the trench 3 and the shielding region 8; and a channel region 10 disposed between the bottom of the trench 3 and the shielding region 8 and in contact with the second source region 9.

[0101] In this application, the semiconductor substrate 1 can be a single-crystal SiC substrate doped with pentavalent elements, and the epitaxial layer 2 can be an epitaxially grown SiC material doped with corresponding impurities. Specifically, the semiconductor substrate 1 and the epitaxial layer 2 are mainly doped with N-type impurities, such as nitrogen (N), phosphorus (P), or arsenic (As). For example, the doping concentration of the semiconductor substrate 1 is generally greater than the doping concentration of the epitaxial layer 2.

[0102] In this application, the first source region 6, the second source region 9, and the channel region 10 can be formed by doping the epitaxial layer 2 using an ion implantation process. Furthermore, the dopants in the first source region 6, the second source region 9, and the channel region 10 are primarily N-type impurities, such as nitrogen (N), phosphorus (P), or arsenic (As). Exemplarily, the doping concentration of the channel region 10 is generally lower than that of the first source region 6 and the second source region 9, while the doping concentration of the first source region 6 and the second source region 9 are generally similar.

[0103] In this application, the well region 7 and the shielding region 8 can be formed by doping the epitaxial layer 2 using an ion implantation process. Furthermore, the dopants in the well region 7 and the shielding region 8 are primarily P-type impurities, such as boron (B), aluminum (Al), or gallium (Ga). Exemplarily, the doping concentration of the well region 7 is generally lower than that of the shielding region 8.

[0104] Continue to refer to Figure 3 and Figure 4The gate 4 may include a first gate 41 and a second gate 42, which are enclosed by a gate insulating film 5, meaning that the first gate 41 and the second gate 42 are insulated from each other. The channel region 10 may contact the gate insulating film 5 enclosing the second gate 42, but the channel region 10 and the gate insulating film 5 enclosing the first gate 41 are not in contact. Due to the presence of the second gate 42, and in conjunction with the channel region 10 located at the bottom of the trench 3, a low-barrier path for electrons exists at the interface between the gate insulating film 5 enclosing the second gate 42 and the channel region 10. This low-barrier path allows electrons to travel from the epitaxial layer 2 → the channel region 10 → the second source region 9. When the device is forward-biased or off, the low-barrier path can prevent electrons in the second source region 9 from entering the epitaxial layer 2 through the channel region 10, thus ensuring the device's blocking capability. When the device operates in the third quadrant, the negative drain bias 13 increases the electron energy in the epitaxial layer 2, correspondingly reducing the barrier height. When the electron energy exceeds the barrier, it preferentially conducts over the body diode from the epitaxial layer 2 to the well region 7, suppressing the body diode's turn-on. Furthermore, only electrons participate in conduction when the low-barrier path is on, resulting in a lower third-quadrant turn-on voltage and avoiding bipolar degradation. This low-barrier path also exhibits excellent reverse recovery characteristics; the reduced reverse recovery charge significantly lowers the MOSFET's turn-on loss. Specifically, the first gate 41 acts as the gate, thus it can be considered a true gate, while the second gate 42 is a virtual gate. Splitting the gate 4 into a true gate and a virtual gate can also significantly reduce the gate-drain capacitance and improve the device's high-frequency performance. Figure 11 and Figure 12 It can be seen that the device of the present invention is superior to the traditional structure in both third quadrant characteristics and reverse recovery characteristics.

[0105] Reference Figure 3 In some embodiments of this application, the gate 4 can be a split structure, that is, within the trench 3, the first gate 41 and the second gate 42 can be stacked, with the second gate 42 located at the bottom of the trench 3 and the first gate 41 located above the second gate 42, separated by a gate insulating film 5. Placing the second gate 42 at the bottom of the trench 3 facilitates contact between the channel region 10 and the gate insulating film 5 enclosing the second gate 42, while ensuring that the channel region 10 and the gate insulating film 5 enclosing the first gate 41 do not contact each other.

[0106] Reference Figure 4In other embodiments of this application, the gate 4 can be a split structure, with the first gate 41 and the second gate 42 arranged side by side in the trench 3. The first gate 41 is disposed adjacent to the first sidewall S1, and the second gate 42 is disposed adjacent to the second sidewall S2. The second gate 42 can also directly contact the source 12. Disposing the second gate 42 adjacent to the second sidewall S2 of the trench 3 facilitates contact between the channel region 10 and the gate insulating film 5 covering the second gate 42. Disposing the first gate 41 adjacent to the first sidewall S1 of the trench 3 ensures that the channel region 10 and the gate insulating film 5 covering the first gate 41 do not contact each other.

[0107] This application does not limit the material of the gate 4. For example, the material of the gate 4 can be polycrystalline silicon, or other materials with good electrical conductivity such as metals (e.g., W, Al, Ti, Cu, Mo or Pt).

[0108] Continue to refer to Figure 3 and Figure 4 In some embodiments of this application, an interlayer dielectric layer 11 may be further included, covering the epitaxial layer 2 on the side away from the semiconductor substrate 1. Furthermore, the interlayer dielectric layer 11 may have contact holes, the orthographic projection of which onto the semiconductor substrate 1 does not overlap with the orthographic projection of the first gate 41 onto the semiconductor substrate 1, and the contact holes expose the first source region 6, the second source region 9, and the shielding region 10, so that the source electrode 12 can contact the shielding region 10, the first source region 6, and the second source region 9 respectively through the contact holes, achieving the effect of ohmic contact between the source electrode 12 and the shielding region 10, the first source region 6, and the second source region 9 respectively.

[0109] This application does not limit the material used to form the interlayer dielectric layer 11. For example, the material used to form the interlayer dielectric layer 11 can be a dielectric material, including but not limited to silicon dioxide (SiO2), silicon oxynitride (SiNO), silicon oxycarbide (SiCO), silicon nitride (SiNx), etc.

[0110] This application does not limit the materials used to form the source 12 and the drain 13. For example, the materials used to form the source 12 and the drain 13 can be metallic materials. Exemplarily, the metallic materials may include W, Al, Ti, Cu, Mo, or Pt, etc.

[0111] Figure 5 This illustration shows a top view of a semiconductor device according to another embodiment of the present application. Figure 6 A top view of a semiconductor device provided in another embodiment of this application is shown.

[0112] Reference Figure 5 and Figure 6In some embodiments of this application, the epitaxial layer 2 may include a drift layer 21 disposed on the semiconductor substrate 1 and a current spreading layer (CSL) 22 disposed on the drift layer 21. The current spreading layer 22 can reduce the diffusion resistance of the current at the upper end of the drift layer 21. The trench 3, the first source region 6, the second source region 9, the well region 7, the channel region 10, and the shielding region 8 are generally disposed within the current spreading layer 22. The current spreading layer 22 and the drift layer 21 are primarily doped with N-type impurities, such as nitrogen (N), phosphorus (P), or arsenic (As). Exemplarily, the doping concentration of the semiconductor substrate 1 is generally greater than the doping concentration of the current spreading layer 22, and the doping concentration of the current spreading layer 22 is generally greater than the doping concentration of the drift layer 21. Alternatively, refer to... Figure 3 and Figure 4 In some other embodiments of this application, the epitaxial layer 2 may only have a drift layer 21, that is, there is no current spreading layer 22.

[0113] Reference Figures 3 to 6 In some embodiments of this application, the channel region 10 may be located only at the bottom of the trench 3, that is, the orthogonal projection of the channel region 10 onto the semiconductor substrate 1 may be located within the orthogonal projection range of the trench 3 onto the semiconductor substrate 1, and the second source region 9 extends from the second sidewall S2 of the trench 3 to the bottom of the trench 3 and contacts the channel region 10. It is worth noting that, in order to ensure that the channel region 10 only contacts the gate insulating film 5 covering the second gate 42, and that the channel region 10 and the gate insulating film 5 covering the first gate 41 do not contact each other, when the gate 4 has a left-right split structure, reference 4 and... Figure 6 The orthographic projection of the channel region 10 onto the semiconductor substrate 1 should be within the orthographic projection range of the second gate 42 onto the semiconductor substrate 1, and the orthographic projection of the channel region 10 onto the semiconductor substrate 1 should not overlap with the orthographic projection of the first gate 41 onto the semiconductor substrate 1.

[0114] Figure 7 This illustration shows a top view of a semiconductor device according to another embodiment of the present application. Figure 8 A top view of a semiconductor device provided in another embodiment of this application is shown.

[0115] Reference Figure 7 and Figure 8 In other embodiments of this application, the channel region 10 may also extend from the bottom of the trench 3 to the second sidewall S2 of the trench 3, so as to contact the second source region 9 located on the second sidewall S2 of the trench 3. It is worth noting that, in order to ensure that the channel region 10 only contacts the gate insulating film 5 surrounding the second gate 42, and that the channel region 10 does not contact the gate insulating film 5 surrounding the first gate 41, when the gate 4 has an upper and lower split structure, refer to... Figure 7The portion of the channel region 10 on the second sidewall S2 of the trench 3 cannot contact the gate insulating film 5 that wraps the first gate 41. The upper portion of the second sidewall S2 contacts the gate insulating film 5 that wraps the first gate 41. The lower portion of the second source region 9 contacts the gate insulating film 5 that wraps the second gate 42.

[0116] Figure 9 This illustration shows a top view of a semiconductor device according to another embodiment of the present application. Figure 10 A top view of a semiconductor device provided in another embodiment of this application is shown.

[0117] Reference Figure 9 and Figure 10 In some other embodiments of this application, based on the fact that the channel region 10 extends from the bottom of the trench 3 to the second sidewall S2 of the trench 3, the second source region 9 may also extend from the second sidewall S2 of the trench 3 to the bottom of the trench 3 and contact the channel region 10.

[0118] Figure 17 A top view of a semiconductor device provided in another embodiment of this application is shown.

[0119] Reference Figure 17 In the semiconductor device provided in the embodiments of this application, there are multiple periodically arranged repeating structures. Figure 17 The diagram illustrates two repeating structures, with the dashed line marking the boundary between them. Each repeating structure employs an asymmetrical layout, placing the shielding area on one side of the trench (the second sidewall), ensuring no current flows through the trench on that side, while the other side (the first sidewall) allows for switching on / off operations. During forward blocking, one bottom corner and part of the bottom of the gate insulating film are enveloped by the shielding area within the repeating structure, while the unenclosed portion of the gate insulating film is protected by the shielding area within the adjacent repeating structure, for example... Figure 17 The shielding area in the left repeating structure shown in the diagram also protects the gate insulating film in the right repeating structure, thus ensuring the reliability of the gate insulating film.

[0120] The semiconductor device provided in this application embodiment introduces a channel region 10 at the bottom of the trench 3. Combined with a gate splitting structure, this provides a low-barrier path for electrons to travel from the epitaxial layer 2 to the second source region 8. This results in a lower third-quadrant turn-on voltage, suppressing the turn-on of the body diode and solving the bipolar degradation problem. Furthermore, the low-barrier path exhibits excellent reverse recovery characteristics, and the reduced reverse recovery charge significantly lowers the device's turn-on loss.

[0121] Based on the same inventive concept, this application also provides a method for fabricating the above-mentioned semiconductor device.

[0122] Figure 13 Some flowcharts of the semiconductor device fabrication method provided in the embodiments of this application are shown. Figures 14a to 14l Schematic diagrams illustrating the process of fabricating a semiconductor device according to embodiments of this application are shown below. (Refer to...) Figure 13 To prepare Figure 5 Taking the structure shown as an example, the preparation method may include the following steps:

[0123] S10. An epitaxial layer is grown on a semiconductor substrate.

[0124] For example, step S10 may include:

[0125] First, an epitaxial process can be used to epitaxially grow SiC material doped with N-type impurities on an N-type SiC semiconductor substrate 1 to form a drift layer 21.

[0126] Then, refer to Figure 14a A current spreading layer 22 is formed by epitaxially growing SiC materials with different concentrations of N-type impurities on the drift layer 21.

[0127] This application does not specify the exact thickness of the drift layer 21 and the current spreading layer 22. In practical applications, the exact thickness of the drift layer 21 and the current spreading layer 22 can be determined according to the requirements of the actual application environment.

[0128] S20. A trap region, a first source region, and a shielding region are formed in the epitaxial layer.

[0129] For example, step S20 may include:

[0130] First, refer to Figure 14b The current extension layer 22 is doped with P-type impurities using an ion implantation process to form a well region 7.

[0131] Then, refer to Figure 14c An ion implantation process is used to dope N-type impurities at the location of the well region 7 to form the first source region 6, so that the retained well region 7 is located below the first source region 6.

[0132] Then, refer to Figure 14d The current spreading layer 22 is doped with P-type impurities using an ion implantation process to form a shielding region 8.

[0133] Therefore, in this embodiment of the application, after the ion implantation process, a trap region 7, a first source region 6, and a shielding region 8 are formed in the current extension layer 22.

[0134] S30. Etch the epitaxial layer to form trenches in the epitaxial layer.

[0135] For example, firstly, a trench mask (which can be a mask formed using photoresist or a hard mask) is formed on the current spreading layer 22. This trench mask covers the areas in the current spreading layer 22 where trenches 3 do not need to be formed, while exposing the areas in the current spreading layer 22 where trenches 3 need to be formed. Then, referring to… Figure 14e A suitable etching process is selected from plasma etching, ion sputtering etching, and reactive ion etching to etch the area of ​​the current spreading layer 22 that is not covered by the trench mask, thus forming a trench 3 in the current spreading layer 22. The trench 3 has a first sidewall S1 and a second sidewall S2 that are arranged opposite to each other. The well region 7, the first source region 6, and the shielding region 8 are all located outside the trench 3. The well region 7 and the first source region 6 are in contact with the first sidewall S1, and the shielding region 8 is in contact with the second sidewall S2.

[0136] S40. A second source region is formed on the second sidewall of the trench, and a channel region is formed at the bottom of the trench.

[0137] For example, firstly, refer to Figure 14f An inclined ion implantation process was used to dope the surface of the second sidewall S2 of trench 3 with N-type impurities, forming the second source region 9. Then, referring to... Figure 14g A vertical ion implantation process is used to dope N-type impurities at the bottom of trench 3 to form a channel region 10 that contacts the second source region 9.

[0138] S50. A gate insulating film is formed in the trench, and a gate is formed in the trench in which the gate insulating film is formed.

[0139] For example, firstly, the semiconductor device can be activated and annealed, and then cleaned. Next, referring to... Figure 14h A high-temperature (>1150 degrees) oxidation process can be used to oxidize the surface of the trench 3, so that a gate insulating film 5 is formed on the surface of the trench 3.

[0140] Next, a deposition process is used to deposit polysilicon material on the entire current spreading layer 22 where the trenches 3 are formed, and the polysilicon material fills the trenches 3. After the trenches 3 are filled with polysilicon material, a polysilicon film layer covers the entire current spreading layer 22. Then, referring to… Figure 14i A suitable etching process is selected from etching processes such as plasma etching, ion sputtering etching, and reactive ion etching to etch the polysilicon material region to form the second gate 42.

[0141] Then, refer to Figure 14jA low-temperature (<900 degrees) oxidation process can be used to oxidize a portion of the polysilicon material on the surface of the second gate 42, so that a gate insulating film 5 is formed on the surface of the second gate 42, ensuring that the first gate 41 and the second gate 42 are wrapped by the gate insulating film 5.

[0142] Next, a deposition process is used again to deposit polysilicon material on the entire current spreading layer 22 where the second gate 42 is formed, and the polysilicon material fills the trench 3. After filling the trench 3 with polysilicon material, a polysilicon film layer covers the entire current spreading layer 22. Then, referring to… Figure 14k A suitable etching process is selected from etching processes such as plasma etching, ion sputtering etching, and reactive ion etching to etch the polysilicon material region again to form the first gate 41.

[0143] S60. A source electrode is formed on the epitaxial layer, and a drain electrode is formed on the side of the semiconductor substrate away from the epitaxial layer.

[0144] For example, firstly, a deposition process can be used to deposit an interlayer dielectric layer 11 on the entire current spread layer 22, so that the interlayer dielectric layer 11 covers the entire current spread layer 22.

[0145] Next, a contact hole mask (which can be a photoresist mask or a hard mask) is formed on the current spreading layer 22. This contact hole mask covers the areas where contact holes do not need to be formed, while exposing the areas where contact holes need to be formed. Then, a suitable etching process is selected from etching processes such as plasma etching, ion sputtering etching, and reactive ion etching to etch the areas of the interlayer dielectric layer 11 that are not covered by the contact hole mask, exposing the shielding region 8, the first source region 6, and the second source region 9.

[0146] Then, refer to Figure 14l A deposition process is used to deposit metallic material on the interlayer dielectric layer 11 to form the source electrode 12. The source electrode 12 is then connected to the shielding region 8, the first source region 6, and the second source region 9 through the contact holes filled with metallic material.

[0147] For example, refer to Figure 14l Alternatively, a deposition process can be used to deposit metal material on the side of the semiconductor substrate 1 away from the epitaxial layer 2 before forming the source electrode 12, thus forming the drain electrode 13.

[0148] This application does not limit the materials of the source 12 and the drain 13. For example, the materials forming the source 12 and the drain 13 can be metallic materials. Exemplarily, the metallic material may include W, Al, Ti, Cu, Mo or Pt.

[0149] Figures 15a to 15c The following are schematic diagrams illustrating another process for fabricating a semiconductor device provided in the embodiments of this application.

[0150] Reference Figures 15a to 15c In some embodiments of this application, when the gate in the semiconductor device adopts a split structure, the above step S50, forming the gate in the trench where the gate insulating film is formed, may specifically include:

[0151] First, a deposition process is used to deposit polysilicon material onto the entire current spreading layer 22 where trenches 3 are formed, and the polysilicon material fills the trenches 3. After filling the trenches 3 with polysilicon material, a polysilicon film layer covers the entire current spreading layer 22. Next, referring to… Figure 15a A suitable etching process is selected from etching processes such as plasma etching, ion sputtering etching, and reactive ion etching to etch the polysilicon material region in order to form the first gate 41 on one side of the first sidewall S1.

[0152] Then, refer to Figure 15b A low-temperature (<900 degrees) oxidation process can be used to oxidize a portion of the polysilicon material on the surface of the first gate 41, so that a gate insulating film 5 is formed on the surface of the first gate 41, ensuring that the first gate 41 and the second gate 42 are wrapped by the gate insulating film 5.

[0153] Next, a deposition process is used again to deposit polysilicon material on the entire current spreading layer 22 where the first gate 41 is formed, and the polysilicon material fills the trench 3. After filling the trench 3 with polysilicon material, a polysilicon film layer covers the entire current spreading layer 22. Then, referring to… Figure 15c A suitable etching process is selected from etching processes such as plasma etching, ion sputtering etching, and reactive ion etching to etch the polysilicon material region again to form the second gate 42.

[0154] Figures 16a to 16b The following are schematic diagrams illustrating another process for fabricating a semiconductor device provided in the embodiments of this application.

[0155] Reference Figures 16a to 16b In other embodiments of this application, when the gate in the semiconductor device adopts a split structure, the above step S50, forming the gate in the trench where the gate insulating film is formed, may specifically include:

[0156] First, a deposition process is used to deposit polysilicon material onto the entire current spreading layer 22 where trenches 3 are formed, and the polysilicon material fills the trenches 3. After filling the trenches 3 with polysilicon material, a polysilicon film layer covers the entire current spreading layer 22. Next, referring to… Figure 16a A suitable etching process is selected from etching processes such as plasma etching, ion sputtering etching, and reactive ion etching to etch the polysilicon material region in order to form a second gate 42 on one side of the second sidewall S2.

[0157] Then, refer to Figure 16b A low-temperature (<900 degrees) oxidation process can be used to oxidize a portion of the polysilicon material on the surface of the second gate 42, so that a gate insulating film 5 is formed on the surface of the second gate 42, ensuring that the first gate 41 and the second gate 42 are wrapped by the gate insulating film 5.

[0158] Next, a deposition process is used again to deposit polysilicon material on the entire current spreading layer 22 where the second gate 42 is formed, and the polysilicon material fills the trench 3. After filling the trench 3 with polysilicon material, a polysilicon film layer covers the entire current spreading layer 22. Then, a suitable etching process is selected from etching processes such as plasma etching, ion sputtering etching, and reactive ion etching to etch the polysilicon material region again to form the first gate 41.

[0159] This application also provides a power conversion circuit, which can be an AC-to-DC conversion circuit and / or a DC-to-DC conversion circuit. The power conversion circuit may include a circuit board and one or more semiconductor devices, with the semiconductor devices connected to the circuit board. Because the aforementioned semiconductor devices have good performance, the power conversion circuit including these semiconductor devices also has good performance. Furthermore, the principle by which this power conversion circuit solves the problem is similar to the principle by which the aforementioned semiconductor devices solve the problem; therefore, the technical effects of this power conversion circuit can be referred to the technical effects of the aforementioned semiconductor devices, and repetitions will not be repeated.

[0160] This application also provides a vehicle, which includes a battery, a power conversion circuit provided in this application, and a motor connected in sequence. Because the power conversion circuit described above has good performance, the vehicle including the power conversion circuit also has good circuit performance. Furthermore, the principle by which this vehicle solves the problem is similar to the principle by which the aforementioned power conversion circuit solves the problem; therefore, the technical effect of this vehicle can be referred to the technical effect of the aforementioned power conversion circuit, and repeated details will not be elaborated further.

[0161] Obviously, those skilled in the art may make various modifications and variations to this application without departing from the scope of protection of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A semiconductor device, characterized in that, include: Semiconductor substrate; An epitaxial layer is disposed on the semiconductor substrate; A trench disposed within the epitaxial layer, the trench having a first sidewall and a second sidewall disposed opposite to each other; A gate, wherein the gate is disposed within the trench, the gate comprising a first gate and a second gate, the first gate and the second gate being wrapped by a gate insulating film; The first source region is disposed within the epitaxial layer and is located outside the trench and in contact with the first sidewall; A well region is disposed within the epitaxial layer and located below the first source region; A shielding area is disposed within the epitaxial layer, the shielding area is located outside the trench and wraps around the second sidewall and extends to the bottom of the trench; The second source region is disposed within the epitaxial layer and is located between the second sidewall of the trench and the shielding region; The channel region is disposed within the epitaxial layer. The channel region is located between the bottom of the trench and the shielding region and is in contact with the second source region. The channel region is in contact with the gate insulating film that encapsulates the second gate, and the channel region is not in contact with the gate insulating film that encapsulates the first gate. A source electrode is disposed on the epitaxial layer and is in contact with the shielding region, the first source region, and the second source region, respectively. Drain electrode, which is disposed on the side of the semiconductor substrate away from the epitaxial layer.

2. The semiconductor device as claimed in claim 1, characterized in that, Within the trench, the first gate and the second gate are stacked, with the second gate located at the bottom of the trench and the first gate located above the second gate.

3. The semiconductor device as described in claim 1, characterized in that, Within the trench, the first gate and the second gate are arranged side by side, with the first gate disposed adjacent to the first sidewall and the second gate disposed adjacent to the second sidewall, and the second gate in contact with the source electrode.

4. The semiconductor device according to any one of claims 1-3, characterized in that, The orthographic projection of the channel region onto the semiconductor substrate lies within the orthographic projection range of the trench onto the semiconductor substrate, and the second source region extends to the bottom of the trench.

5. The semiconductor device according to any one of claims 1-4, characterized in that, The epitaxial layer includes a drift layer disposed on the semiconductor substrate and a current spreading layer disposed on the drift layer. The current spreading layer and the drift layer are N-type doped, and the doping concentration of the current spreading layer is greater than that of the drift layer. The trench, the first source region, the second source region, the well region, the channel region, and the shielding region are all disposed within the current spreading layer.

6. The semiconductor device as claimed in claim 5, characterized in that, The semiconductor substrate is N-type doped, and the doping concentration of the semiconductor substrate is greater than the doping concentration of the current spreading layer.

7. The semiconductor device according to any one of claims 1-6, characterized in that, The channel region, the first source region, and the second source region are N-type doped, and the doping concentration of the channel region is less than that of the first source region and the second source region.

8. The semiconductor device according to any one of claims 1-7, characterized in that, The well region and the shielding region are P-type doped, and the doping concentration of the well region is less than that of the shielding region.

9. The semiconductor device according to any one of claims 1-8, characterized in that, Also includes: An interlayer dielectric layer covers the epitaxial layer on the side away from the semiconductor substrate, and the interlayer dielectric layer has a contact hole, the orthographic projection of the contact hole on the semiconductor substrate and the orthographic projection of the first gate on the semiconductor substrate do not overlap, and the contact hole exposes the first source region, the second source region and the shielding region; The source electrode is in contact with the shielding area, the first source area, and the second source area through the contact hole, respectively.

10. The semiconductor device according to any one of claims 1-9, characterized in that, The semiconductor substrate and the epitaxial layer are made of SiC.

11. A method for fabricating a semiconductor device, characterized in that, include: An epitaxial layer is grown on a semiconductor substrate, and a well region, a first source region, and a shielding region are formed in the epitaxial layer. The epitaxial layer is etched to form a trench in the epitaxial layer. The trench has a first sidewall and a second sidewall disposed opposite to each other. The well region, the first source region and the shielding region are all located outside the trench. The well region and the first source region are both in contact with the first sidewall. The well region is located below the first source region. The shielding region is in contact with the second sidewall. A second source region is formed on the second sidewall of the trench, and a channel region is formed at the bottom of the trench, the channel region being in contact with the second source region; A gate insulating film is formed in the trench, and a gate is formed in the trench in which the gate insulating film is formed. The gate includes a first gate and a second gate, and the first gate and the second gate are wrapped by the gate insulating film. A source electrode is formed on the epitaxial layer, and the source electrode is in contact with the shielding region, the first source region and the second source region, respectively. A drain electrode is formed on the side of the semiconductor substrate away from the epitaxial layer.

12. The method for fabricating a semiconductor device as described in claim 11, characterized in that, Forming a gate in a trench where the gate insulating film is formed includes: A second gate is formed in a trench in which the gate insulating film is formed; The gate insulating film is formed to enclose the surface of the second gate. A first gate is formed on a second gate whose surface is covered by the gate insulating film.

13. The method for fabricating a semiconductor device as described in claim 11, characterized in that, Forming a gate in a trench where the gate insulating film is formed includes: A first gate is formed on one side of the first sidewall in the trench where the gate insulating film is formed; The gate insulating film is formed covering the surface of the first gate. A second gate is formed on one side of the second sidewall in the trench.

14. The method for fabricating a semiconductor device as described in claim 11, characterized in that, Forming a gate in a trench where the gate insulating film is formed includes: A second gate is formed on one side of the second sidewall in the trench where the gate insulating film is formed; The gate insulating film is formed to cover the surface of the second gate. A first gate is formed on one side of the first sidewall in the trench.

15. The method for fabricating a semiconductor device according to any one of claims 11-14, characterized in that, Also includes: An interlayer dielectric layer covering the entire epitaxial layer is formed on the epitaxial layer; The interlayer dielectric layer is etched to form a contact hole, which exposes the first source region, the second source region, and the shielding region. The orthographic projection of the contact hole onto the semiconductor substrate does not overlap with the orthographic projection of the first gate onto the semiconductor substrate. The source electrode contacts the shielding region, the first source region, and the second source region through the contact hole, respectively.

16. A power conversion circuit, characterized in that, It includes a circuit board and one or more semiconductor devices as described in any one of claims 1-10, wherein the semiconductor devices are connected to the circuit board.

17. A vehicle, characterized in that, It includes a battery, a power conversion circuit as described in claim 16, and a motor connected in sequence, wherein the power conversion circuit is used to convert AC and / or DC power to output DC power.

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