A SiC VDMOSFET device of lateral variable-doping body diode
By introducing a lateral doped body diode structure into SiC VDMOSFET, the problem of poor reverse recovery characteristics of SiC VDMOSFET is solved, thereby reducing switching power consumption and improving device reliability.
Patent Information
- Application Number
- CN202211263060.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-10-14
- Publication Date
- 2025-12-05
- Estimated Expiration
- 2042-10-14
AI Technical Summary
The parasitic body diode of SiC VDMOSFET has poor reverse recovery characteristics, which leads to increased switching power consumption and decreased device reliability. Furthermore, the integrated Schottky base diode design increases the cell size.
By employing a lateral variable doped diode structure, the minority carrier concentration in the drift region is reduced and the reverse recovery characteristics are improved by forming parallel P+/P-/P+ contact regions in the SiC VDMOSFET.
Without increasing the cell size, the reverse recovery speed of the device is improved, the switching power consumption is reduced, and the reliability of the device is improved.
Smart Images
Figure CN115632069B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the field of microelectronics technology, and particularly relates to a SiC VDMOSFET device with a lateral variable-doping body diode. BACKGROUND
[0002] In high-power inverter applications, a freewheeling diode is needed to provide a current path for the VDMOSFET when it is turned off. In particular, in hard-switching applications, a topology of VDMOSFET and diode in anti-parallel is usually used, such as synchronous buck DC converter and inverter. This topology mainly provides a freewheeling path by the reverse conduction of the VDMOSFET during the freewheeling period, and the diode is turned off during the dead time. The diode will experience a reverse recovery process from the on state to the off state during the freewheeling period. If the reverse recovery characteristic is poor, not only the switching characteristics of the device will be affected, i.e. the switching power consumption increases and the circuit efficiency decreases, but also a large reverse peak current may be generated to damage the reliability of the device.
[0003] For Si-based switching systems, since the Si-based VDMOSFET parasitic body diode has poor reverse recovery characteristics, a diode is usually connected in series with the drain of the Si-based VDMOSFET to prevent the parasitic body diode from being turned on, and a fast recovery diode is connected in anti-parallel across the source and the drain to provide a new freewheeling path. In contrast, at the same voltage level, the SiC-based VDMOSFET has a smaller drift region thickness due to the larger critical breakdown field strength of the material, which greatly reduces the internal stored charge when the parasitic body diode of the SiC-based VDMOSFET is turned on, thereby improving the reverse recovery characteristics of the device and reducing the switching power consumption, which provides the possibility for the application of the body diode of the SiC VDMOSFET.
[0004] However, since the parasitic body diode of the SiC VDMOSFET is generally a PN junction formed by a P+ contact region (P well) and an N-type drift region, its reverse recovery characteristics are still subject to the minority carrier storage effect. Although the integrated Schottky body diode design using the split source or split gate method has better switching characteristics, the additional Schottky diode embedded in the VDMOSFET also increases the cell size of the VDMOSFET. SUMMARY
[0005] In order to solve the above problems in the prior art, the application provides a SiC VDMOSFET device with a lateral variable-doping body diode. The technical problem to be solved by the application is solved by the following technical scheme:
[0006] A SiC VDMOSFET device of a lateral variable-doping body diode, comprising: a drain, an N+ substrate and an N- drift region arranged in sequence from bottom to top;
[0007] The N- drift region has P well regions on both sides thereof;
[0008] The P well regions have N+ active regions inside thereof;
[0009] The N+ active regions and the inner side boundaries of the P well regions have a spacing therebetween;
[0010] The P well regions have first P+ contact regions formed on the outward side surfaces thereof;
[0011] The first P+ contact regions extend from the surface of the N- drift region to the bottom boundary of the P well regions and contact the outward side of the N+ active regions;
[0012] The first P+ contact regions have P- contact regions formed on the side surfaces thereof facing away from the N+ active regions;
[0013] The P- contact regions have second P+ contact regions formed on the side surfaces thereof facing away from the first P+ contact regions;
[0014] Further comprising: a gate oxide layer, a gate, a SiO2 passivation layer and a source;
[0015] The gate oxide layer contacts the surface of the N- drift region between the two P well regions, part of the surface of the P well regions and part of the surface of the N+ active regions;
[0016] The gate is located above the gate oxide layer;
[0017] The SiO2 passivation layer is located above the gate oxide layer and the gate;
[0018] The source is located above the first P+ contact regions, the P- contact regions, the second P+ contact regions, part of the N+ active regions and the SiO2 passivation layer.
[0019] In an embodiment of the present application, the first P+ contact regions and the second P+ contact regions are connected in parallel with the P- contact regions.
[0020] In an embodiment of the present application, the surface of the P well regions has a doping concentration of 2.5×10 17 cm -3 , and the bottom of the P well regions close to the boundary of the N- drift region has a doping concentration of 1×10 16 cm -3 ;
[0021] The first P+ contact regions and the second P+ contact regions have a doping concentration of 5×1018 cm -3 ;
[0022] The doping concentration of the P-contact region is 7*10 17 cm -3 ;
[0023] The doping concentration of the N+ active region is 6*10 18 cm -3 ;
[0024] The doping concentration of the N- drift region is 6*10 15 cm -3 .
[0025] In an embodiment of the present application, the doping concentration of the N+ substrate is 5*10 18 cm -3 ;
[0026] The gate is N-type polysilicon material, and the doping concentration is 1*10 20 cm -3 , and the doping ion is phosphorus ion.
[0027] In an embodiment of the present application, the N+ substrate, the N- drift region and the N+ active region are all N-type SiC material; the doping ion of the N-type SiC material is nitrogen ion or phosphorus ion;
[0028] The P-well region, the first P+ contact region, the P- contact region and the second P+ contact region are all P-type SiC material, and the doping ion of the P-type SiC material is boron ion or aluminum ion.
[0029] In an embodiment of the present application, the thickness of the N- drift region is 60-70um.
[0030] In an embodiment of the present application, the interface between the source and the N+ active region, the first P+ contact region, the P- contact region and the second P+ contact region is ohmic contact.
[0031] The interface between the drain and the N+ substrate is ohmic contact.
[0032] The present application has the following beneficial effects:
[0033] The application forms a contact area of a lateral variable doping structure of P+ / P- / P+ under the premise of not increasing the cell size of the SiC VDMOSFET body diode, reduces the minority carrier concentration injected into the drift region during the freewheeling period, i.e. accelerates the speed of the minority carrier holes swept out of the drift region in the reverse recovery process, improves the minority carrier storage effect of the PN junction, and improves the reverse recovery characteristics of the device, thereby solving the problems of increased switching power consumption and reduced device reliability caused by poor reverse recovery characteristics of the SiC VDMOSFET parasitic body diode.
[0034] The application will be further described in detail below in combination with the drawings and embodiments. BRIEF DESCRIPTION OF DRAWINGS
[0035] Figure 1 A cross-sectional schematic view of a structure of a SiC VDMOSFET device with a lateral variable doping body diode according to an embodiment of the application.
[0036] REFERENCE NUMERALS
[0037] 10-drain; 20-N+ substrate; 30-N- drift region; 40-P well region; 50-N+ active region; 61-first P+ contact area; 62-P- contact area; 63-second P+ contact area; 71-gate oxide layer; 72-gate; 80-SiO2 passivation layer; 90-source. DETAILED DESCRIPTION
[0038] The application will be further described in detail below in combination with the drawings and embodiments.
[0039] As shown in the drawings, Figure 1 A SiC VDMOSFET device with a lateral variable doping body diode, including, from bottom to top, a drain 10, an N+ substrate 20, and an N- drift region 30, further including a gate oxide layer 71, a gate 72, an SiO2 passivation layer 80, and a source 90.
[0040] The N- drift region 30 has a P well region 40 on each side. The P well region 40 extends from the surface of the N- drift region 30 to the inside of the N- drift region 30. The inside of each P well region 40 has an N+ active region 50; the N+ active region 50 extends from the surface of the P well region 40 to the inside of the P well region 40. There is a gap between the N+ active region 50 and the inside boundary of the P well region 40. The first P+ contact area 61 is formed on the outward side surface of the P well region 40.
[0041] The first P+ contact region 61 extends from the surface of the N-drift region 30 to the bottom boundary of the P-well region 40, and the first P+ contact region 61 is in contact with the outward side of the N+ active region 50. The P- contact region 62 is formed on the side of the first P+ contact region 61 facing away from the N+ active region 50. The P- contact region 62 extends from the surface of the N-drift region 30 to the bottom boundary of the P-well region 40. The second P+ contact region 63 is formed on the side of the P- contact region 62 facing away from the first P+ contact region 61; the second P+ contact region 63 extends from the surface of the N-drift region 30 to the bottom boundary of the P-well region 40. The P- contact region 62 is located between the first P+ contact region 61 and the second P+ contact region 63. The N-drift region 30 of the body diode has two contact regions composed of the first P+ contact region 61, the P- contact region 62, and the second P+ contact region 63, and the P+ contact region and the P- contact region 62 are in parallel, that is, the first P+ contact region 61 and the second P+ contact region 63 are in parallel with the P- contact region 62.
[0042] The gate oxide layer 71 is in contact with the surface of the N-drift region 30 between the two P-well regions 40, part of the surface of the P-well region 40, and part of the surface of the N+ active region 50. The gate electrode 72 is located above the gate oxide layer 71. The SiO2 passivation layer 80 is located above the gate oxide layer 71 and the gate electrode 72, and wraps the gate electrode 72. The source electrode 90 is located above the first P+ contact region 61, the P- contact region 62, the second P+ contact region 63, part of the N+ active region 50, and the SiO2 passivation layer 80. The source electrode 90 covers the surface of the device.
[0043] In this embodiment, the doping mode of the P+ contact region of the conventional body diode is changed from uniform doping to variable doping, so that the original single body diode becomes a structure of multiple body diodes in parallel. Since the additional hole injection of the PIN junction is related to the P-type doping concentration, the structure of this embodiment is equivalent to two PINs in parallel with different injection ratios. During actual freewheeling, the high-concentration holes injected into the drift region by the PN junction with a high injection ratio will rapidly diffuse in all directions, blocking the diffusion channel of the low-concentration holes and thus shielding the body diode in the low-doped region, reducing the minority carrier concentration injected into the drift region 30 during freewheeling, and weakening the storage effect of the additional carriers, so that the reverse recovery speed of the device during the reverse recovery stage is accelerated due to the decrease in the storage charge density, and the reverse recovery characteristics of the device are improved. Moreover, since the body diode still retains the P+ contact region, the forward transmission characteristics of the body diode during the freewheeling stage will not be affected, while the reverse characteristics are improved, thus increasing the switching speed of the device and reducing the power consumption. At the same time, the structure of this embodiment does not increase the cell size of the SiC VDMOSFET body diode.
[0044] In one embodiment, the surface doping concentration of the P-well region 40 is 2.5 x 1018 cm-3. 17 cm -3The doping concentration of the bottom of the P-well region 40 near the boundary of the N-drift region 30 is 1 x 1018cm-3. 16 cm -3 ;
[0045] The doping concentration of the first P+ contact region 61 and the second P+ contact region 63 is 5 x 1019cm-3. 18 cm -3 ;
[0046] The doping concentration of the P- contact region 62 is 7 x 1019cm-3. 17 cm -3 ;
[0047] The doping concentration of the N+ active region 50 is 6 x 1019cm-3. 18 cm -3 ;
[0048] The doping concentration of the N-drift region 30 is 6 x 1018cm-3. 15 cm -3 .
[0049] In one embodiment, the doping concentration of the N+ substrate 20 is 5 x 1018cm-3. 18 cm -3 ;
[0050] The gate 72 is N-type polysilicon material, and the doping concentration is 1 x 1019cm-3, and the doping ions are phosphorus ions. 20 cm -3 .
[0051] In one embodiment, the N+ substrate 20, the N-drift region 30 and the N+ active region 50 are all N-type SiC material; the doping ions of the N-type SiC material are nitrogen ions or phosphorus ions.
[0052] The P-well region 40, the first P+ contact region 61, the P- contact region 62 and the second P+ contact region 63 are all P-type SiC material, and the doping ions of the P-type SiC material are boron ions or aluminum ions.
[0053] In one embodiment, the thickness of the N-drift region 30 is 60-70um.
[0054] In one embodiment, the interface between the source 90 and the N+ active region 50, the first P+ contact region 61, the P- contact region 62 and the second P+ contact region 63 is ohmic contact.
[0055] The interface between the drain 10 and the N+ substrate 20 is ohmic contact.
[0056] In the description of the present application, it is to be understood that the orientations or positional relationships indicated by the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements indicated thereby must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.
[0057] In addition, the terms "first", "second", "third", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated thereby. Therefore, the features defined with "first", "second", etc. can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified and limited.
[0058] In the present application, unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting", "fixing" and the like should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrated; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.
[0059] In the present application, unless otherwise explicitly specified and limited, the first feature "above" or "below" the second feature can include that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, the first feature "above", "above" and "above" the second feature includes that the first feature is directly above and obliquely above the second feature, or only indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature "below", "below" and "below" the second feature includes that the first feature is directly below and obliquely below the second feature, or only indicates that the horizontal height of the first feature is less than that of the second feature.
[0060] In the description of the specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate different embodiments or examples described in the specification.
[0061] The above is a further detailed description of the present application in combination with specific preferred embodiments, and cannot be considered as limiting the specific implementation of the present application to these descriptions. For those skilled in the art, without departing from the concept of the present application, a number of simple deductions or substitutions can be made, which should be considered as falling within the protection scope of the present application.
Claims
1. A SiC VDMOSFET device of lateral variable-doped body diode, characterized in that, The application relates to a vertical power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) device. The device comprises: a drain electrode (10), an N+ substrate (20) and an N- drift region (30) arranged from bottom to top; each of the two side portions of the N- drift region (30) has a P-well region (40); the inner portion of the P-well region (40) has an N+ active region (50); a gap is formed between the N+ active region (50) and the inner side boundary of the P-well region (40); a first P+ contact region (61) is formed on the outward side surface of the P-well region (40); the first P+ contact region (61) extends from the surface of the N- drift region (30) to the bottom boundary of the P-well region (40) and contacts the outward side of the N+ active region (50); a P- contact region (62) is formed on the side of the first P+ contact region (61) facing away from the N+ active region (50); a second P+ contact region (63) is formed on the side of the P- contact region (62) facing away from the first P+ contact region (61); the device further comprises a gate oxide layer (71), a gate electrode (72), a SiO2 passivation layer (80) and a source electrode (90); the gate oxide layer (71) contacts the surface of the N- drift region (30) between the two P-well regions (40), part of the surface of the P-well region (40) and part of the surface of the N+ active region (50); the gate electrode (72) is located above the gate oxide layer (71); the SiO2 passivation layer (80) is located above the gate oxide layer (71) and the gate electrode (72); 2. The SiC VDMOSFET device of claim 1, wherein, the source electrode (90) is located above the first P+ contact region (61), the P- contact region (62), the second P+ contact region (63), part of the N+ active region (50) and the SiO2 passivation layer (80).
3. The SiC VDMOSFET device of claim 1, wherein, The surface doping concentration of the P-well region (40) is 2.5 × 10⁻⁶. 17 cm -3 The doping concentration at the bottom of the P-well region (40) near the boundary of the N-drift region (30) is 1×10⁻⁶. 16 cm -3 ; The doping concentration of the first P+ contact region (61) and the second P+ contact region (63) is both 5 x 1019cm-3. 18 cm -3 ; The P-contact region (62) has a doping concentration of 7 x 1018cm-3 17 cm -3 -3 The N+ active region (50) has a doping concentration of 6 x 1018 18 cm -3 -3 The N-drift region (30) has a doping concentration of 6 x 1015cm-3 15 cm -3 .
4. The SiC VDMOSFET device of claim 1, wherein, The N+ substrate (20) has a doping concentration of 5 x 1018 18 cm -3 -3 The gate (72) is N-type polysilicon material with a doping concentration of 1 x 10 20 cm -3 -3 and phosphorus ions as doping ions.
5. The SiC VDMOSFET device of claim 1, wherein, The first P+ contact region (61) and the second P+ contact region (63) are connected in parallel with the P- contact region (62). The N+ substrate (20), the N- drift region (30) and the N+ active region (50) are all N-type SiC materials, and the doping ions of the N-type SiC materials are nitrogen ions or phosphorus ions; 6. The SiC VDMOSFET device of claim 1, wherein, The P-well region (40), the first P+ contact region (61), the P- contact region (62) and the second P+ contact region (63) are all P-type SiC materials, and the doping ions of the P-type SiC materials are boron ions or aluminum ions.
7. The SiC VDMOSFET device of claim 1, wherein, The thickness of the N- drift region (30) is 60-70 um. The interface between the source electrode (90) and the N+ active region (50), the first P+ contact region (61), the P- contact region (62) and the second P+ contact region (63) is ohmic contact; the interface between the drain electrode (10) and the N+ substrate (20) is ohmic contact.