Method, device, equipment and storage medium for realizing clock synchronization

Abstract

The present disclosure provides a method and apparatus, device, and storage medium for clock synchronization, and relates to the field of communication technology. The method for clock synchronization includes: obtaining the congestion parameters of the master clock, the congestion parameters including the average CPU utilization rate within a predetermined time and the average bandwidth utilization rate reaching the output interface of the slave clock device; based on the congestion parameters, processing the synchronization message to obtain an update synchronization message; sending the update synchronization message to the slave clock, so that the slave clock determines the stable state of the master clock according to the update synchronization message, and adjusts the crystal oscillator based on the stable state. The method disclosed in the present disclosure determines the stable state of the master clock according to the average CPU utilization rate and the average bandwidth utilization rate of the master clock. The slave clock adjusts the crystal oscillator accordingly according to the stable state of the master clock. The stable state of the master clock determines the crystal oscillator frequency of the slave clock, the synchronization accuracy is high, and the stability and reliability of the network are enhanced.

Description

Background Art

[0002] The clock frequency and phase differences of each network element in the digital network need to be limited within the allowable error range to ensure the stable transmission of the digital bit stream and avoid the loss or duplication of code elements due to inconsistent clock frequencies between devices or interference damage during the transmission of the digital bit stream, which leads to sliding damage in the transmitted bit stream. The current industry solution is the hardware-based IEEE1588 Time Synchronization Protocol (PTP). IEEE1588 is a network clock synchronization protocol that mainly runs on Ethernet. Its main goal is to achieve synchronization accuracy higher than microseconds within the scope of the local area network. It has now developed to version v2. In the IEEE1588v2 communication system, the clock is divided into a master clock and a slave clock. The basic principle of clock synchronization includes the recording of time information for sending and receiving time, and adding a "time stamp" to each piece of information. With the time record, the receiving end can calculate its own clock error and delay in the network, synchronize the master clock time from the slave clock and adjust the crystal oscillator.

[0003] The PTP protocol defines four types of multipoint transmission messages and management messages, including synchronization messages (Sync), follow-up messages (Follow_up), delay request messages (Delay_Req), and delay response messages (Delay_Resp). The interaction order of these messages is as follows: Figure 1 As shown. The Sync message is sent periodically from the master clock (usually once every two seconds), and it contains the clock attributes required by the master clock algorithm. Since the Sync message contains the expected sending time rather than the actual sending time, the actual sending time of the Sync message is measured and sent in the subsequent Follow_Up message. The receiver of the Sync message records the actual receiving time. Using the actual sending time in the Follow_Up message and the actual receiving time of the receiver, the time difference between the slave clock and the master clock can be calculated, and the slave clock time can be corrected accordingly.

[0004] However, the time difference calculated at this time includes the delay caused by network transmission, so the Delay_Req message is used to define the network transmission delay. The Delay_Req message is sent by the slave clock after the Sync message is received. Like the Sync message, the sender records the accurate sending time and the receiver records the accurate receiving time. The accurate receiving time is included in the Delay_Resp message, so as to calculate the network delay and clock error.

[0005] However, in the above adjustment method, when the CPU or current link bandwidth occupancy of the master clock is too high, it will cause problems such as unstable time synchronization. In the clock synchronization process, the slave clock cannot determine the status of the master clock. When the time deviation of the master clock is large, the time synchronization accuracy is significantly reduced.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0007] The purpose of the present disclosure is to provide a method and apparatus, device, and storage medium for implementing clock synchronization, which at least to some extent overcome the problem of low clock synchronization accuracy due to the limitations of related technologies.

[0008] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0009] According to one aspect of the present disclosure, a method for implementing clock synchronization is provided, which is applied to a master clock and includes:

[0010] Acquire congestion parameters of the master clock, where the congestion parameters include an average CPU utilization rate within a predetermined time and an average bandwidth utilization rate reaching an output interface of a slave clock device;

[0011] Based on the congestion parameter, the synchronization message is processed to obtain an update synchronization message;

[0012] The update synchronization message is sent to the slave clock, so that the slave clock determines the stable state of the master clock according to the update synchronization message, and performs crystal oscillator adjustment based on the stable state.

[0013] In an exemplary embodiment of the present disclosure, based on the congestion parameter, processing the synchronization message to obtain an update synchronization message includes:

[0014] Obtaining a reserved field in the synchronization message;

[0015] Based on the congestion parameter, modify the reserved field according to a preset conversion rule to obtain a binary number;

[0016] Based on the binary number, an update synchronization message is generated.

[0017] In an exemplary embodiment of the present disclosure, based on the congestion parameter, modifying the reserved field according to a preset conversion rule to obtain a binary number includes:

[0018] Modify the reserved field according to the CPU average utilization to generate a CPU status code, where the CPU status code includes 00, 01, 10, and 11;

[0019] Modify the reserved field according to the average bandwidth utilization to generate a bandwidth status code; the bandwidth status code includes 00, 01, 10, and 11;

[0020] A 4-bit binary number is generated based on the CPU status code and the bandwidth status code.

[0021] In an exemplary embodiment of the present disclosure, the binary number includes a fourth bit, a third bit, a second bit and a first bit arranged in sequence; the two code values ​​of the CPU status code occupy the fourth bit and the second bit respectively, and the two code values ​​of the bandwidth status code occupy the third bit and the first bit respectively.

[0022] In an exemplary embodiment of the present disclosure, when the average CPU utilization is 0-A1, the CPU status code is 00; when the average CPU utilization is A1-A2, the CPU status code is 01; when the average CPU utilization is A2-A3, the CPU status code is 10; when the average CPU utilization is A3-100%, the CPU status code is 11; wherein, 0<A1<A2<A3<100%.

[0023] In an exemplary embodiment of the present disclosure, when the average bandwidth utilization is 0-B1, the bandwidth status code is 00; when the average bandwidth utilization is B1-B2, the bandwidth status code is 01; when the average bandwidth utilization is B2-B3, the bandwidth status code is 10; when the average bandwidth utilization is B3-100%, the bandwidth status code is 11; wherein, 0<B1<B2<B3<100%.

[0024] In an exemplary embodiment of the present disclosure, the slave clock determines the stable state of the master clock based on the update synchronization message; comprising:

[0025] The slave clock obtains the binary number in the update synchronization message;

[0026] Convert the binary number into decimal to obtain a stability coefficient n;

[0027] Based on the stability coefficient n, a stable state of the master clock is determined, where the stable state includes a trusted state, a busy state, an untrusted state, and a high-risk state.

[0028] In an exemplary embodiment of the present disclosure, determining the stability state of the master clock based on the stability coefficient n includes:

[0029] When n is 0 to C1, the master clock is in a trusted state; when n is C1 to C2, the master clock is in a busy state; when n is C2 to C3, the master clock is in an untrusted state; when n is C3 to 15, the master clock is in a high-risk state; where 0 <C1<C2<C3<15。

[0030] In an exemplary embodiment of the present disclosure, the slave clock performs crystal oscillator adjustment based on the stable state of the master clock, including:

[0031] When the master clock is in a trusted state, the slave clock adjusts the crystal oscillator once according to (n+2) synchronization message cycles;

[0032] When the master clock is in a busy state, the slave clock adjusts the crystal oscillator once according to 2n synchronization message cycles;

[0033] When the master clock is in an untrusted state, the slave clock calculates the time deviation value between the slave clock and the master clock within a preset synchronization message period; determines whether the time deviation value is less than a pre-configured acceptable deviation value; if not, does not perform crystal oscillator adjustment until a preset waiting time is reached, and reacquires the stable state of the master clock; if so, determines whether the next time deviation value is less than the acceptable deviation value, until the preset time deviation values ​​are all less than the acceptable deviation value, and the slave clock performs crystal oscillator adjustment in a busy state;

[0034] When the master clock is in a high-risk state, the slave clock does not perform crystal oscillator adjustment.

[0035] In a second aspect of the present disclosure, a method for implementing clock synchronization is provided, which is applied to a slave clock and includes:

[0036] receiving an update synchronization message, wherein the update synchronization message is obtained by the master clock after processing the synchronization message based on the congestion parameter of the master clock, and the congestion parameter includes an average CPU utilization rate within a predetermined time and an average bandwidth utilization rate reaching an output interface of a slave clock device;

[0037] Determining a stable state of the master clock based on the update synchronization message;

[0038] The crystal oscillator is adjusted according to the stable state of the master clock.

[0039] In a third aspect of the present disclosure, a device for implementing clock synchronization is provided, which is applied to a master clock and includes:

[0040] An acquisition module, used for acquiring congestion parameters of the master clock, wherein the congestion parameters include an average CPU utilization rate within a predetermined time and an average bandwidth utilization rate reaching an output interface of a slave clock device;

[0041] An update module, configured to process the synchronization message based on the congestion parameter to obtain a sync update message;

[0042] The sending module is used to send the update synchronization message to the slave clock, so that the slave clock determines the stable state of the master clock according to the update synchronization message, and performs crystal oscillator adjustment based on the stable state.

[0043] In a fourth aspect of the present disclosure, a device for implementing clock synchronization is provided, which is applied to a slave clock, and includes:

[0044] A receiving module, configured to receive an update synchronization message, wherein the synchronization update message is obtained by the master clock after processing the synchronization message based on the congestion parameter of the master clock, wherein the congestion parameter includes an average CPU utilization rate within a predetermined time and an average bandwidth utilization rate reaching an output interface of a slave clock device;

[0045] A steady state determination module, configured to determine a steady state of the master clock based on the update synchronization message;

[0046] The crystal oscillator adjustment module is used to adjust the crystal oscillator according to the stable state of the main clock.

[0047] In a fifth aspect of the present disclosure, an electronic device is provided, including:

[0048] Processor; and

[0049] A memory, configured to store executable instructions of the processor;

[0050] The processor is configured to execute any one of the methods for implementing clock synchronization as described above by executing the executable instructions.

[0051] In a sixth aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the method for realizing clock synchronization as described in any one of the above items is implemented.

[0052] The method, apparatus, device, and storage medium for implementing clock synchronization provided by the embodiments of the present disclosure processes the synchronization message of the master clock based on the average CPU utilization rate within the predetermined time of the master clock and the average bandwidth utilization rate reaching the output interface of the slave clock device to obtain an updated synchronization message. The updated synchronization message is notified to the slave time, so that the slave clock can determine the stable state of the master clock, that is, determine the CPU state of the master clock and the link bandwidth occupancy. After the slave clock obtains the stable state of the master clock, the corresponding crystal oscillator adjustment is performed according to the stable state of the master clock, and there is no need to constantly judge the crystal oscillator time interval of the master-slave system, so the resource consumption is lower and the reliability is strong.

[0053] Furthermore, the slave clock adjusts the crystal oscillator according to different adjustment cycles according to different stable states, and reduces or even stops the crystal oscillator adjustment of the slave clock when the system is busy or the port utilization is high, which reduces resource consumption, increases time accuracy, and improves reliability.

[0054] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0056] Figure 1 A schematic diagram showing the message interaction sequence of the PTP protocol in the prior art;

[0057] Figure 2 A flowchart showing a method for implementing clock synchronization in one embodiment of the present disclosure is shown;

[0058] Figure 3 A flow chart showing the process of determining the stable state of the master clock from the slave clock in the embodiment of the present disclosure;

[0059] Figure 4 A flow chart showing the crystal oscillator adjustment of the slave clock according to the stable state of the master clock in the embodiment of the present disclosure is shown;

[0060] Figure 5 A flowchart of a method for implementing clock synchronization in a specific application scenario of an embodiment of the present disclosure is shown;

[0061] Figure 6 A flowchart showing a method for implementing clock synchronization in another embodiment of the present disclosure is shown;

[0062] Figure 7 A structural diagram showing a device for implementing clock synchronization in one embodiment of the present disclosure; and

[0063] Figure 8 A structural diagram of a device for implementing clock synchronization in another embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0064] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and to fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0065] In addition, the accompanying drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0066] The existing 1588 clock synchronization protocol requires constant judgment of the crystal oscillator time interval of the master and slave systems, which occupies a large amount of equipment resources. When the master clock CPU is high or the link bandwidth occupancy rate is high or even congestion and packet loss occurs, it will lead to low time accuracy and unstable time signal. Based on this, the present disclosure provides a method for realizing clock synchronization to improve the time synchronization accuracy and enhance the stability and reliability of the network.

[0067] Figure 2 A flow chart of a method 200 for implementing clock synchronization in an embodiment of the present disclosure is shown. Figure 2 As shown, a method 200 for implementing clock synchronization applied to a master clock includes:

[0068] Step S210, obtaining congestion parameters of the master clock, wherein the congestion parameters include an average CPU utilization rate within a predetermined time and an average bandwidth utilization rate reaching an output interface of a slave clock device;

[0069] Step S220, processing the synchronization message based on the congestion parameter to obtain an update synchronization message;

[0070] Step S230, sending the update synchronization message to the slave clock, so that the slave clock determines the stable state of the master clock according to the update synchronization message, and performs crystal oscillator adjustment based on the stable state.

[0071] The method for realizing clock synchronization processes the synchronization message of the master clock based on the average CPU utilization rate within the predetermined time of the master clock and the average bandwidth utilization rate reaching the output interface of the slave clock device to obtain an updated synchronization message. The updated synchronization message notifies the slave time, so that the slave clock can determine the stable state of the master clock, that is, determine the CPU state and link bandwidth occupancy of the master clock. After the slave clock obtains the stable state of the master clock, the corresponding crystal oscillator adjustment is performed according to the stable state of the master clock, and there is no need to judge the crystal oscillator time interval of the master-slave system all the time, so the resource consumption is lower and the reliability is strong.

[0072] In the following, each step of the method for implementing clock synchronization in the exemplary embodiment of the present disclosure will be described in more detail with reference to the accompanying drawings and embodiments.

[0073] In step S210, the congestion parameters of the master clock are obtained, and the congestion parameters include the average CPU utilization within a predetermined time and the average bandwidth utilization reaching the output interface of the slave clock device. The predetermined period can be, for example, 1 minute, 2 minutes, 5 minutes, etc., and the present disclosure does not impose specific restrictions. By obtaining the average CPU utilization and the average bandwidth utilization within a certain period of time, the busyness of the device resources of the master clock is characterized.

[0074] In step S220, based on the congestion parameter, the synchronization message (Sync message) is processed to obtain an update synchronization message.

[0075] For ease of understanding, the following briefly describes the Sync message structure.

[0076] In the PTP protocol, the structure of the Sync message is shown in Table 1. The data content of the Sync message consists of a header and an originTimestamp field.

[0077] Table 1

[0078]

[0079] The definitions of the various fields of the header in Table 1 are shown in Table 2. The header includes a messageLength (message length) field, a domainNumber (domain name) field, a reserved (reserved) field, a flagField (flag field) field, and the like.

[0080] Table 2

[0081]

[0082] In an embodiment of the present disclosure, step S220 specifically includes:

[0083] Step S221, obtaining a reserved field in the synchronization message.

[0084] In an embodiment of the present disclosure, a reserved field between the domainNumber field and the flagField field in the Sync message is obtained.

[0085] Step S222: Based on the congestion parameter, the reserved field is modified according to a preset conversion rule to obtain a binary number. Specifically, the lower four bits of the reserved field are modified to obtain a 4-bit binary number.

[0086] In the embodiment of the present disclosure, the preset conversion rule modifies the reserved field, including:

[0087] The reserved field is modified according to the CPU average utilization to generate a CPU status code, where the CPU status code includes 00, 01, 10, and 11.

[0088] In one embodiment of the present disclosure, when the average CPU utilization is 0 to A1, the CPU status code is 00; when the average CPU utilization is A1 to A2, the CPU status code is 01; when the average CPU utilization is A2 to A3, the CPU status code is 10; when the average CPU utilization is A3 to 100%, the CPU status code is 11; wherein, 0<A1<A2<A3<100%. It is understandable that A1, A2 and A3 can be set according to different requirements. For example, A1 is 30%, A2 is 60%, A3 is 80%, etc., and the present disclosure does not make specific restrictions.

[0089] The reserved field is modified according to the average bandwidth utilization to generate a bandwidth status code; the bandwidth status code includes 00, 01, 10, and 11.

[0090] In one embodiment of the present disclosure, when the average bandwidth utilization is 0 to B1, the bandwidth status code is 00; when the average bandwidth utilization is B1 to B2, the bandwidth status code is 01; when the average bandwidth utilization is B2 to B3, the bandwidth status code is 10; when the average bandwidth utilization is B3 to 100%, the bandwidth status code is 11; wherein, 0<B1<B2<B3<100%. It is understandable that B1, B2 and B3 can be set according to different requirements. For example, B1 is 50%, B2 is 70%, B3 is 90%, etc., and the present disclosure does not make specific restrictions.

[0091] A 4-bit binary number is generated based on the CPU status code and the bandwidth status code. Specifically, in one embodiment of the present disclosure, the binary number includes a fourth bit, a third bit, a second bit, and a first bit arranged in sequence; the two code values ​​of the CPU status code occupy the fourth bit and the second bit respectively, and the two code values ​​of the bandwidth status code occupy the third bit and the first bit respectively.

[0092] Step S223: Generate an update synchronization message based on the binary number. Specifically, in the update synchronization message, the lower four bits of the reserved field between the domainNumber field and the flagField field are the binary number obtained in step S220.

[0093] Through the above conversion rules, different status codes are used to represent different stable states of the master clock, and can be transmitted to the slave clock through the Sync message. The higher the average CPU utilization and the average bandwidth utilization, the larger the modified binary value. The average CPU utilization is associated with the fourth bit and the second bit, and the average bandwidth utilization is associated with the third bit and the first bit. The setting of two status codes is more conducive to reflecting the congestion state of the master clock, and because the CPU utilization has a greater impact on the clock synchronization accuracy, the above setting can give the CPU average utilization a higher weight.

[0094] In step S130, the update synchronization message is sent to the slave clock, so that the slave clock determines the stable state of the master clock according to the update synchronization message, and performs crystal oscillator adjustment based on the stable state.

[0095] See also Figure 3 In one embodiment of the present disclosure, the slave clock determines the stable state of the master clock based on the update synchronization message, specifically including:

[0096] Step S310, the slave clock obtains the binary number in the update synchronization message;

[0097] Step S320, convert the binary number into decimal to obtain a stability coefficient n. For example, when the binary number is 1100, the stability coefficient n is 9. The maximum value of the stability coefficient n is 15, and the minimum value is 0.

[0098] Step S330: determining the stable state of the master clock based on the stability coefficient n, wherein the stable state includes a trusted state, a busy state, an untrusted state, and a high-risk state.

[0099] In one embodiment of the present disclosure, step S330 specifically includes:

[0100] When n is 0 to C1, the master clock is in a trusted state; when n is C1 to C2, the master clock is in a busy state; when n is C2 to C3, the master clock is in an untrusted state; when n is C3 to 15, the master clock is in a high-risk state; where 0 <C1<C2<C3<15。

[0101] It is understandable that C1, C2 and C3 can be set according to different requirements, and the present disclosure does not impose specific limitations. For example, in one embodiment, C1 is 3, C2 is 8, and C3 is 11. When n≤3, the master clock is in a stable state; when 3<n<8, the master clock is in a busy state; when 8≤n≤11, the master clock is in an untrustworthy state; when 11<n≤15, the master clock is in a high-risk state.

[0102] See also Figure 4 In one embodiment of the present disclosure, the slave clock performs crystal oscillator adjustment based on the stable state of the master clock, specifically including:

[0103] Step S410, when the master clock is in a trusted state, the slave clock adjusts the crystal oscillator once according to (n+2) Sync message cycles. Specifically, the Sync message cycle is generally 1s or 2s. When the master clock is determined to be in a trusted state, the slave clock considers that the master clock time is accurate and reliable, and adjusts the crystal oscillator once according to (n+2) Sync message cycles. For example, when n is 1, the crystal oscillator is adjusted once every 3 Sync message cycles; when n is 2, the crystal oscillator is adjusted once every 4 Sync message cycles.

[0104] Step S420: When the master clock is in a busy state, the slave clock adjusts the crystal oscillator once according to 2n Sync message cycles.

[0105] Furthermore, in one embodiment of the present disclosure, when the master clock is in a busy state, when adjusting the crystal oscillator, it also includes: determining whether the time deviation between the slave clock and the master clock is greater than a preset value x, if not, the slave clock adjusts the crystal oscillator once according to 2n Sync message cycles; if so, the slave clock does not adjust the crystal oscillator and waits for the next adjustment cycle.

[0106] For example, if n=4, if the preset value x is 30μs, and the calculated time deviation between the slave clock and the master clock is 20μs, the slave clock adjusts the crystal oscillator once every 8 Sync message cycles. For another example, if n=5, if the preset value x is 30μs, and the calculated time deviation between the slave clock and the master clock is 40μs, the slave clock does not adjust the crystal oscillator, waits for the next adjustment cycle, and adjusts the crystal oscillator according to the stability coefficient of the next cycle.

[0107] Step S430, when the master clock is in an untrusted state, the slave clock calculates the time deviation value between the slave clock and the master clock within a preset synchronization message period; determines whether the time deviation value is less than a pre-configured acceptable deviation value; if not, does not perform crystal oscillator adjustment until a preset waiting time is reached, and reacquires the stable state of the master clock; if so, determines whether the next time deviation value is less than the acceptable deviation value, until the preset time deviation values ​​are all less than the acceptable deviation value, and the slave clock performs crystal oscillator adjustment in a busy state.

[0108] When the master clock is in an untrusted state, it means that the master clock CPU is high and the link is congested, and the time accuracy may be low. The preset synchronization message period can be, for example, 5 Sync message periods, 10 Sync message periods, etc., and the present disclosure does not make specific restrictions. The preset waiting time can be, for example, 5 minutes, 10 minutes, etc., and the present disclosure does not make specific restrictions.

[0109] Specifically, until the preset time deviation values ​​are all smaller than the acceptable deviation value, the slave clock performs crystal oscillator adjustment in a busy state. For example, it may be that two consecutive time deviation values ​​are smaller than the pre-configured acceptable deviation value, the slave clock performs crystal oscillator adjustment in a busy state; or three consecutive time deviation values ​​are smaller than the pre-configured acceptable deviation value, the slave clock performs crystal oscillator adjustment in a busy state, and the present disclosure does not impose specific limitations.

[0110] For example, in one embodiment, when the master clock is in an untrusted state, the slave clock calculates the time deviation value T between the slave clock and the master clock within 10 Sync message cycles. Determine whether three consecutive time deviation values ​​T are less than the pre-configured acceptable deviation value D. If so, the crystal oscillator is adjusted in a busy state (the crystal oscillator is adjusted once every 2n Sync message cycles); if not, the crystal oscillator is not adjusted, and the master clock is re-acquired in a stable state after waiting for 10 minutes. The corresponding crystal oscillator adjustment is performed according to the new stable state. The time deviation value T is shown in the following formula (1):

[0111]

[0112] In formula (1), T j is the jth time deviation value, j = 1, 2, 3, ..., j; t i is the time difference between the master clock and the slave clock in the i-th Sync message cycle, M is the average time difference between the master clock and the slave clock in 10 Sync message cycles, i=1 indicates the first Sync message cycle in which the value of the reserved field n of the Sync message is received in the range of 8≤n≤11, i=1, 2, …, 10.

[0113] The acceptable deviation value D is shown in the following formula (2):

[0114] D = x 2 (2);

[0115] In formula (2), x is an acceptable preset value configured by the user.

[0116] Get 1 -t 10 According to formula (1), we can calculate T 1 ; if T 1 Less than D, then get t 11 -t 20 , according to t 11 -t 20 Calculate T 2 ; if T 2 Less than D, then get t 21 -t 30 , according to t 21 -t 30 Calculate T 3 ; T 1 , T 2 , T 3 If both are less than D, the master clock state is considered reliable and the crystal oscillator is adjusted according to the busy state algorithm. 1 , T 2 , T 3 If any value is greater than D, the crystal oscillator adjustment is not performed. Wait for 10 minutes and repeat the above steps to check again. The crystal oscillator adjustment is then performed until the main clock becomes busy or stable.

[0117] Step S440: When the master clock is in a high-risk state, the slave clock does not perform crystal oscillator adjustment. It is not judged until the master clock changes to another state. When it is determined that the master clock is in a high-risk state, the slave clock synchronizes other clock source signals or maintains the original state to avoid network oscillation caused by unstable time signals of the next-level slave clock.

[0118] Through steps S410 to S440, the crystal oscillator adjustment cycle is confirmed by a stateful crystal oscillator adjustment algorithm, and the range of the stability coefficient n value corresponds to different master clock states and the interval of adjusting the crystal oscillator from the clock. A stateful crystal oscillator adjustment algorithm is used to determine the crystal oscillator adjustment cycle. When it is judged that the master clock state is better (for example, a trusted state, a busy state), the crystal oscillator is adjusted at a higher frequency, and when it is judged that the master clock state is worse (for example, an untrustworthy state, a high-risk state), the crystal oscillator adjustment cycle is increased, or even the crystal oscillator adjustment is stopped. Through the above-mentioned stateful crystal oscillator adjustment, when the system is busy or the port utilization rate is high, the time adjustment is reduced or even stopped, resource consumption is lower, time accuracy is higher, and reliability is strong.

[0119] See also Figure 5As shown, for ease of understanding, this embodiment uses a more specific application scenario to illustrate the process of steps S110 to S130.

[0120] Step S501 : The master clock 510 detects the average CPU utilization rate of the master clock system and the average bandwidth utilization rate reaching the output interface of the slave clock device within one minute through the detection module 511 .

[0121] Step S502: Send the average CPU utilization and the average bandwidth utilization to the Sync message processing module 512. The Sync message processing module 512 modifies the reserved field between the domainNumber field and the flagField field based on the obtained data to obtain an update synchronization message.

[0122] The modification process of the reserved field is as follows:

[0123] Bits3, bits2, bits1, and bits0 represent the last four bits of the reserved field from high to low. Bits3 and bits1 are modified according to the average CPU utilization, and bits2 and bits0 are modified according to the average bandwidth utilization.

[0124] The CPU average utilization is different, and the modification rules for bits3, bits2, bits1, and bits0 are shown in Table 3. In Table 3, “-” means no modification.

[0125] Table 3

[0126] Average CPU utilization bits3 bits2 bits1 bits0 Less than 30% 0 - 0 - Greater than or equal to 30% Less than 60% 0 - 1 - Greater than or equal to 60% Less than 80% 1 - 0 - Greater than or equal to 80% 1 - 1 -

[0127] The average bandwidth utilization is different, and the modification rules for bits3, bits2, bits1, and bits0 are shown in Table 4. In Table 4, “-” means no modification.

[0128] Table 4

[0129]

[0130]

[0131] Through the modification rules of Table 3 and Table 4, bits 3, bits 2, bits 1 and bits 0 of the reserved field are modified according to the obtained average CPU utilization and average bandwidth utilization to obtain an update synchronization message. For example, if the average CPU utilization obtained by the detection module 310 is 55% and the average bandwidth utilization is 75%, then in the update synchronization message obtained after being processed by the Sync message processing module 320, bits 3 to bits 0 of the reserved field are 0110.

[0132] Step S503 : The master clock sends an update synchronization message to the slave clock 520 .

[0133] Step S504, after receiving the update synchronization message sent by the master clock 510, the slave clock 520 determines the stability state of the master clock through the Sync message processing module 521. For example, the Sync message processing module 521 converts the stability coefficient n of the master clock to 5 according to bits 3 to bits 0 of the reserved field, and determines that the master clock is in a busy state.

[0134] Step S505, the crystal oscillator adjustment module 521 determines the crystal oscillator adjustment period based on the stable state of the master clock to perform stateful crystal oscillator adjustment. For example, n=5, the master clock is in a busy state, and the time deviation between the slave clock and the master clock is calculated to be 20μs. If the preset value x is 30μs, the slave clock adjusts the crystal oscillator once according to 10 Sync message cycles. Specifically, the crystal oscillator adjustment process includes:

[0135] S5051, determine whether the master time and the slave clock time are less than 0;

[0136] S5052, if yes, slow down the system time from the clock;

[0137] S5053: If not, speed up the system time from the clock.

[0138] Figure 6 A method 600 for implementing clock synchronization applied to a slave clock is exemplarily shown. Figure 6 As shown, the method 600 specifically includes:

[0139] Step S610, receiving an update synchronization message, wherein the update synchronization message is obtained by the master clock after processing the synchronization message based on the congestion parameter of the master clock, and the congestion parameter includes an average CPU utilization rate within a predetermined time and an average bandwidth utilization rate reaching an output interface of a slave clock device;

[0140] Step S620, determining a stable state of the master clock based on the update synchronization message;

[0141] Step S630, adjusting the crystal oscillator according to the stable state of the master clock.

[0142] The method for realizing clock synchronization processes the synchronization message of the master clock based on the average CPU utilization rate within the predetermined time of the master clock and the average bandwidth utilization rate reaching the output interface of the slave clock device to obtain an updated synchronization message. The updated synchronization message notifies the slave time, so that the slave clock can determine the stable state of the master clock, that is, determine the CPU state and link bandwidth occupancy of the master clock. After the slave clock obtains the stable state of the master clock, the corresponding crystal oscillator adjustment is performed according to the stable state of the master clock, and there is no need to judge the crystal oscillator time interval of the master-slave system all the time, so the resource consumption is lower and the reliability is strong.

[0143] The specific process in steps S610 to S630 can refer to the specific description of each step in method 200, which will not be repeated here.

[0144] Figure 7 A device 700 for implementing clock synchronization is schematically shown, which is applied to a master clock and includes:

[0145] An acquisition module 710 is used to acquire congestion parameters of the master clock, where the congestion parameters include an average CPU utilization rate within a predetermined time and an average bandwidth utilization rate reaching an output interface of a slave clock device;

[0146] An updating module 720, configured to process the synchronization message based on the congestion parameter to obtain a sync update message;

[0147] The sending module 730 is used to send the update synchronization message to the slave clock, so that the slave clock determines the stable state of the master clock according to the update synchronization message, and performs crystal oscillator adjustment based on the stable state.

[0148] The device for realizing clock synchronization processes the synchronization message of the master clock based on the average CPU utilization rate within the predetermined time of the master clock and the average bandwidth utilization rate reaching the output interface of the slave clock device to obtain an updated synchronization message. The slave clock is notified of the updated synchronization message so that the slave clock can determine the stable state of the master clock, that is, determine the CPU state of the master clock and the link bandwidth occupancy. After the slave clock obtains the stable state of the master clock, the corresponding crystal oscillator adjustment is performed according to the stable state of the master clock, and there is no need to judge the crystal oscillator time interval of the master-slave system all the time, so the resource consumption is lower and the reliability is strong.

[0149] In one embodiment of the present disclosure, the device 700 for implementing clock synchronization may further include a module for implementing other process steps in each embodiment of the method for implementing clock synchronization. Since each function of the device 700 for implementing clock synchronization has been described in detail in its corresponding method embodiment, the present disclosure will not repeat them here.

[0150] Figure 8 A device 800 for implementing clock synchronization is schematically shown, which is applied to a slave clock and includes:

[0151] The receiving module 810 is used to receive an update synchronization message, wherein the synchronization update message is obtained by the master clock after processing the synchronization message based on the congestion parameter of the master clock, and the congestion parameter includes an average CPU utilization rate within a predetermined time and an average bandwidth utilization rate reaching the output interface of the slave clock device;

[0152] A steady state determination module 820, configured to determine a steady state of the master clock based on the update synchronization message;

[0153] The crystal oscillator adjustment module 830 is used to adjust the crystal oscillator according to the stable state of the master clock.

[0154] The device for realizing clock synchronization processes the synchronization message of the master clock based on the average CPU utilization rate within the predetermined time of the master clock and the average bandwidth utilization rate reaching the output interface of the slave clock device to obtain an updated synchronization message. The slave clock is notified of the updated synchronization message so that the slave clock can determine the stable state of the master clock, that is, determine the CPU state of the master clock and the link bandwidth occupancy. After the slave clock obtains the stable state of the master clock, the corresponding crystal oscillator adjustment is performed according to the stable state of the master clock, and there is no need to judge the crystal oscillator time interval of the master-slave system all the time, so the resource consumption is lower and the reliability is strong.

[0155] In one embodiment of the present disclosure, the device 800 for implementing clock synchronization may also include a module for implementing other process steps in each embodiment of the method for implementing clock synchronization. Since each function of the device 800 for implementing clock synchronization has been described in detail in its corresponding method embodiment, the present disclosure will not repeat it here.

[0156] It should be noted that, although several modules or units of the device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into multiple modules or units to be embodied.

[0157] In an exemplary embodiment of the present disclosure, an electronic device capable of implementing the above-mentioned method for realizing clock synchronization is also provided.

[0158] It will be appreciated by those skilled in the art that various aspects of the present invention may be implemented as a system, method or program product. Therefore, various aspects of the present invention may be specifically implemented in the following forms, namely: a complete hardware implementation, a complete software implementation (including firmware, microcode, etc.), or a combination of hardware and software, which may be collectively referred to herein as a "circuit", "module" or "system".

[0159] The electronic device is in the form of a general-purpose computing device. The components of the electronic device may include, but are not limited to: the at least one processing unit, the at least one storage unit, and a bus connecting different system components (including the storage unit and the processing unit).

[0160] The storage unit stores program code, which can be processed by the processor

[0161] The processing unit executes so that the processing unit executes the steps according to various exemplary embodiments of the present invention described in the above “Exemplary Method” section of this specification. For example, the processing unit may execute the following steps: Figure 2 In step S210 shown in the figure, congestion parameters of the master clock are obtained, and the congestion parameters include the average CPU utilization within a predetermined time and the average bandwidth utilization reaching the output interface of the slave clock device; in step S220, the synchronization message is processed based on the congestion parameters to obtain an update synchronization message; in step S230, the update synchronization message is sent to the slave clock, so that the slave clock determines the stable state of the master clock according to the updated synchronization message, and adjusts the crystal oscillator based on the stable state.

[0162] The processing unit may perform the following Figure 6 In step S610 shown in the figure, an update synchronization message is received, wherein the update synchronization message is obtained by the master clock after processing the synchronization message based on the congestion parameters of the master clock, and the congestion parameters include the average CPU utilization within a predetermined time and the average bandwidth utilization reaching the output interface of the slave clock device; in step S620, a stable state of the master clock is determined based on the update synchronization message; in step S630, a crystal oscillator is adjusted according to the stable state of the master clock.

[0163] The storage unit may include a readable medium in the form of a volatile memory unit, such as a random access memory unit (RAM) and / or a cache memory unit, and may further include a read-only memory unit (ROM).

[0164] The storage unit may also include a program / utility having a set (at least one) of program modules, such program modules including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0165] The bus may represent one or more of several types of bus structures, including a memory unit bus or memory unit controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

[0166] The electronic device can also communicate with one or more external devices (such as keyboards, pointing devices, Bluetooth devices, etc.), and can also communicate with one or more devices that enable users to interact with the electronic device, and / or communicate with any device (such as routers, modems, etc.) that enables the electronic device to communicate with one or more other computing devices. This communication can be carried out through an input / output (I / O) interface. In addition, the electronic device can also communicate with one or more networks (such as local area networks (LANs), wide area networks (WANs) and / or public networks, such as the Internet) through a network adapter. As shown in the figure, the network adapter communicates with other modules of the electronic device through a bus. It should be understood that, although not shown in the figure, other hardware and / or software modules can be used in conjunction with the electronic device, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, etc.

[0167] Through the description of the above implementation, it is easy for those skilled in the art to understand that the example implementation described here can be implemented by software, or by software combined with necessary hardware. Therefore, the technical solution according to the implementation of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, including several instructions to enable a computing device (which can be a personal computer, a server, a terminal device, or a network device, etc.) to execute the method according to the implementation of the present disclosure.

[0168] In an exemplary embodiment of the present disclosure, a computer-readable storage medium is also provided, on which a program product capable of implementing the above method of the present specification is stored. In some possible implementations, various aspects of the present invention can also be implemented in the form of a program product, which includes a program code, and when the program product is run on a terminal device, the program code is used to enable the terminal device to execute the steps according to various exemplary embodiments of the present invention described in the above "Exemplary Method" section of the present specification.

[0169] A program product for implementing the above method according to an embodiment of the present invention is described, which can adopt a portable compact disk read-only memory (CD-ROM) and include program code, and can be run on a terminal device, such as a personal computer. However, the program product of the present invention is not limited thereto, and in this document, a readable storage medium can be any tangible medium containing or storing a program, which can be used by or in combination with an instruction execution system, an apparatus or a device.

[0170] The program product may use any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0171] Computer readable signal media may include data signals propagated in baseband or as part of a carrier wave, in which readable program code is carried. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Readable signal media may also be any readable medium other than a readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0172] The program code embodied on the readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wired, optical cable, RF, etc., or any suitable combination of the foregoing.

[0173] Program code for performing the operations of the present invention may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving a remote computing device, the remote computing device may be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., through the Internet using an Internet service provider).

[0174] It should be noted that, although several modules or units of the device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into multiple modules or units to be embodied.

[0175] In addition, although the steps of the method in the present disclosure are described in a specific order in the drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0176] Through the description of the above implementation, it is easy for those skilled in the art to understand that the example implementation described here can be implemented by software, or by software combined with necessary hardware. Therefore, the technical solution according to the implementation of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, including several instructions to enable a computing device (which can be a personal computer, a server, a mobile terminal, or a network device, etc.) to execute the method according to the implementation of the present disclosure.

[0177] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A method for clock synchronization, applied to a master clock, characterized in that: include: Acquire congestion parameters of the master clock, where the congestion parameters include an average CPU utilization rate within a predetermined time and an average bandwidth utilization rate reaching an output interface of a slave clock device; Based on the congestion parameter, the synchronization message is processed to obtain an update synchronization message; Sending the update synchronization message to the slave clock, so that the slave clock determines the stable state of the master clock according to the update synchronization message, and performs crystal oscillator adjustment based on the stable state, wherein the stable state includes a trusted state, a busy state, an untrusted state, and a high-risk state; The crystal oscillator adjustment based on the stable state includes: when the master clock is in a trusted state, the slave clock adjusts the crystal oscillator once according to (n+2) synchronization message cycles; When the master clock is in a busy state, the slave clock adjusts the crystal oscillator once according to 2n synchronization message cycles; The above n is the stability coefficient; When the master clock is in an untrusted state, the slave clock calculates a time deviation value between the slave clock and the master clock within a preset synchronization message period; and determines, based on the time deviation, whether the slave clock performs crystal oscillator adjustment in a busy state or does not perform crystal oscillator adjustment; When the master clock is in a high-risk state, the slave clock does not perform crystal oscillator adjustment.

2. The method for realizing clock synchronization according to claim 1, characterized in that: Based on the congestion parameter, the synchronization message is processed to obtain an update synchronization message, including: Obtaining a reserved field in the synchronization message; Based on the congestion parameter, modify the reserved field according to a preset conversion rule to obtain a binary number; Based on the binary number, an update synchronization message is generated.

3. The method for realizing clock synchronization according to claim 2, characterized in that: The step of modifying the reserved field based on the congestion parameter according to a preset conversion rule to obtain a binary number includes: Modify the reserved field according to the CPU average utilization to generate a CPU status code, where the CPU status code includes 00, 01, 10, and 11; Modify the reserved field according to the average bandwidth utilization to generate a bandwidth status code; the bandwidth status code includes 00, 01, 10, and 11; A 4-bit binary number is generated based on the CPU status code and the bandwidth status code.

4. The method for realizing clock synchronization according to claim 3, characterized in that: The binary number includes a fourth bit, a third bit, a second bit and a first bit arranged in sequence; the two code values ​​of the CPU status code occupy the fourth bit and the second bit respectively, and the two code values ​​of the bandwidth status code occupy the third bit and the first bit respectively.

5. The method for realizing clock synchronization according to claim 3, characterized in that: When the average CPU utilization is 0-A1, the CPU status code is 00; when the average CPU utilization is A1-A2, the CPU status code is 01; when the average CPU utilization is A2-A3, the CPU status code is 10; when the average CPU utilization is A3-100%, the CPU status code is 11; wherein, 0<A1<A2<A3<100%.

6. The method for realizing clock synchronization according to claim 3, characterized in that: When the average bandwidth utilization is 0 to B1, the bandwidth status code is 00; when the average bandwidth utilization is B1 to B2, the bandwidth status code is 01; when the average bandwidth utilization is B2 to B3, the bandwidth status code is 10; when the average bandwidth utilization is B3 to 100%, the bandwidth status code is 11; wherein, 0<B1<B2<B3<100%.

7. The method for realizing clock synchronization according to any one of claims 2 to 6, characterized in that: The slave clock determines the stable state of the master clock based on the update synchronization message; comprising: The slave clock obtains the binary number in the update synchronization message; Convert the binary number into decimal to obtain a stability coefficient n; Based on the stability factor n, a stability state of the master clock is determined.

8. The method for realizing clock synchronization according to claim 7, characterized in that: Determining a stable state of the master clock based on the stability coefficient n includes: When n is 0 to C1, the master clock is in a trusted state; when n is C1 to C2, the master clock is in a busy state; when n is C2 to C3, the master clock is in an untrusted state; when n is C3 to 15, the master clock is in a high-risk state; where 0 <C1<C2<C3<15。 9. The method for realizing clock synchronization according to claim 7, characterized in that: The slave clock performs crystal oscillator adjustment based on the stable state of the master clock, including: Determine whether the time deviation value is less than a pre-configured acceptable deviation value; if not, do not perform crystal oscillator adjustment until the preset waiting time is reached, and re-acquire the stable state of the master clock; if so, determine whether the next time deviation value is less than the acceptable deviation value, until the preset time deviation values ​​are all less than the acceptable deviation value, and the slave clock performs crystal oscillator adjustment in a busy state.

10. A method for implementing clock synchronization, applied to a slave clock, characterized in that: include: receiving an update synchronization message, wherein the update synchronization message is obtained by the master clock after processing the synchronization message based on the congestion parameter of the master clock, and the congestion parameter includes an average CPU utilization rate within a predetermined time and an average bandwidth utilization rate reaching an output interface of a slave clock device; Determining a stable state of the master clock based on the update synchronization message; Performing crystal oscillator adjustment according to the stable state of the master clock, wherein the stable state includes a trusted state, a busy state, an untrusted state, and a high-risk state; Wherein, adjusting the crystal oscillator according to the stable state of the master clock includes: when the master clock is in a trusted state, the slave clock adjusts the crystal oscillator once according to (n+2) synchronization message cycles; When the master clock is in a busy state, the slave clock adjusts the crystal oscillator once according to 2n synchronization message cycles; The above n is the stability coefficient; When the master clock is in an untrusted state, the slave clock calculates a time deviation value between the slave clock and the master clock within a preset synchronization message period; and determines, based on the time deviation, whether the slave clock performs crystal oscillator adjustment in a busy state or does not perform crystal oscillator adjustment; When the master clock is in a high-risk state, the slave clock does not perform crystal oscillator adjustment.

11. A device for realizing clock synchronization, applied to a master clock, characterized in that: include: An acquisition module, used for acquiring congestion parameters of the master clock, wherein the congestion parameters include an average CPU utilization rate within a predetermined time and an average bandwidth utilization rate reaching an output interface of a slave clock device; An updating module, configured to process the synchronization message based on the congestion parameter to obtain an updated synchronization message; A sending module, used for sending the update synchronization message to the slave clock, so that the slave clock determines the stable state of the master clock according to the update synchronization message, and performs crystal oscillator adjustment based on the stable state, wherein the stable state includes a trusted state, a busy state, an untrusted state and a high-risk state; The crystal oscillator adjustment based on the stable state includes: when the master clock is in a trusted state, the slave clock adjusts the crystal oscillator once according to (n+2) synchronization message cycles; When the master clock is in a busy state, the slave clock adjusts the crystal oscillator once according to 2n synchronization message cycles; The above n is the stability coefficient; When the master clock is in an untrusted state, the slave clock calculates a time deviation value between the slave clock and the master clock within a preset synchronization message period; and determines, based on the time deviation, whether the slave clock performs crystal oscillator adjustment in a busy state or does not perform crystal oscillator adjustment; When the master clock is in a high-risk state, the slave clock does not perform crystal oscillator adjustment.

12. A device for implementing clock synchronization, applied to a slave clock, characterized in that: include: A receiving module, configured to receive an update synchronization message, wherein the synchronization update message is obtained by the master clock after processing the synchronization message based on the congestion parameter of the master clock, wherein the congestion parameter includes an average CPU utilization rate within a predetermined time and an average bandwidth utilization rate reaching an output interface of a slave clock device; A steady state determination module, configured to determine a steady state of the master clock based on the update synchronization message; A crystal oscillator adjustment module, used for adjusting the crystal oscillator according to the stable state of the master clock, wherein the stable state includes a trusted state, a busy state, an untrusted state and a high-risk state; Wherein, adjusting the crystal oscillator according to the stable state of the master clock includes: when the master clock is in a trusted state, the slave clock adjusts the crystal oscillator once according to (n+2) synchronization message cycles; When the master clock is in a busy state, the slave clock adjusts the crystal oscillator once according to 2n synchronization message cycles; The above n is the stability coefficient; When the master clock is in an untrusted state, the slave clock calculates a time deviation value between the slave clock and the master clock within a preset synchronization message period; and determines, based on the time deviation, whether the slave clock performs crystal oscillator adjustment in a busy state or does not perform crystal oscillator adjustment; When the master clock is in a high-risk state, the slave clock does not perform crystal oscillator adjustment.

13. An electronic device, characterized in that: include: processor; as well as A memory, configured to store executable instructions of the processor; The processor is configured to execute the method for implementing clock synchronization according to any one of claims 1 to 10 by executing the executable instructions.

14. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method for realizing clock synchronization according to any one of claims 1 to 10 is implemented.

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