Gate driving circuit and display panel

Abstract

The present application discloses a gate driving circuit and a display panel. The gate driving circuit includes a plurality of cascaded gate driving units. Each gate driving unit includes a pull-up control module, an inverter module, and a feedback module. By stepwise raising the potential of the pull-up node through the pull-up control module, the inverter module can control the feedback module to turn off when the potential of the pull-up node is relatively low, improving the phenomenon of leakage of the pull-up node through the feedback module.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to a gate driving circuit and a display panel. Background Art

[0002] In each gate driving unit of a gate driving circuit, the potential of a pull-up node is usually raised by a pull-up control module. However, since the output potential of the pull-up control module is usually constant, the potential of the pull-up node rises relatively fast, resulting in leakage of the pull-up node. Summary of the Invention

[0003] This application provides a gate driving circuit and a display panel to alleviate the technical problem of leakage of the pull-up node.

[0004] In a first aspect, this application provides a gate driving circuit. The gate driving circuit includes a plurality of cascaded gate driving units. Each gate driving unit includes a pull-up control module, an inverting module, and a feedback module. The output terminal of the pull-up control module is connected to the pull-up node and is used to stepwise raise the potential of the pull-up node. The input terminal of the inverting module is connected to the pull-up node and is used to output an anti-leakage control signal in response to the rise of the potential of the pull-up node. The control terminal of the feedback module is connected to the output terminal of the inverting module. One end of the feedback module is connected to the pull-up node, and the other end of the feedback module is connected to a first low-potential line and is used to reduce the leakage from the pull-up node to the first low-potential line in response to the anti-leakage control signal.

[0005] In some embodiments, the pull-up node is used to provide a pull-up control signal. The pull-up control signal includes at least one stepped pulse. Each stepped pulse includes a first potential pulse and a second potential pulse that are sequentially connected. The potential of the first potential pulse is lower than the potential of the second potential pulse.

[0006]

[0007] In some embodiments, each stepped pulse further includes a third potential pulse that follows the second potential pulse. The potential of the second potential pulse is lower than the potential of the third potential pulse.

[0008] In some embodiments, the pull-up control module includes a pull-up control transistor. One of the source / drain of the pull-up control transistor is connected to the J-th scan line, the gate of the pull-up control transistor is connected to the J-th cascade line, and the other of the source / drain of the pull-up control transistor is connected to the pull-up node. Wherein, the J-th scan line is used to transmit the J-th scan signal with a front chamfer, and the J-th cascade line is used to transmit the J-th cascade signal with a front chamfer.In some of these embodiments, the gate driving unit further includes a pull-up transistor and a cascading transistor. One of the source / drain of the pull-up transistor is connected to the Nth-level clock line, the gate of the pull-up transistor is connected to the pull-up node, and the other of the source / drain of the pull-up transistor is connected to the Nth-level scan line; One of the source / drain of the cascading transistor is connected to the Nth-level clock line, the gate of the cascading transistor is connected to the pull-up node, and the other of the source / drain of the cascading transistor is connected to the Nth-level cascading line; wherein, the Nth-level clock line is used to transmit the Nth-level clock signal with a front chamfer; the Nth-level scan line is used to transmit the Nth-level scan signal with a front chamfer, the waveform of the Nth-level scan signal is the same as that of the Jth-level scan signal and the phase of the Nth-level scan signal lags behind the phase of the Jth-level scan signal; the waveform of the Nth-level cascading signal is the same as that of the Jth-level cascading signal and the phase of the Nth-level cascading signal lags behind the phase of the Jth-level cascading signal.

[0009] In some of these embodiments, the starting moment of the front chamfer is the same as the starting moment of the rising edge of the Nth-level clock signal in terms of timing, and the ratio of the duration of the front chamfer to the pulse duration of the Nth-level clock signal is greater than or equal to 1 / 4 and less than or equal to 1 / 3.

[0010] In some of these embodiments, the potential of the front chamfer is greater than or equal to 1 / 3 and less than or equal to 2 / 3 of the pulse amplitude of the Nth-level clock signal.

[0011] In some of these embodiments, the potential of the front chamfer is 1 / 2 of the pulse amplitude of the Nth-level clock signal.

[0012] In some of these embodiments, the inverting module includes a first inverting sub-module. The first inverting sub-module includes a first transistor, a second transistor, a third transistor, and a fourth transistor. One of the source / drain of the first transistor is connected to one of the source / drain of the first low-frequency control line, the second transistor, and the gate of the first transistor. The other of the source / drain of the first transistor is connected to the gate of the second transistor and one of the source / drain of the third transistor. The other of the source / drain of the second transistor is connected to one of the source / drain of the fourth transistor. The gate of the third transistor is connected to the pull-up node and the gate of the fourth transistor. The first low-potential line is connected to the other of the source / drain of the third transistor and the other of the source / drain of the fourth transistor; The feedback module includes a first feedback transistor. One of the source / drain of the first feedback transistor is connected to the pull-up node. The gate of the first feedback transistor is connected to the other of the source / drain of the second transistor and the other of the source / drain of the fourth transistor. The other of the source / drain of the first feedback transistor is connected to the first low-potential line.

[0013] In some of these embodiments, the inverting module further includes a second inverting sub-module. The second inverting sub-module includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. One of the source / drain of the fifth transistor is connected to one of the source / drain of the second low-frequency control line, the sixth transistor, and the gate of the fifth transistor. The other of the source / drain of the fifth transistor is connected to the gate of the sixth transistor and one of the source / drain of the seventh transistor. The other of the source / drain of the sixth transistor is connected to one of the source / drain of the eighth transistor. The gate of the seventh transistor is connected to the pull-up node and the gate of the eighth transistor. The first low-potential line is connected to the other of the source / drain of the seventh transistor and the other of the source / drain of the eighth transistor. The feedback module includes a second feedback transistor. One of the source / drain of the second feedback transistor is connected to the pull-up node. The gate of the second feedback transistor is connected to the other of the source / drain of the sixth transistor and one of the source / drain of the eighth transistor. The other of the source / drain of the second feedback transistor is connected to the first low-potential line.

[0014] In a second aspect, the present application provides a gate driving circuit. The gate driving circuit includes a plurality of cascaded gate driving units. Each gate driving unit includes a pull-up control transistor, a first transistor, a second transistor, a third transistor, a fourth transistor, and a first feedback transistor. One of the source / drain of the pull-up control transistor is connected to the J-th scan line. The gate of the pull-up control transistor is connected to the J-th cascade line. The other of the source / drain of the pull-up control transistor is connected to the pull-up node. One of the source / drain of the first transistor is connected to the first low-frequency control line and the gate of the first transistor. One of the source / drain of the second transistor is connected to one of the source / drain of the first transistor. The gate of the second transistor is connected to the other of the source / drain of the first transistor. One of the source / drain of the third transistor is connected to the other of the source / drain of the first transistor. The gate of the third transistor is connected to the pull-up node. The other of the source / drain of the third transistor is connected to the first low-potential line. One of the source / drain of the fourth transistor is connected to the other of the source / drain of the second transistor. The gate of the fourth transistor is connected to the pull-up node. The other of the source / drain of the fourth transistor is connected to the first low-potential line. One of the source / drain of the first feedback transistor is connected to the pull-up node. The gate of the first feedback transistor is connected to the other of the source / drain of the second transistor and one of the source / drain of the fourth transistor. The other of the source / drain of the first feedback transistor is connected to the first low-potential line. Among them, the J-th scan line is used to transmit the J-th scan signal with a front chamfer, and the J-th cascade line is used to transmit the J-th cascade signal with a front chamfer.

[0015] In some of these embodiments, the gate driving unit further includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a second feedback transistor. One of the source / drain of the fifth transistor is connected to the second low-frequency control line and the gate of the fifth transistor. One of the source / drain of the sixth transistor is connected to one of the source / drain of the fifth transistor, and the gate of the sixth transistor is connected to the other of the source / drain of the fifth transistor. One of the source / drain of the seventh transistor is connected to the other of the source / drain of the fifth transistor, the gate of the seventh transistor is connected to the pull-up node, and the other of the source / drain of the seventh transistor is connected to the first low-potential line. One of the source / drain of the eighth transistor is connected to the other of the source / drain of the sixth transistor, the gate of the eighth transistor is connected to the pull-up node, and the other of the source / drain of the eighth transistor is connected to the first low-potential line. One of the source / drain of the second feedback transistor is connected to the pull-up node, the gate of the second feedback transistor is connected to the other of the source / drain of the sixth transistor and one of the source / drain of the seventh transistor, and the other of the source / drain of the second feedback transistor is connected to the first low-potential line.

[0016] In some of these embodiments, the gate driving unit further includes a pull-up transistor and a cascaded transistor. One of the source / drain of the pull-up transistor is connected to the Nth-stage clock line, the gate of the pull-up transistor is connected to the pull-up node, and the other of the source / drain of the pull-up transistor is connected to the Nth-stage scan line. One of the source / drain of the cascaded transistor is connected to the Nth-stage clock line, the gate of the cascaded transistor is connected to the pull-up node, and the other of the source / drain of the cascaded transistor is connected to the Nth-stage cascaded line. Wherein, the Nth-stage clock line is used to transmit the Nth-stage clock signal with a front chamfer; the Nth-stage scan line is used to transmit the Nth-stage scan signal with a front chamfer, the waveform of the Nth-stage scan signal is the same as that of the Jth-stage scan signal and the phase of the Nth-stage scan signal lags behind the phase of the Jth-stage scan signal; the waveform of the Nth-stage cascaded signal is the same as that of the Jth-stage cascaded signal and the phase of the Nth-stage cascaded signal lags behind the phase of the Jth-stage cascaded signal.

[0017] In a third aspect, the present application provides a display panel, which includes the gate driving circuit in at least one of the above embodiments.

[0018] The gate driving circuit and the display panel provided by the present application stepwise raise the potential of the pull-up node through the pull-up control module, reduce the potential raising speed of the pull-up node, and can control the feedback module to turn off through the inverting module when the potential of the pull-up node is low, improving the phenomenon of leakage of the pull-up node through the feedback module.

[0019] Moreover, since the leakage of the feedback module is reduced or avoided, the abnormal working phenomenon of the feedback module is improved, which is beneficial to increasing the service life of the feedback module and the charging saturation degree of the pull-up node, and further improving the working reliability of the gate driving circuit.

[0020] Moreover, since the pull-up module raises the potential of the pull-up node step by step, although it will affect the potential charging speed of the pull-up node, during the process of the gate driving circuit outputting a scanning signal to control the charging of the data signal, the effective charging time is usually located in the latter part of the pulse duration of the scanning signal. Therefore, no matter what the waveform of the former part of the pulse duration of the scanning signal is, it will not affect the effective charging time. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The technical solutions and other beneficial effects of the present application will become obvious by describing the specific embodiments of the present application in detail with reference to the accompanying drawings.

[0022] Figure 1 It is a schematic structural diagram of the gate driving circuit provided by the embodiment of the present application.

[0023] Figure 2 For Figure 1 it is a waveform schematic diagram of CK(N) under the related technology.

[0024] Figure 3 For Figure 1 it is a waveform schematic diagram of the gate driving circuit shown during the pre-charging period.

[0025] Figure 4 For Figure 2 it is a waveform schematic diagram driven by CK(N) in

[0026] Figure 5 It is a waveform schematic diagram of CK(N) provided by the embodiment of the present application.

[0027] Figure 6 For Figure 5 it is a waveform schematic diagram driven by CK(N) in DETAILED DESCRIPTION OF THE EMBODIMENTS

[0028] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0029] This embodiment provides a gate driving circuit, as Figure 1As shown, the gate driving circuit includes a plurality of cascaded gate driving units. Each gate driving unit includes a pull-up control module 30, an inverting module, and a feedback module. The output terminal of the pull-up control module 30 is connected to the pull-up node Q(N); the input terminal of the inverting module is connected to the pull-up node Q(N); the control terminal of the feedback module is connected to the output terminal of the inverting module. One end of the feedback module is connected to the pull-up node Q(N), and the other end of the feedback module is connected to the first low-potential line.

[0030] Among them, the first low-potential line is used to transmit the first low-potential signal VSSQ, and the potential of the first low-potential signal VSSQ is less than or equal to -8V, and specifically may also be -10V, -12V, -15V, -18V, -20V, -28V... and so on.

[0031] In one embodiment, the pull-up control module 30 includes a pull-up control transistor T11. One of the source / drain of the pull-up control transistor T11 is connected to the Jth scanning line, the gate of the pull-up control transistor T11 is connected to the Jth cascading line, and the other of the source / drain of the pull-up control transistor T11 is connected to the pull-up node Q(N).

[0032] Among them, the Jth scanning line is used to transmit the Jth scanning signal. The Jth cascading line is used to transmit the Jth cascading signal. J is a positive integer.

[0033] In one embodiment, the inverting module includes a first inverting sub-module 10. The first inverting sub-module 10 includes a first transistor T51, a second transistor T53, a third transistor T52, and a fourth transistor T54. One of the source / drain of the first transistor T51 is connected to one of the source / drain of the first low-frequency control line and the second transistor T53, and the gate of the first transistor T51. The other of the source / drain of the first transistor T51 is connected to the gate of the second transistor T53 and one of the source / drain of the third transistor T52. The other of the source / drain of the second transistor T53 is connected to one of the source / drain of the fourth transistor T54. The gate of the third transistor T52 is connected to the pull-up node Q(N) and the gate of the fourth transistor T54. The first low-potential line is connected to the other of the source / drain of the third transistor T52 and the other of the source / drain of the fourth transistor T54.

[0034] Among them, the above-mentioned first low-frequency control line is used to transmit the first low-frequency control signal LC1.

[0035] In one embodiment, the inverting module further includes a second inverting sub-module 20. The second inverting sub-module 20 includes a fifth transistor T61, a sixth transistor T63, a seventh transistor T62, and an eighth transistor T64. One of the source / drain of the fifth transistor T61 is connected to one of the source / drain of the second low-frequency control line, the sixth transistor T63, and the gate of the fifth transistor T61. The other of the source / drain of the fifth transistor T61 is connected to the gate of the sixth transistor T63 and one of the source / drain of the seventh transistor T62. The other of the source / drain of the sixth transistor T63 is connected to one of the source / drain of the eighth transistor T64. The gate of the seventh transistor T62 is connected to the pull-up node Q(N) and the gate of the eighth transistor T64. The first low-potential line is connected to the other of the source / drain of the seventh transistor T62 and the other of the source / drain of the eighth transistor T64.

[0036] Wherein, the above-mentioned second low-frequency control line is used to transmit the second low-frequency control signal LC2.

[0037] In one embodiment, the feedback module includes a first feedback transistor T42. One of the source / drain of the first feedback transistor T42 is connected to the pull-up node Q(N). The gate of the first feedback transistor T42 is connected to the other of the source / drain of the second transistor T53 and one of the source / drain of the fourth transistor T54. The other of the source / drain of the first feedback transistor T42 is connected to the first low-potential line.

[0038] In one embodiment, the feedback module includes a second feedback transistor T43. One of the source / drain of the second feedback transistor T43 is connected to the pull-up node Q(N). The gate of the second feedback transistor T43 is connected to the other of the source / drain of the sixth transistor T63 and one of the source / drain of the eighth transistor T64. The other of the source / drain of the second feedback transistor T43 is connected to the first low-potential line.

[0039] In one embodiment, the gate driving unit further includes a pull-up transistor T21. One of the source / drain of the pull-up transistor T21 is connected to the Nth-stage clock line. The gate of the pull-up transistor T21 is connected to the pull-up node Q(N). The other of the source / drain of the pull-up transistor T21 is connected to the Nth-stage scan line.

[0040] Wherein, the Nth-stage clock line is used to transmit the Nth-stage clock signal CK(N). The Nth-stage scan line is used to transmit the Nth-stage scan signal G(N).

[0041] In one embodiment, the gate driving unit further includes a cascaded transistor T22. One of the source / drain of the cascaded transistor T22 is connected to the Nth-stage clock line, the gate of the cascaded transistor T22 is connected to the pull-up node Q(N), and the other of the source / drain of the cascaded transistor T22 is connected to the Nth-stage cascaded line.

[0042] Wherein, the Nth-stage cascaded line is used to transmit the Nth-stage cascaded signal ST(N).

[0043] In one embodiment, the gate driving unit further includes a transistor T44. One of the source / drain of the transistor T44 is connected to the other of the source / drain of the pull-up control transistor T11 and the pull-up node Q(N), the other of the source / drain of the transistor T44 is connected to the first low-potential line, and the gate of the transistor T32 is connected to the start line.

[0044] It should be noted that the start line is used to transmit a start signal STV, and the start signal STV can prohibit the gate driving circuit from providing an output signal with a pulse during the blank stage of each frame.

[0045] In one embodiment, the gate driving unit further includes a transistor T72. One of the source / drain of the transistor T72 is connected to the other of the source / drain of the cascaded transistor T22 and the Nth-stage cascaded line, the other of the source / drain of the transistor T72 is connected to the first low-potential line, and the gate of the transistor T72 is connected to one of the source / drain of the fourth transistor T54.

[0046] In one embodiment, the gate driving unit further includes a transistor T32. One of the source / drain of the transistor T32 is connected to the other of the source / drain of the pull-up transistor T21 and the Nth-stage scan line, the other of the source / drain of the transistor T32 is connected to the second low-potential line, and the gate of the transistor T32 is connected to one of the source / drain of the fourth transistor T54.

[0047] It should be noted that the second low-potential line is used to transmit a second low-potential signal VSSG.

[0048] In one embodiment, the gate driving unit further includes a capacitor Cbt. One end of the capacitor Cbt is connected to the pull-up node Q(N), and the other end of the capacitor Cbt is connected to the Nth-stage scan line.

[0049] In one embodiment, the gate driving unit further includes a transistor T73. One of the source / drain of the transistor T73 is connected to the Nth-stage cascaded line, the other of the source / drain of the transistor T73 is connected to the first low-potential line, and the gate of the transistor T73 is connected to one of the source / drain of the seventh transistor T62.

[0050] In one embodiment, the gate driving unit further includes a transistor T33. One of the source / drain of the transistor T33 is connected to the N-th scanning line, the other of the source / drain of the transistor T33 is connected to the second low potential line, and the gate of the transistor T33 is connected to one of the source / drain of the seventh transistor T62.

[0051] In one embodiment, the gate driving unit further includes a transistor T41. One of the source / drain of the transistor T41 is connected to the pull-up node Q(N), the other of the source / drain of the transistor T41 is connected to the first low potential line, and the gate of the transistor T41 is connected to the (N + 8)-th cascading line.

[0052] It should be noted that the (N + 8)-th cascading line is used to transmit the (N + 8)-th cascading signal ST(N + 8).

[0053] In one embodiment, the gate driving unit further includes a transistor T31. One of the source / drain of the transistor T31 is connected to the N-th scanning line, the other of the source / drain of the transistor T31 is connected to the second low potential line, and the gate of the transistor T31 is connected to the (N + 8)-th cascading line.

[0054] In one embodiment, each of the above transistors may be an N-channel thin film transistor, specifically an N-channel metal oxide thin film transistor. Preferably, it may also be an N-channel indium gallium zinc oxide thin film transistor.

[0055] In one embodiment, each of the above transistors may be a P-channel thin film transistor, specifically a P-channel polysilicon thin film transistor. Preferably, it may also be a P-channel low temperature polysilicon thin film transistor.

[0056] Figure 2 For Figure 1 the waveform diagram of CK(N) under the related technology. Before chamfering, the pulse amplitude and pulse duration of the N-th clock signal CK(N) are Y and T respectively. Since the N-th clock signal CK(N) is not chamfered, therefore, the J-th scanning signal and the J-th cascading signal are also not chamfered. Correspondingly, the potential rising speed of the pull-up control module 30 for the pull-up node Q(N) remains constant and will not change.

[0057] Figure 3 For Figure 1Schematic diagram of the waveform of the shown gate drive circuit during pre-charging. Before T1 during pre-charging, since the potential of the pull-up node Q(N) is at a low potential, the potential of the gate of the first feedback transistor T42, i.e., the potential of the K / P node, is at a high potential; during T1 of pre-charging, the pull-up control module 30 starts to charge the pull-up node Q(N). Since the potential change trends of the pull-up node Q(N) and the K / P node are opposite, the voltage at which the potentials of the pull-up node Q(N) and the K / P node are equal is defined as the overlap voltage OVLV.

[0058] It can be understood that the lower the overlap voltage OVLV, the lower the potential of the pull-up node Q(N) when the feedback module is turned off. And the lower the potential of the pull-up node Q(N), the smaller the voltage difference between the pull-up node Q(N) and the first low-potential signal VSSQ, the better the anti-leakage effect of the pull-up node Q(N), and the more saturated the potential of the pull-up node Q(N) can be.

[0059] Figure 4 For Figure 2 the waveform schematic diagram driven by CK(N) in Figure 2 Since the Nth-stage clock signal CK(N) in

[0060] is not chamfered, the charging speed of the pull-up control module 30 for the pull-up node Q(N) remains constant, the potential of the pull-up node Q(N) is continuously lifted at a relatively fast speed, and the potential change trend of the node K / P hardly changes. In this case, it will cause the overlap voltage OVLV to be relatively high, for example, 10V. This indicates that the potential of the pull-up node Q(N) is relatively high when the feedback module is turned off. And the higher the potential of the pull-up node Q(N), the greater the voltage difference between the pull-up node Q(N) and the first low-potential signal VSSQ, the worse the anti-leakage effect of the pull-up node Q(N), and it is difficult to charge the potential of the pull-up node Q(N) to saturation, which easily leads to leakage of the pull-up node Q(N).

[0061] It can be understood that for the gate drive circuit provided in this embodiment, by stepwise lifting the potential of the pull-up node Q(N) through the pull-up control module 30, the potential lifting speed of the pull-up node Q(N) is reduced, and the feedback module can be controlled to turn off by the inverter module when the potential of the pull-up node Q(N) is relatively low, improving the phenomenon of leakage of the pull-up node Q(N) through the feedback module.

[0062] Moreover, since the leakage of the feedback module is reduced or avoided, the abnormal working phenomenon of the feedback module is improved, which is beneficial to increasing the service life of the feedback module and the charging saturation of the pull-up node Q(N), thereby improving the working reliability of the gate driving circuit.

[0063] Moreover, since the pull-up module raises the potential of the pull-up node Q(N) step by step, although it will affect the potential charging speed of the pull-up node Q(N), during the process of the gate driving circuit outputting a scan signal to control the charging of the data signal, the effective charging time is usually located in the latter part of the pulse duration of the scan signal. Therefore, no matter what the waveform of the former part of the pulse duration of the scan signal is, it will not affect the effective charging time.

[0064] Figure 5 is a waveform schematic diagram of CK(N) provided by an embodiment of the present application. Compared with Figure 2 shown, in this embodiment, the Nth-level clock line is used to transmit the Nth-level clock signal CK(N) with a front chamfer. According to Figure 1 the structure of the gate driving circuit shown, the Nth-level scan signal G(N) transmitted by the Nth-level scan line also has a front chamfer, and the Nth-level cascade signal ST(N) transmitted by the Nth-level cascade line also has a front chamfer. Since the waveform of the Nth-level scan signal G(N) is the same as that of the Jth-level scan signal and the phase of the Nth-level scan signal G(N) lags behind the phase of the Jth-level scan signal, and the waveform of the Nth-level cascade signal ST(N) is the same as that of the Jth-level cascade signal and the phase of the Nth-level cascade signal ST(N) lags behind the phase of the Jth-level cascade signal, therefore, the Jth-level scan signal transmitted by the Jth-level scan line also has a front chamfer, and the Jth-level cascade signal transmitted by the Jth-level cascade line also has a front chamfer.

[0065] It should be noted that the pull-up control transistor T11 can transmit the Jth-level scan signal with a front chamfer to the pull-up node Q(N) under the control of the Jth-level cascade signal with a front chamfer to realize the potential raising speed of the pull-up node Q(N) from slow to fast.

[0066] In one embodiment, since the Jth-level cascade signal and the Jth-level scan signal are the same, they can also be exchanged.

[0067] Among them, J is less than N. For example, J can be any one of N - 1 to N - 9, and further can be Figure 1 N - 6 shown. Correspondingly, the Jth-level scan signal is the (N - 6)th-level scan signal G(N - 6), and the Jth-level cascade signal is the (N - 6)th-level cascade signal ST(N - 6).

[0068] It should be noted that the structure of the pull-up control module 30 is not limited to the implementation manner including only the pull-up control transistor T11, and it can also be other structures that can realize the step-by-step elevation of the potential of the pull-up node Q(N).

[0069] In one embodiment, as Figure 5 shown, the starting time of the front chamfer is the same as the starting time of the rising edge of the Nth-stage clock signal CK(N) in terms of timing, and the duration t of the front chamfer is greater than or equal to 1 / 4 and less than or equal to 1 / 3 compared to the pulse duration T of the Nth-stage clock signal CK(N).

[0070] It should be noted that setting the ratio range of the two in this embodiment neither affects the effective charging time of the display panel nor can improve the leakage situation of the pull-up node Q(N).

[0071] In one embodiment, as Figure 5 shown, the potential y of the front chamfer is greater than or equal to 1 / 3 and less than or equal to 2 / 3 compared to the pulse amplitude Y of the Nth-stage clock signal CK(N).

[0072] It should be noted that setting the ratio range of the two in this embodiment neither affects the effective charging time of the display panel nor can further improve the leakage situation of the pull-up node Q(N).

[0073] In one embodiment, as Figure 5 shown, the potential y of the front chamfer is 1 / 2 compared to the pulse amplitude Y of the Nth-stage clock signal CK(N).

[0074] It should be noted that setting the specific value of the ratio of the two in this embodiment neither affects the effective charging time of the display panel nor can optimally improve the leakage situation of the pull-up node Q(N).

[0075] That is to say, the output terminal of the pull-up control module 30, namely the pull-up node Q(N), is used to provide a pull-up control signal, and the pull-up control signal includes at least one stepped pulse, and each stepped pulse includes a first potential pulse and a second potential pulse that are connected in sequence before and after, and the potential of the first potential pulse is lower than the potential of the second potential pulse.

[0076] It should be noted that the potential of the first potential pulse can be Figure 5 the potential y of the front chamfer shown in. The potential of the second potential pulse can be Figure 5 the pulse amplitude Y shown in.

[0077] In one embodiment, each stepped pulse further includes a third potential pulse (not shown) that follows the second potential pulse, and the potential of the second potential pulse is lower than the potential of the third potential pulse.

[0078] It can be understood that each step pulse for constructing the pull-up control signal in this embodiment has three successively increasing potentials, which can further control the rising speed of the potential of the pull-up node Q(N). For example, when charging the pull-up node Q(N) with the first potential, the rising speed of the potential of the pull-up node Q(N) is the slowest; when charging the pull-up node Q(N) with the second potential, the rising speed of the potential of the pull-up node Q(N) is faster; when charging the pull-up node Q(N) with the third potential, the rising speed of the potential of the pull-up node Q(N) is the fastest.

[0079] In one of the embodiments, each step pulse may further include more successively increasing potentials following the third potential.

[0080] Figure 6 For Figure 5 the waveform schematic diagram driven by CK(N) in Figure 5 since the Nth-level clock signal CK(N) transmitted by the Nth-level clock line in

[0081] has a front chamfer, the pull-up control module 30 can raise the potential of the pull-up node Q(N) from slow to fast, while the potential change trend of the node K / P hardly changes. In this case, the overlapping voltage OVLV will be lower, such as -6.8V, which indicates that the potential of the pull-up node Q(N) is lower when the feedback module is turned off. And the lower potential of the pull-up node Q(N) will further reduce the voltage difference between the pull-up node Q(N) and the first low-potential signal VSSQ, and the anti-leakage effect of the pull-up node Q(N) will also become better, and the potential of the pull-up node Q(N) can also be charged to saturation, improving the leakage situation of the pull-up node Q(N).

[0082] It can be understood that for the display panel provided in this embodiment, by the pull-up control module 30 stepping up the potential of the pull-up node Q(N), the rising speed of the potential of the pull-up node Q(N) is reduced, and the feedback module can be controlled to turn off through the inverting module when the potential of the pull-up node Q(N) is relatively low, improving the phenomenon of leakage of the pull-up node Q(N) through the feedback module.

[0083] Moreover, since the leakage situation of the feedback module is reduced or avoided, the abnormal working phenomenon of the feedback module is improved, which is beneficial to improving the service life of the feedback module and the charging saturation of the pull-up node Q(N), and further improving the working reliability of the gate driving circuit.

[0084] Moreover, since the pull-up module raises the potential of the pull-up node Q(N) step by step, although it will affect the charging speed of the potential of the pull-up node Q(N), during the process of the gate driving circuit outputting a scanning signal to control the charging of the data signal, the effective charging time is usually located in the latter part of the pulse duration of the scanning signal. Therefore, no matter what the waveform of the former part of the pulse duration of the scanning signal is, it will not affect the effective charging time.

[0085] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0086] The gate driving circuit and the display panel provided by the embodiments of the present application have been introduced in detail above. Specific examples are used herein to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the technical solution and its core idea of the present application; those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A gate driving circuit, characterized in that, The gate driving circuit includes a plurality of cascaded gate driving units, and each of the gate driving units includes: a pull-up control module, an output end of the pull-up control module is connected to a pull-up node, and is configured to stepwise raise the potential of the pull-up node; an inverting module, an input end of the inverting module is connected to the pull-up node, and is configured to output an anti-leakage control signal in response to the raising of the potential of the pull-up node; and a feedback module, a control end of the feedback module is connected to an output end of the inverting module, one end of the feedback module is connected to the pull-up node, and the other end of the feedback module is connected to a first low-potential line, and is configured to reduce the leakage between the pull-up node and the first low-potential line in response to the anti-leakage control signal; a pull-up transistor, one of a source / drain of the pull-up transistor is connected to an Nth-stage clock line, a gate of the pull-up transistor is connected to the pull-up node, and the other of the source / drain of the pull-up transistor is connected to an Nth-stage scan line; wherein, the Nth-stage clock line is configured to transmit an Nth-stage clock signal with a front chamfer, the Nth-stage scan line is configured to transmit an Nth-stage scan signal with a front chamfer, a starting moment of the front chamfer is the same as a starting moment of a rising edge of the Nth-stage clock signal in time sequence, a duration of the front chamfer is greater than or equal to 1 / 4 and less than or equal to 1 / 3 of a pulse duration of the Nth-stage clock signal, and a potential of the front chamfer is greater than or equal to 1 / 3 and less than or equal to 2 / 3 of a pulse amplitude of the Nth-stage clock signal; wherein, the pull-up control module includes a pull-up control transistor, one of a source / drain of the pull-up control transistor is connected to a Jth-stage scan line, a gate of the pull-up control transistor is connected to a Jth-stage cascade line, and the other of the source / drain of the pull-up control transistor is connected to the pull-up node; wherein, the Jth-stage scan line is configured to transmit a Jth-stage scan signal with a front chamfer, and the Jth-stage cascade line is configured to transmit a Jth-stage cascade signal with a front chamfer; wherein, the gate driving unit further includes a cascade transistor, one of a source / drain of the cascade transistor is connected to the Nth-stage clock line, a gate of the cascade transistor is connected to the pull-up node, and the other of the source / drain of the cascade transistor is connected to an Nth-stage cascade line; wherein, a waveform of the Nth-stage scan signal is the same as a waveform of the Jth-stage scan signal and a phase of the Nth-stage scan signal lags behind a phase of the Jth-stage scan signal; a waveform of an Nth-stage cascade signal transmitted by the Nth-stage cascade line is the same as a waveform of the Jth-stage cascade signal and a phase of the Nth-stage cascade signal lags behind a phase of the Jth-stage cascade signal.

2. The gate driving circuit according to claim 1, wherein The pull-up node is configured to provide a pull-up control signal, the pull-up control signal includes at least one stepped pulse, and each of the stepped pulses includes a first potential pulse and a second potential pulse that are sequentially connected, and a potential of the first potential pulse is lower than a potential of the second potential pulse.

3. The gate driving circuit according to claim 2, wherein Each of the step pulses further includes a third potential pulse following the second potential pulse, and the potential of the second potential pulse is lower than that of the third potential pulse.

4. The gate driving circuit according to claim 1, characterized in that, The ratio of the potential of the front chamfer to the pulse amplitude of the Nth-stage clock signal is 1 / 2.

5. The gate driving circuit according to any one of claims 1-4, characterized in that, The inverting module includes a first inverting sub-module. The first inverting sub-module includes a first transistor, a second transistor, a third transistor, and a fourth transistor. One of the source / drain of the first transistor is connected to one of the source / drain of the first low-frequency control line, the second transistor, and the gate of the first transistor. The other of the source / drain of the first transistor is connected to the gate of the second transistor and one of the source / drain of the third transistor. The other of the source / drain of the second transistor is connected to one of the source / drain of the fourth transistor. The gate of the third transistor is connected to the pull-up node and the gate of the fourth transistor. The first low-potential line is connected to the other of the source / drain of the third transistor and the other of the source / drain of the fourth transistor. The feedback module includes a first feedback transistor. One of the source / drain of the first feedback transistor is connected to the pull-up node. The gate of the first feedback transistor is connected to the other of the source / drain of the second transistor and one of the source / drain of the fourth transistor. The other of the source / drain of the first feedback transistor is connected to the first low-potential line.

6. The gate driving circuit according to claim 5, wherein The inverting module further includes a second inverting sub-module. The second inverting sub-module includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. One of the source / drain of the fifth transistor is connected to one of the source / drain of the second low-frequency control line, the sixth transistor, and the gate of the fifth transistor. The other of the source / drain of the fifth transistor is connected to the gate of the sixth transistor and one of the source / drain of the seventh transistor. The other of the source / drain of the sixth transistor is connected to one of the source / drain of the eighth transistor. The gate of the seventh transistor is connected to the pull-up node and the gate of the eighth transistor. The first low-potential line is connected to the other of the source / drain of the seventh transistor and the other of the source / drain of the eighth transistor. The feedback module includes a second feedback transistor. One of the source / drain of the second feedback transistor is connected to the pull-up node. The gate of the second feedback transistor is connected to the other of the source / drain of the sixth transistor and one of the source / drain of the eighth transistor. The other of the source / drain of the second feedback transistor is connected to the first low-potential line.

7. A gate driving circuit, characterized in that The gate driving circuit includes a plurality of cascaded gate driving units. Each of the gate driving units includes: A pull-up control transistor, one of the source / drain of the pull-up control transistor is connected to the J-th scan line, the gate of the pull-up control transistor is connected to the J-th cascade line, and the other of the source / drain of the pull-up control transistor is connected to the pull-up node; A first transistor, one of the source / drain of the first transistor is connected to the first low-frequency control line and the gate of the first transistor; A second transistor, one of the source / drain of the second transistor is connected to one of the source / drain of the first transistor, and the gate of the second transistor is connected to the other of the source / drain of the first transistor; A third transistor, one of the source / drain of the third transistor is connected to the other of the source / drain of the first transistor, the gate of the third transistor is connected to the pull-up node, and the other of the source / drain of the third transistor is connected to the first low-potential line; A fourth transistor, one of the source / drain of the fourth transistor is connected to the other of the source / drain of the second transistor, the gate of the fourth transistor is connected to the pull-up node, and the other of the source / drain of the fourth transistor is connected to the first low-potential line; and A first feedback transistor, one of the source / drain of the first feedback transistor is connected to the pull-up node, the gate of the first feedback transistor is connected to the other of the source / drain of the second transistor and one of the source / drain of the fourth transistor, and the other of the source / drain of the first feedback transistor is connected to the first low-potential line; A pull-up transistor, one of the source / drain of the pull-up transistor is connected to the N-th clock line, the gate of the pull-up transistor is connected to the pull-up node, and the other of the source / drain of the pull-up transistor is connected to the N-th scan line; Wherein, the J-th scan line is used to transmit the J-th scan signal with a front chamfer, and the J-th cascade line is used to transmit the J-th cascade signal with a front chamfer; the N-th clock line is used to transmit the N-th clock signal with a front chamfer; the N-th scan line is used to transmit the N-th scan signal with a front chamfer, the starting moment of the front chamfer is the same as the starting moment of the rising edge of the N-th clock signal in time sequence, the ratio of the duration of the front chamfer to the pulse duration of the N-th clock signal is greater than or equal to 1 / 4 and less than or equal to 1 / 3, and the ratio of the potential of the front chamfer to the pulse amplitude of the N-th clock signal is greater than or equal to 1 / 3 and less than or equal to 2 / 3; Wherein, the gate driving unit further includes: A fifth transistor, one of the source / drain of the fifth transistor is connected to the second low-frequency control line and the gate of the fifth transistor; A sixth transistor, one of the source / drain of the sixth transistor is connected to one of the source / drain of the fifth transistor, and the gate of the sixth transistor is connected to the other of the source / drain of the fifth transistor; A seventh transistor, one of the source / drain electrodes of the seventh transistor is connected to the other of the source / drain electrodes of the fifth transistor, the gate of the seventh transistor is connected to the pull-up node, and the other of the source / drain electrodes of the seventh transistor is connected to the first low-potential line; An eighth transistor, one of the source / drain electrodes of the eighth transistor is connected to the other of the source / drain electrodes of the sixth transistor, the gate of the eighth transistor is connected to the pull-up node, and the other of the source / drain electrodes of the eighth transistor is connected to the first low-potential line; and A second feedback transistor, one of the source / drain electrodes of the second feedback transistor is connected to the pull-up node, the gate of the second feedback transistor is connected to the other of the source / drain electrodes of the sixth transistor and one of the source / drain electrodes of the seventh transistor, and the other of the source / drain electrodes of the second feedback transistor is connected to the first low-potential line; Wherein, the gate driving unit further includes a cascaded transistor, one of the source / drain electrodes of the cascaded transistor is connected to the Nth-stage clock line, the gate of the cascaded transistor is connected to the pull-up node, and the other of the source / drain electrodes of the cascaded transistor is connected to the Nth-stage cascaded line; Wherein, the waveform of the Nth-stage scan signal is the same as the waveform of the Jth-stage scan signal and the phase of the Nth-stage scan signal lags behind the phase of the Jth-stage scan signal; the waveform of the Nth-stage cascaded signal transmitted on the Nth-stage cascaded line is the same as the waveform of the Jth-stage cascaded signal and the phase of the Nth-stage cascaded signal lags behind the phase of the Jth-stage cascaded signal.

8. A display panel, characterized in that, Comprising the gate driving circuit according to any one of claims 1 to 7.

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