Command decoding circuit, memory, and electronic device
By designing a command decoding circuit for LPDDR5, a clock gate is used to generate a dynamic clock signal, the problem of high power consumption when decoding active commands in the prior art is solved, and more efficient energy efficiency performance is achieved.
Patent Information
- Application Number
- CN202110811855.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-07-19
- Publication Date
- 2025-06-27
- Estimated Expiration
- 2041-07-19
AI Technical Summary
In the prior art, when decoding the active commands ACT1 and ACT2 in LPDDR5, it is necessary to rely on the system clock signal, resulting in high power consumption.
A command decoding circuit is designed, including a first decoding unit, a second decoding unit and a clock gate. The dynamic clock signal is generated through the clock gate, and it is generated and switched only when the decoding command is decoded. After the decoding is completed, the dynamic clock signal is turned off to reduce unnecessary clock signal switching.
Effectively reduce the power consumption during decoding active commands, and improve the energy efficiency performance of the circuit by reducing unnecessary switching of clock signals.
Smart Images
Figure CN115641890B_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of integrated circuit technology, and in particular, to a command decoding circuit, a memory, and an electronic device. Background Art
[0002] In various electronic devices, memory is an indispensable component that affects the performance of the electronic device. A commonly used memory can be SDRAM (synchronous dynamic random-access memory). During the research on SDRAM, various types of SDRAM have emerged. For example, LPDDR (low power double data rate SDRAM). In the new protocol of LPDDR5 (the fifth generation of LPDDR), two active commands, ACT1 and ACT2, are defined. The system chip sends ACT1 and ACT2 in sequence, and ACT1 and ACT2 are executed after being decoded.
[0003] In the prior art, when decoding ACT1 and ACT2, it is necessary to rely on the system clock signal provided by the system chip. Since this system clock signal is always constantly switching between high level and low level, the power consumption during decoding of the active command is relatively high. Summary of the Invention
[0004] The embodiments of the present application provide a command decoding circuit, a memory, and an electronic device to reduce the power consumption during decoding of the active command.
[0005] In a first aspect, the embodiments of the present application provide a command decoding circuit, including:
[0006] A first decoding unit for decoding a first command signal according to a dynamic clock signal generated by a clock gate;
[0007] A second decoding unit for decoding a second command signal according to the dynamic clock signal generated by the clock gate, where the second command signal is triggered within a preset period after the first command signal;
[0008] The clock gate is configured to generate a dynamic clock signal after the chip select signal of the first decoding unit represents the start of decoding the first command signal, or after decoding the second command signal, and to turn off the dynamic clock signal when the chip select signal represents that the decoding of the first command signal has not started, or after decoding the second command signal.
[0009] Optionally, it further includes:
[0010] An enable signal generation unit, configured to generate an enable signal according to the first command signal and the second command signal;
[0011] The clock gate is further configured to generate a dynamic clock signal or turn off the dynamic clock signal according to the chip select signal, the enable signal, and the system clock signal.
[0012] Optionally, the enable signal generation unit is further configured to generate the enable signal with a high level when both the first command signal and the second command signal are at a high level; or generate the enable signal with a low level when the first command signal or the second command signal is at a low level;
[0013] The clock gate is further configured to turn off the dynamic clock signal when the chip select signal is at a low level or the enable signal is at a high level; or generate a dynamic clock signal according to the system clock signal when the chip select signal is at a high level and the enable signal is at a low level.
[0014] Optionally, the enable signal generation unit includes:
[0015] An AND gate, configured to determine the AND signal of the first command signal and the second command signal as the enable signal;
[0016] The clock gate includes:
[0017] A NOT gate, configured to take the inverted signal of the chip select signal;
[0018] An OR gate, configured to determine the OR signal of the inverted signal, the enable signal, and the system clock signal as the dynamic clock signal.
[0019] Optionally, the enable signal generation unit is further configured to generate the enable signal with a low level when both the first command signal and the second command signal are at a high level; or generate the enable signal with a high level when the first command signal or the second command signal is at a low level;
[0020] The clock gate is further configured to turn off the dynamic clock signal when the chip select signal or the enable signal is at a low level; or generate a dynamic clock signal according to the system clock signal when the chip select signal and the enable signal are at a high level.
[0021] Optionally, the enable signal generation unit includes:
[0022] An AND gate, configured to determine the AND signal of the first command signal and the second command signal;
[0023] A NOT gate, taking the inverted signal of the AND signal as the enable signal;
[0024] The clock gate is an AND gate for determining the AND signal of the system clock signal, the enable signal, and the chip select signal as the dynamic clock signal.
[0025] Optionally, it further includes:
[0026] A timer for generating a timing signal after the first decoding unit decodes the first command signal. The timing signal is used to indicate whether the duration between the current time and the decoding of the first command signal is greater than a preset period, and the timing signal changes over time;
[0027] The clock gate is further used to turn off the dynamic clock signal when the duration is greater than the preset period.
[0028] Optionally, the timer is further used to generate a timing signal according to the dynamic clock signal after the first decoding unit decodes the first command signal.
[0029] Optionally, it further includes:
[0030] An enable signal generation unit for generating the enable signal according to the first command signal, the second command signal, and the timing signal;
[0031] The clock gate is further used to generate a dynamic clock signal or turn off the dynamic clock signal according to the chip select signal, the enable signal, and the system clock signal.
[0032] Optionally, the enable signal generation unit is further used to generate the high-level enable signal when the first command signal is high level and the second command signal or the timing signal is high level; or generate the low-level enable signal when the first command signal, or the second command signal, or the timing signal is low level;
[0033] The clock gate is further used to turn off the dynamic clock signal when the chip select signal is low level or the enable signal is high level; or generate a dynamic clock signal according to the system clock signal when the chip select signal is high level and the enable signal is low level.
[0034] Optionally, the enable signal generation unit includes:
[0035] An OR gate for determining the OR signal of the second command signal and the timing signal;
[0036] A first AND gate for determining the AND signal between the first command signal and the AND signal output by the second AND gate, and the AND signal output by the first AND gate is the enable signal;
[0037] A second AND gate for determining an AND signal between the OR signal and the AND signal output by the first AND gate;
[0038] The clock gate includes:
[0039] A NOT gate for taking the inverted signal of the chip select signal;
[0040] An OR gate for determining an OR signal of the inverted signal, the enable signal, and the system clock signal as the dynamic clock signal.
[0041] Optionally, the enable signal generation unit is further configured to generate the low-level enable signal when the first command signal is high and the second command signal or the timing signal is high; or, generate the high-level enable signal when the first command signal, or the second command signal, or the timing signal is low;
[0042] The clock gate is further configured to turn off the dynamic clock signal when the chip select signal or the enable signal is low; or, generate a dynamic clock signal according to the system clock signal when the chip select signal and the enable signal are high.
[0043] Optionally, the enable signal generation unit includes:
[0044] An OR gate for determining an OR signal of the second command signal and the timing signal;
[0045] A first AND gate for determining an AND signal between the first command signal and the AND signal output by the second AND gate;
[0046] A second AND gate for determining an AND signal between the OR signal and the AND signal output by the first AND gate;
[0047] A NOT gate for using the inverted signal of the AND signal output by the first AND gate as the enable signal;
[0048] The clock gate is an AND gate for determining an AND signal of the system clock signal, the enable signal, and the chip select signal as the dynamic clock signal.
[0049] Optionally, when the timing signal is low, it represents that the duration between the current time and decoding the first command signal is less than or equal to a preset period; when the timing signal is high, it represents that the duration between the current time and decoding the first command signal is greater than the preset period.
[0050] Optionally, the preset period is 8 cycles of the system clock signal.
[0051] Optionally, the first command signal is used to trigger the decoding of the second command signal, and the second command signal is used to perform a row operation on the storage bank.
[0052] In a second aspect, an embodiment of the present application further provides a memory, including:
[0053] The command decoding circuit, system chip, and storage bank as described in the first aspect;
[0054] The system chip is used to generate the system clock signal and trigger the first command signal and the second command signal;
[0055] The second command signal is used to operate on the storage bank.
[0056] Optionally, the memory is a low-power double data rate synchronous dynamic random access memory LPDDR.
[0057] In a third aspect, an embodiment of the present application further provides an electronic device, including the memory described in the second aspect.
[0058] The command decoding circuit, memory, and electronic device provided by the embodiments of the present application. The circuit includes: a first decoding unit, a second decoding unit, and a clock gate. Among them, the first decoding unit is used to decode the first command signal according to the dynamic clock signal generated by the clock gate. The second decoding unit is used to decode the second command signal according to the dynamic clock signal generated by the clock gate, and the second command signal is triggered within a preset period after the first command signal. The clock gate is used to generate a dynamic clock signal after the chip select signal of the first decoding unit represents the start of decoding the first command signal, or after the second decoding unit decodes the second command signal, and turn off the dynamic clock signal after the chip select signal of the first decoding unit represents the non-start of decoding the first command signal, or after the second decoding unit decodes the second command signal. It can be seen that the clock gate also needs to generate a dynamic clock signal in combination with the system clock signal. It is possible to avoid the continuous switching of the clock signal between high and low levels before decoding the first active command and after decoding the second active command. In this way, the power consumption can be reduced. Description of the Drawings
[0059] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0060] Figure 1Exemplarily shown is a schematic diagram of the process of performing row operations on a memory bank in the prior art;
[0061] Figures 2 to 6 Exemplarily shown are five schematic diagrams of the command decoding circuit provided in the embodiments of the present application;
[0062] Figure 7 Exemplarily shown is a schematic diagram of a memory structure provided in the embodiments of the present application. Detailed implementation manners
[0063] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the embodiments of the present application.
[0064] The embodiments of the present application are applicable to the decoding process of active commands for reading and writing memory data. The active commands after decoding can be used to read and write data to the memory, that is, row operations. Among them, after the continuous evolution of SDRAM, LPDDR emerged.
[0065] In LPDDR5, the active commands are divided into first active commands and second active commands. The first active command is used to keep the following signals at a high level after the rising edge of the system clock signal arrives: CS (chip select) signal, the first CA (command address) signal CA0, the second CA signal CA1, and the third CA signal CA2. The second active command is used to keep the CS signal at a high level, CA0 at a high level, CA1 at a high level, and CA2 at a low level after the rising edge of the system clock signal arrives. The second active command is triggered within 8 clock cycles after the first active command is triggered. If the second active command is not triggered within 8 clock cycles, it is determined that a timeout has occurred. After that, the second active command is no longer waited for, but the next round of the first active command is waited for. Within these 8 clock cycles, only CA signals, write signals, read signals, masked write signals, MRR, precharge signals, memory bank update signals, etc. can be triggered.
[0066] Figure 1 Exemplarily shown is a schematic diagram of the process of performing row operations on a memory bank in the prior art. Refer to Figure 1As shown, the controller includes a decoding circuit, which can decode a command address signal according to a system clock signal to obtain a first active command ACT1 or a second active command ACT2. Among them, the system clock signal is provided by a system chip. The decoded second command signal can be used to perform row operations on a memory storage group, that is, data reading or data writing.
[0067] However, since the system clock signal is always constantly switching between high level and low level, the power consumption of the decoding circuit is relatively high.
[0068] To solve the above problem, it can be considered to avoid the continuous switching of the clock signal between high level and low level when decoding is not required.
[0069] As can be seen from the above definitions of the first active command and the second active command, the second active command is usually triggered within 8 clock cycles after the first active command is triggered. When the second active command is triggered, it represents the end of a command for data reading and writing, and it is necessary to wait for the next first active command. Therefore, before decoding the first active command and after decoding the second active command, the continuous switching of the clock signal between high level and low level can be avoided. In this way, the power consumption can be reduced.
[0070] Figure 2 An exemplary structural schematic diagram of a command decoding circuit 100 provided by an embodiment of the present application is shown. Refer to Figure 2 As shown, the command decoding circuit 100 includes a first decoding unit 101, a second decoding unit 102, and a clock gate 103.
[0071] Among them, the first decoding unit 101 is used to decode the first command signal according to the dynamic clock signal generated by the clock gate 103.
[0072] The second decoding unit 102 is used to decode the second command signal according to the dynamic clock signal generated by the clock gate 103, and the second command signal is triggered within a preset period after the first command signal.
[0073] The clock gate 103 is used to generate a dynamic clock signal after the chip select signal of the first decoding unit 101 represents the start of decoding the first command signal, or after the second decoding unit 102 decodes the second command signal, and to turn off the dynamic clock signal after the chip select signal of the first decoding unit 101 represents that the decoding of the first command signal has not started, or after the second decoding unit 102 decodes the second command signal. It can be seen that the clock gate 103 also needs to generate a dynamic clock signal in combination with the system clock signal.
[0074] Among them, the first decoding unit 101 and the second decoding unit 102 are circuits that decode the first command signal and the second command signal from the CA signal. Specifically, the first command signal and the second command signal are determined according to the CA signals sent on each command address line.
[0075] The first command signal is the signal corresponding to the aforementioned first active command, and the second command signal is the signal of the aforementioned second active command. The first command signal is used to trigger the second command signal, and the second command signal is used to perform row operations on the storage group, and the operations include but are not limited to: reading data in the storage group and writing data into the storage group.
[0076] It can be seen that when the first decoding unit 101 decodes the first command signal, it is based on the dynamic clock signal. Since the dynamic clock signal is generated according to the chip select signal of the first decoding unit 101, when the chip select signal represents that the first decoding unit 101 starts to decode, a dynamic clock signal that switches between high level and low level is generated, and the dynamic clock signal is turned off before that. In this way, the power consumption of the first decoding unit 101 can be saved.
[0077] When the second decoding unit 102 decodes the second command signal, it is based on the dynamic clock signal generated by the clock gate 103. After decoding the first command signal and before decoding the second command signal, the dynamic clock signal is the same as the system clock signal and also continuously switches between high level and low level. The dynamic clock signal is turned off after the second decoding unit 102 decodes the second command signal, that is, after that, the dynamic clock signal does not continuously switch between high level and low level, but always maintains a high level or a low level. In this way, the power consumption during decoding of the second decoding unit 102 is reduced.
[0078] In order to implement the above relationships among the first command signal, the second command signal, the chip select signal, and the dynamic clock signal, the above command decoding circuit further includes:
[0079] An enable signal generation unit 104, which is used to generate an enable signal according to the first command signal and the second command signal.
[0080] Based on the above enable signal generation unit 104, the above clock gate 103 is further used to generate a dynamic clock signal or turn off the dynamic signal according to the enable signal, the chip select signal, and the system clock signal.
[0081] Specifically, when the chip select signal is at a low level, that is, when the first decoding unit 101 does not start to decode, at this time, the dynamic clock signal can be turned off. The chip select signal is at a high level when the first decoding unit 101 starts to decode and at a low level before starting to decode.
[0082] When the chip select signal is high and the first command signal or the second command signal is low, that is, the first decoding unit 101 is decoding or the second decoding unit 102 is decoding. At this time, a dynamic clock signal can be generated so that the first decoding unit 101 or the second decoding unit 102 can decode according to the dynamic clock signal.
[0083] When the chip select signal, the first command signal, and the second command signal are all high, that is, the first command signal is decoded and the second command signal is decoded. At this time, the dynamic clock signal can be turned off. Since the chip select signal is high and the first command signal is also high when the second command signal is decoded, that is, the dynamic clock signal is turned off when the second command signal is high.
[0084] To implement the relationship between the first command signal, the second command signal, the chip select signal, and the dynamic clock signal, the enable signal can be high level or low level. This will be described in detail through two examples below.
[0085] In the first example, the above-mentioned enable signal generation unit 104 is specifically configured to generate a high-level enable signal when both the first command signal and the second command signal are high; or generate a low-level enable signal when the first command signal or the second command signal is low.
[0086] Correspondingly, the above-mentioned clock gate 103 is used to turn off the dynamic clock signal when the chip select signal is low or the enable signal is high; or generate a dynamic clock signal according to the system clock signal when the chip select signal is high and the enable signal is low.
[0087] To implement the above relationship between the first command signal, the second command signal, and the enable signal, referring to Figure 3 As shown, the above-mentioned enable signal generation unit 104 can be an AND gate.
[0088] Among them, the above-mentioned AND gate is used to determine the AND signal of the first command signal and the second command signal. That is, when the first command signal and the second command signal are high, the enable signal is high; when the first command signal or the second command signal is low, the enable signal is low.
[0089] Corresponding to the Figure 3 shown enable signal generation unit 104, referring to Figure 3As shown, the above clock gate 103 may include a NOT gate and an OR gate. Among them, the NOT gate is used to invert the chip select signal. The OR gate is used to determine the OR signal of the inverted signal output by the NOT gate, the system clock signal, and the enable signal to obtain a dynamic clock signal. That is to say, when the system clock signal or the enable signal or the inverted signal is at a high level, the dynamic clock signal is at a high level; when the system clock signal, the enable signal, and the inverted signal are all at a low level, the dynamic clock signal is at a low level.
[0090] In this case, when the chip select signal is at a high level and the enable signal is at a low level, the inverted signal of the chip select signal is at a low level, and the OR signal of the inverted signal and the enable signal is at a low level. Since the system clock signal switches between a high level and a low level, its OR signal with the low level, that is, the output dynamic clock signal, also switches with the switching of the system clock signal. When the enable signal is at a high level or the chip select signal is at a low level, the inverted signal of the chip select signal is at a high level, and the OR signal of the inverted signal and the enable signal is at a high level. Since the OR signal of the system clock signal and the high level, that is, the output dynamic clock signal, is always at a high level, the dynamic clock signal is turned off.
[0091] In the second example, the above enable signal generation unit 104 is specifically configured to generate a low-level enable signal when both the first command signal and the second command signal are at a high level; or, generate a high-level enable signal when the first command signal or the second command signal is at a low level.
[0092] Correspondingly, the above clock gate 103 is specifically configured to turn off the dynamic clock signal when the chip select signal or the enable signal is at a low level; or, generate a dynamic clock signal according to the system clock signal when the enable signal and the chip select signal are at a high level.
[0093] To implement the above relationship between the first command signal, the second command signal, and the enable signal, the above enable signal generation unit 104 may include an AND gate and a NOT gate. Refer to Figure 4 As shown, the AND gate and the NOT gate are combined into a NAND gate.
[0094] Among them, the AND gate is used to determine the AND signal of the first command signal and the second command signal. That is, when both the first command signal and the second command signal are at a high level, the AND signal output by the AND gate is at a high level; when the first command signal or the second command signal is at a low level, the AND signal output by the AND gate is at a low level.
[0095] The NOT gate is used to use the inverted signal of the AND signal as the enable signal. That is to say, when the AND signal output by the AND gate is at a high level, the inverted signal output by the NOT gate is at a low level, and the enable signal is at a low level; when the AND signal output by the AND gate is at a low level, the inverted signal output by the NOT gate is at a high level, and the enable signal is at a high level.
[0096] AndFigure 4 corresponds to the enabling signal generation unit 104 shown. Refer to Figure 4 As shown, the above clock gate 103 includes: an AND gate for determining the AND signal of the system clock signal, the enabling signal, and the chip select signal as the dynamic clock signal. That is, when the system clock signal, the enabling signal, and the chip select signal are all at a high level, the dynamic clock signal output by the clock gate 103 is at a high level; when the system clock signal or the enabling signal or the chip select signal is at a low level, the dynamic clock signal output by the clock gate 103 is at a low level.
[0097] In this case, when the enabling signal and the chip select signal are at a high level, the AND signal of the enabling signal and the chip select signal is at a high level. Since the system clock signal switches between a high level and a low level, its AND signal with the high level, that is, the dynamic clock signal, also switches with the switching of the system clock signal. When the enabling signal or the chip select signal is at a low level, the AND signal of the enabling signal and the chip select signal is at a low level, and its AND signal with the system clock signal, that is, the dynamic clock signal, is always at a low level, that is, the dynamic clock signal is turned off.
[0098] Optionally, the above command decoding circuit may further include: a timer 105 for generating a timing signal after the first decoding unit 101 decodes the first command signal. The timing signal is used to indicate whether the duration between the current time and the decoding of the first command signal is greater than a preset period, and the timing signal changes over time. Accordingly, the above clock gate 103 is further configured to turn off the dynamic clock signal when the duration between the current time and the decoding of the first command signal is greater than the preset period, or generate a dynamic clock signal when the duration between the current time and the decoding of the first command signal is less than or equal to the preset period.
[0099] Wherein, the preset period is 8 clock cycles of the system clock signal defined in the new protocol of LPDDR5.
[0100] The timing signal may be a signal with different levels before and after reaching the preset period after decoding the first command signal. Two typical timing signals are illustrated below.
[0101] First, before reaching the preset period after decoding the first command signal, that is, when the duration between the current time and the decoding of the first command signal is less than or equal to the preset period, the above timing signal may be at a high level; after reaching the preset period after decoding the first command signal, that is, when the duration between the current time and the decoding of the first command signal is greater than the preset period, the above timing signal is at a low level.
[0102] Second, before reaching the preset period after decoding the first command signal, that is, when the duration between the current time and decoding the first command signal is less than or equal to the preset period, the above timing signal can be at a low level; after reaching the preset period after decoding the first command signal, that is, when the duration between the current time and decoding the first command signal is greater than the preset period, the above timing signal is at a high level. Hereinafter, the second case is taken as an example to illustrate the relationship between the timing signal, the first command signal, the second command signal, and the dynamic clock signal.
[0103] In the embodiment of the present application, within 8 clock cycles after decoding the first command signal, if the second command signal is not triggered, it is determined as a timeout. At this time, waiting for the second command signal is no longer continued, and the dynamic clock signal is turned off so that the dynamic clock signal always remains at a high level or a low level. In this way, the power consumption can be further reduced.
[0104] Optionally, the above timer 105 is further configured to generate a timing signal according to the dynamic clock signal after the first decoding unit 101 decodes the first command signal.
[0105] It can be understood that after decoding the first command signal, the dynamic clock signal, like the system clock signal, continuously switches between a high level and a low level. At this time, the timer 105 needs to generate a timing signal according to the dynamic clock signal that continuously switches between a high level and a low level to wait for the second command signal or a timeout. After decoding the second command signal or a timeout, since the dynamic clock signal is turned off, the timer 105 no longer generates a timing signal, thus further reducing the power consumption.
[0106] In summary, before the first decoding unit 101 decodes, or after decoding the second command signal or the timing signal represents a timeout, the clock gate 103 turns off the dynamic clock signal, and the clock gate 103 generates the dynamic clock signal at other times.
[0107] To implement the above relationships among the first command signal, the second command signal, the chip select signal, the timing signal, and the dynamic clock signal, the above command decoding circuit further includes:
[0108] An enable signal generation unit 104, configured to generate an enable signal according to the first command signal, the second command signal, and the timing signal.
[0109] Based on the above enable signal generation unit 104, the above clock gate 103 is further configured to generate a dynamic clock signal or turn off the dynamic signal according to the chip select signal, the enable signal, and the system clock signal.
[0110] Specifically, when the chip select signal is at a low level, that is, when the first decoding unit 101 has not started decoding, at this time, the dynamic clock signal can be turned off.
[0111] When the chip select signal is at a high level and the first command signal or the second command signal or the timing signal is at a low level, that is, the first decoding unit 101 is performing decoding, or the second decoding unit 102 is performing decoding. At this time, a dynamic clock signal can be generated so that the first decoding unit 101 or the second decoding unit 102 can perform decoding according to the dynamic clock signal.
[0112] When the chip select signal and the first command signal are both at a high level and the second command signal or the timing signal is at a high level, that is, the first command signal is decoded and the second command signal is decoded, or the second command signal is not triggered within 8 clock cycles after the first command signal is decoded, the dynamic clock signal is turned off.
[0113] To implement the relationship between the first command signal, the second command signal, the chip select signal, the timing signal and the dynamic clock signal, the enable signal can be at a high level or a low level. Two examples are given below for detailed description.
[0114] In the first example, the above-mentioned enable signal generation unit 104 is specifically configured to generate a high-level enable signal when the first command signal is at a high level and the second command signal or the timing signal is at a high level; or, when the first command signal, or the second command signal, or the timing signal is at a low level, generate a low-level enable signal.
[0115] Correspondingly, the above-mentioned clock gate 103 is used to turn off the dynamic clock signal when the chip select signal is at a low level or the enable signal is at a high level; or, when the chip select signal is at a high level and the enable signal is at a low level, generate a dynamic clock signal according to the system clock signal.
[0116] To implement the above relationship between the first command signal, the second command signal and the timing signal and the enable signal, refer to Figure 5 As shown, the above-mentioned enable signal generation unit 104 may include an OR gate, a first AND gate and a second AND gate.
[0117] Among them, the above-mentioned OR gate is used to determine the OR signal of the second command signal and the timing signal. That is, when at least one of the second command signal and the timing signal is at a high level, the OR signal is at a high level; when both the second command signal and the timing signal are at a low level, the OR signal is at a low level.
[0118] The first AND gate is used to determine the AND signal between the first command signal and the AND signal output by the second AND gate, and the AND signal output by the first AND gate is the enable signal. That is, when both the first command signal and the AND signal output by the second AND gate are at a high level, the AND signal output by the first AND gate is at a high level and the enable signal is at a high level; when the first command signal or the AND signal output by the second AND gate is at a low level, the AND signal output by the first AND gate is at a low level and the enable signal is at a low level.
[0119] The second AND gate is used to determine the AND signal between the OR signal and the AND signal output by the first AND gate. That is, when both the OR signal output by the OR gate and the AND signal output by the first AND gate are at a high level, the AND signal output by the second AND gate is at a high level; when either the OR signal output by the OR gate or the AND signal output by the first AND gate is at a low level, the AND signal output by the second AND gate is at a low level.
[0120] AND Figure 5 Corresponding to the enable signal generation unit 104 shown in the figure, refer to Figure 5 As shown in the figure, the above clock gate 103 may include a NOT gate and an OR gate. Among them, the NOT gate is used to take the inverse signal of the chip select signal. The OR gate is used to determine the OR signal of the inverse signal output by the NOT gate, the system clock signal, and the enable signal to obtain a dynamic clock signal. That is, when the system clock signal or the enable signal or the inverse signal is at a high level, the dynamic clock signal is at a high level; when the system clock signal, the enable signal, and the inverse signal are all at a low level, the dynamic clock signal is at a low level.
[0121] In this case, when the chip select signal is at a high level and the enable signal is at a low level, the inverse signal of the chip select signal is at a low level, and the OR signal of the inverse signal and the enable signal is at a low level. Since the system clock signal switches between a high level and a low level, its OR signal with the low level, that is, the output dynamic clock signal, also switches with the switching of the system clock signal. When the enable signal is at a high level or the chip select signal is at a low level, the inverse signal of the chip select signal is at a high level, and the OR signal of the inverse signal and the enable signal is at a high level. Since the OR signal of the system clock signal and the high level, that is, the output dynamic clock signal, is always at a high level, the dynamic clock signal is turned off.
[0122] In the second example, the above enable signal generation unit 104 is specifically configured to generate a low-level enable signal when the first command signal is at a high level and the second command signal or the timing signal is at a high level; or, generate a high-level enable signal when the first command signal, or the second command signal, or the timing signal is at a low level.
[0123] Correspondingly, the above clock gate 103 is specifically configured to turn off the dynamic clock signal when the chip select signal or the enable signal is at a low level; or, generate a dynamic clock signal according to the system clock signal when the chip select signal and the enable signal are at a high level.
[0124] To implement the above relationship between the first command signal, the second command signal, the timing signal, and the enable signal, refer to Figure 6 As shown in the figure, the above enable signal generation unit 104 may include an OR gate, a first AND gate, a second AND gate, and a NOT gate.
[0125] Wherein, the above OR gate is used to determine the OR signal of the second command signal and the timing signal. That is, when at least one of the second command signal and the timing signal is at a high level, the OR signal is at a high level; when both the second command signal and the timing signal are at a low level, the OR signal is at a low level.
[0126] The first AND gate is used to determine the AND signal between the first command signal and the AND signal output by the second AND gate. That is, when both the first command signal and the AND signal output by the second AND gate are at a high level, the AND signal output by the first AND gate is at a high level; when either the first command signal or the AND signal output by the second AND gate is at a low level, the AND signal output by the first AND gate is at a low level.
[0127] The second AND gate is used to determine the AND signal between the OR signal and the AND signal output by the first AND gate. That is, when both the OR signal output by the OR gate and the AND signal output by the first AND gate are at a high level, the AND signal output by the second AND gate is at a high level; when either the OR signal output by the OR gate or the AND signal output by the first AND gate is at a low level, the AND signal output by the second AND gate is at a low level.
[0128] The NOT gate is used to use the NOT signal of the AND signal output by the first AND gate as the enable signal.
[0129] AND Figure 6 corresponding to the enable signal generation unit 104 shown, referring to Figure 6 as shown, the above clock gate 103 includes: an AND gate, which is used to determine the AND signal of the system clock signal, the enable signal, and the chip select signal as the dynamic clock signal. That is, when the system clock signal, the enable signal, and the chip select signal are all at a high level, the dynamic clock signal output by the clock gate 103 is at a high level; when the system clock signal or the enable signal or the chip select signal is at a low level, the dynamic clock signal output by the clock gate 103 is at a low level.
[0130] In this case, when the enable signal and the chip select signal are at a high level, the AND signal of the enable signal and the chip select signal is at a high level. Since the system clock signal switches between a high level and a low level, its AND signal with the high level, that is, the dynamic clock signal, also switches with the switching of the system clock signal. When the enable signal or the chip select signal is at a low level, the AND signal of the enable signal and the chip select signal is at a low level, and its AND signal with the system clock signal, that is, the dynamic clock signal, is always at a low level, that is, the dynamic clock signal is turned off.
[0131] Figure 7 An exemplary structural schematic diagram of a memory provided by an embodiment of the present application is shown, including: a command decoding circuit 302, a system chip 301, and a storage group 303.
[0132] Among them, the system-on-chip 301 is used to generate a system clock signal, and trigger a first command signal and a second command signal, and the second command signal is used to operate on the storage group 303.
[0133] The command decoding circuit 302 is used to decode the first command signal and the second command signal.
[0134] Optionally, the above-mentioned memory is LPDDR (low power double data rate SDRAM, low-power double-data-rate synchronous dynamic random access memory).
[0135] The embodiment of the present application also provides an electronic device, including the aforementioned memory.
[0136] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present application, and are not intended to limit them; although the embodiments of the present application have been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A command decoding circuit, characterized in that, Including: A first decoding unit for decoding a first command signal according to a dynamic clock signal generated by a clock gate; A second decoding unit for decoding a second command signal according to the dynamic clock signal generated by the clock gate, where the second command signal is triggered within a preset period after the first command signal; The clock gate is used to generate the dynamic clock signal after the chip select signal of the first decoding unit represents the start of decoding the first command signal or after decoding the second command signal, and to turn off the dynamic clock signal when the chip select signal represents that the first command signal has not started to be decoded or after decoding the second command signal.
2. The command decoding circuit according to claim 1, wherein Further including: An enable signal generation unit for generating an enable signal according to the first command signal and the second command signal; The clock gate is further used to generate the dynamic clock signal or turn off the dynamic clock signal according to the chip select signal, the enable signal, and the system clock signal.
3. The command decoding circuit according to claim 2, characterized in that The enable signal generation unit is further used to generate a high-level enable signal when both the first command signal and the second command signal are high level; or to generate a low-level enable signal when the first command signal or the second command signal is low level; The clock gate is further used to turn off the dynamic clock signal when the chip select signal is low level or the enable signal is high level; or to generate the dynamic clock signal according to the system clock signal when the chip select signal is high level and the enable signal is low level.
4. The command decoding circuit according to claim 3, characterized in that, The enable signal generation unit includes: An AND gate for determining the AND signal of the first command signal and the second command signal as the enable signal; The clock gate includes: A NOT gate for taking the inverted signal of the chip select signal; An OR gate for determining the OR signal of the inverted signal, the enable signal, and the system clock signal as the dynamic clock signal.
5. The command decoding circuit according to claim 2, characterized in that The enable signal generation unit is further used to generate a low-level enable signal when both the first command signal and the second command signal are high level; or to generate a high-level enable signal when the first command signal or the second command signal is low level; The clock gate is further used to turn off the dynamic clock signal when the chip select signal or the enable signal is low level; or to generate the dynamic clock signal according to the system clock signal when the chip select signal and the enable signal are high level.
6. The command decoding circuit according to claim 5, characterized in that, The enable signal generation unit includes: An AND gate for determining the AND signal of the first command signal and the second command signal; A NOT gate for taking the inverted signal of the AND signal as the enable signal; The clock gate is an AND gate for determining the AND signal of the system clock signal, the enable signal, and the chip select signal as the dynamic clock signal.
7. The command decoding circuit according to claim 1, wherein Further including: A timer, configured to generate a timing signal after the first decoding unit decodes the first command signal, where the timing signal is used to indicate whether the duration between the current time and the decoding of the first command signal is greater than the preset period, and the timing signal changes over time; The clock gate is further configured to turn off the dynamic clock signal when the duration is greater than the preset period.
8. The command decoding circuit according to claim 7, wherein: The timer is further configured to generate the timing signal according to the dynamic clock signal after the first decoding unit decodes the first command signal.
9. The command decoding circuit according to claim 8, wherein It further includes: An enable signal generation unit, configured to generate the enable signal according to the first command signal, the second command signal, and the timing signal; The clock gate is further configured to generate the dynamic clock signal or turn off the dynamic clock signal according to the chip select signal, the enable signal, and the system clock signal.
10. The command decoding circuit according to claim 9, wherein: The enable signal generation unit is further configured to generate the high-level enable signal when the first command signal is high level and the second command signal or the timing signal is high level; or generate the low-level enable signal when the first command signal, or the second command signal, or the timing signal is low level; The clock gate is further configured to turn off the dynamic clock signal when the chip select signal is low level or the enable signal is high level; or generate the dynamic clock signal according to the system clock signal when the chip select signal is high level and the enable signal is low level.
11. The command decoding circuit according to claim 10, characterized in that, The enable signal generation unit includes: An OR gate, configured to determine the OR signal of the second command signal and the timing signal; A first AND gate, configured to determine the AND signal between the first command signal and the AND signal output by the second AND gate, and the AND signal output by the first AND gate is the enable signal; A second AND gate, configured to determine the AND signal between the OR signal and the AND signal output by the first AND gate; The clock gate includes: A NOT gate, configured to take the inverted signal of the chip select signal; An OR gate, configured to determine the OR signal of the inverted signal, the enable signal, and the system clock signal as the dynamic clock signal.
12. The command decoding circuit according to claim 9, wherein: The enable signal generation unit is further configured to generate the low-level enable signal when the first command signal is high level and the second command signal or the timing signal is high level; or generate the high-level enable signal when the first command signal, or the second command signal, or the timing signal is low level; The clock gate is further configured to turn off the dynamic clock signal when the chip select signal or the enable signal is low level; or generate the dynamic clock signal according to the system clock signal when the chip select signal and the enable signal are high level.
13. The command decoding circuit according to claim 12, characterized in that, The enable signal generation unit includes: An OR gate, configured to determine the OR signal of the second command signal and the timing signal; A first AND gate for determining an AND signal between the first command signal and the AND signal output by the second AND gate; A second AND gate for determining an AND signal between the OR signal and the AND signal output by the first AND gate; An inverter for using the inverted signal of the AND signal output by the first AND gate as the enable signal; The clock gate is an AND gate for determining the AND signal of the system clock signal, the enable signal, and the chip select signal as the dynamic clock signal.
14. The command decoding circuit according to claim 7, wherein When the timing signal is at a low level, it represents that the duration between the current time and decoding the first command signal is less than or equal to the preset period; when the timing signal is at a high level, it represents that the duration between the current time and decoding the first command signal is greater than the preset period.
15. The command decoding circuit according to any one of claims 1 to 14, characterized in that The preset period is 8 periods of the system clock signal.
16. The command decoding circuit according to any one of claims 1 to 14, characterized in that The first command signal is used to trigger the second command signal, and the second command signal is used to perform a row operation on the memory bank.
17. A memory, characterized in that, Comprising: The command decoding circuit, system chip, and memory bank according to any one of claims 1 to 16; The system chip for generating a system clock signal and triggering the first command signal and the second command signal; The second command signal decoded by the second decoding unit is used to perform a row operation on the memory bank.
18. The memory according to claim 17, wherein The memory is a low-power double-data-rate synchronous dynamic random access memory LPDDR.
19. An electronic device, characterized in that, Comprising the memory according to claim 17 or 18.
Citation Information
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Semiconductor memory device
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