Semiconductor device with deep-depletion channel and method of manufacturing the same

Abstract

A semiconductor device includes a substrate, a gate structure, a source region, a drain region, a doped region, and a channel region. The gate structure is disposed in the substrate, and the source region and the drain region of a first conductivity type are disposed on opposite sides of the gate structure. A doped region of a second conductivity type different from the first conductivity type is disposed below and separated from the gate structure, the source region, and the drain region. The channel region is disposed between and in contact with the doped region and the gate structure, and the channel region has a doping concentration less than a doping concentration of the doped region.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to a semiconductor device, and more particularly to a semiconductor device with a deep depletion channel. BACKGROUND

[0002] Generally, a semiconductor device with a deep depletion channel is a device fabricated on a bulk silicon substrate. In operation of such a device, a depletion region can be generated at a predetermined distance below the gate structure, which exhibits similar electrical characteristics as the buried oxide of a silicon-on-insulator (SOI) substrate. Since the bulk silicon substrate is less expensive than the SOI substrate, the semiconductor device with a deep depletion channel is increasingly popular in certain applications, such as IoT (Internet of Things) device applications that require low power consumption.

[0003] The semiconductor device with a deep depletion channel generally includes a planar gate structure and a high-doped region (also referred to as a shield region, an SCR region). The SCR region is disposed at a predetermined distance below the planar gate structure. However, current leakage often occurs between each source / drain region and the SCR region, which negatively affects the electrical performance of the semiconductor device. SUMMARY

[0004] In view of the foregoing, there is still a need to provide an improved semiconductor device with a deep depletion channel and a method of fabricating the same.

[0005] According to some embodiments of the present disclosure, a semiconductor device is provided, which includes a substrate, a gate structure, a source region, a drain region, a doped region, and a channel region. The gate structure is disposed in the substrate, and the source region and the drain region of a first conductivity type are respectively disposed on two sides of the gate structure. The doped region having a second conductivity type different from the first conductivity type is disposed below and separated from the gate structure, the source region, and the drain region. The channel region is disposed between and in contact with the doped region and the gate structure, and a doping concentration of the channel region is less than a doping concentration of the doped region.

[0006] According to some embodiments of the present disclosure, a method of fabricating a semiconductor device is provided, which includes the following steps. A substrate is provided, and a doped region is formed on the substrate. Then, a channel layer is formed on the doped region, and a trench is formed in the channel layer. Subsequently, a gate structure is formed in the trench, wherein the gate structure is disposed above and separated from the doped region. Next, a source region and a drain region are formed on two sides of the gate structure, wherein the source region and the drain region are disposed above and separated from the doped region. A doping concentration of the channel layer is less than a doping concentration of the doped region.

[0007] These and other objects of the present disclosure will no doubt become apparent to those of ordinary skill in the art after reading the following detailed description of the preferred embodiments in conjunction with the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0008] Various aspects of the present application can be better understood when read in conjunction with the following detailed description of various embodiments. It should be understood that the various features of the present application can be used in any combination. For the sake of brevity, some of the inventive features will not be described repeatedly.

[0009] Figure 1 is a schematic cross-sectional view showing a semiconductor device according to some embodiments of the present application.

[0010] Figure 2 is a schematic cross-sectional view showing a semiconductor device according to some embodiments of the present application. Figure 1 is a schematic enlarged cross-sectional view showing a concentration profile in region A in

[0011] Figure 3 is a schematic cross-sectional view showing a semiconductor device according to some alternative embodiments of the present application.

[0012] Figure 4 is a schematic cross-sectional view showing a semiconductor device according to some alternative embodiments of the present application.

[0013] Figure 5 is a schematic top view showing a semiconductor device according to some embodiments of the present application.

[0014] Figures 6 to 9 is a schematic cross-sectional view showing a process of a method of manufacturing a semiconductor device according to some embodiments of the present application.

[0015] Figure 10 is a schematic cross-sectional view showing a process of a method of manufacturing a semiconductor device according to some alternative embodiments of the present application. DETAILED DESCRIPTION

[0016] The present technology is described with reference to the drawings, in which like elements are referred to with like numerals throughout. The drawings are not drawn to scale unless specifically noted. They are included solely for clarity of discussion. Several aspects of the present technology are discussed below with reference to exemplary applications. It should be understood that numerous specific details, relationships, and methods are set forth to provide a full understanding of the present technology. One having ordinary skill in the relevant art, however, will readily recognize that the present technology can be practiced without one or more of the specific details or with other methods. In other instances, well-known structures or operations are not shown in order to avoid obscuring the technology. The present technology is not limited by the illustrated ordering of acts or events, as some acts can occur in different orders and / or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with the present technology.

[0017] Figure 1 This is a schematic cross-sectional view showing a semiconductor device 100-1 according to some embodiments of the present invention. (Refer to...) Figure 1 Semiconductor device 100-1 may be a transistor with a deep depletion channel, and semiconductor device 100-1 may include at least a substrate 102, a doped region 104, a channel region 110, a gate structure 116, a source region 122, and a drain region 124.

[0018] Substrate 102 can be a semiconductor substrate of the desired conductivity type (e.g., n-type or p-type). In this invention, substrate 102 can also be any type of substrate for forming semiconductor devices thereon, including single-crystal substrates, semiconductor-on-insulator (SOI) substrates, and epitaxial-on-semiconductor (EPI) substrates, etc. Furthermore, while various embodiments will be described primarily with respect to materials and processes compatible with silicon-based semiconductor materials (e.g., silicon and alloys of silicon with germanium and / or carbon), this technology is not limited in this respect. Rather, various embodiments can be implemented using any type of semiconductor material.

[0019] Doped region 104 can be disposed on substrate 102, and can be disposed below and separated from gate structure 116. Doped region 104 can have a concentration profile where the doping concentration gradually increases from the bottom of doped region 104 to a predetermined region adjacent to the top of doped region 104, and then gradually decreases from that predetermined region to the top of doped region 104. For doped region 104 with a concentration profile, the peak concentration of the concentration profile can be 5 × 10⁻⁶. 18 Up to 1×10 20 atoms / cm 3 (atoms / cm 3 For example, it equals 5 × 10 18 atoms / cm 3 Greater than 5×10 18 atoms / cm 3 And less than 1×10 20 atoms / cm 3 , or equal to 1×10 20 atoms / cm 3The peak concentration of doped region 104 can extend laterally in the horizontal region below source region 122, drain region 124, and gate structure 116. For n-type semiconductor devices, such as silicon-based NMOS, doped region 104 may include p-type dopants, such as boron (B) or indium (In). Conversely, for p-type semiconductor devices, such as silicon-based PMOS, doped region 104 may include n-type dopants, such as arsenic (As), antimony (Sb), or phosphorus (P). It is worth noting that when doped region 104 is formed by performing an implantation process on substrate 102, doped region 104 can be considered as a doped region disposed in the upper part of substrate 102. In contrast, when doped region 104 is formed by performing an epitaxial growth process on substrate 102, doped region 104 can be considered as a doped region disposed on the top surface of substrate 102.

[0020] The channel region 110 is disposed on the doped region 104, such that the source region 122 and the drain region 124 are separated from the doped region 104 through the channel region 110. Furthermore, a portion of the channel region 110 may be disposed between the doped region 104 and the gate structure 116. Therefore, the gate structure 116 is also separated from the doped region 104 through the channel region 110. The channel region 110 can be an undoped region or a lightly doped region, such as undoped silicon or lightly doped silicon, such that the average doping concentration of the channel region 110 is less than the average doping concentration of the doped region 104.

[0021] According to some embodiments of the present invention, the channel region 110 may be a single-layer structure or a double-layer structure. For a double-layer channel region 110, the channel region 110 may include a first channel layer 106 and a second channel layer 108 in contact with the underlying doped region 104. The first channel layer 106 may be an undoped or lightly doped layer extending laterally over the doped region 104. A trench 140 may be formed in the first channel layer 106 and extend to the upper portion of the doped region. Furthermore, the second channel layer 108 may be an undoped or lightly doped layer conformally to the surface of the trench 140. Because the second channel layer 108 is disposed in the trench 140, a portion of the second channel layer 108 may be considered embedded in or surrounded by the doped region 104. Depending on different requirements, the trench 140 may be designed to include a curved surface or a surface having a flat bottom and sloping sidewalls. In either case, the second channel layer 108 may conformally to the surface of the trench 140. According to some embodiments of the present invention, the thickness of the first channel layer 106 may be greater than the thickness of the second channel layer 108. For example, the thickness of the first channel layer 106 is about 100 to 150 nanometers, and the thickness of the second channel layer 108 is about 10 to 40 nanometers.

[0022] It should be noted that, although Figure 1The curved interface between the first channel layer 106 and the second channel layer 108 is shown, but when the first channel layer 106 and the second channel layer 108 are made of the same material (e.g., undoped silicon), the interface may be difficult to detect or observe.

[0023] The gate structure 116 may be a trench gate including a gate dielectric 112 and a gate electrode 114, and the gate structure 116 may be disposed in a gate trench 150 defined by the inner surface of the second channel layer 108. Due to the presence of the second channel layer 108, the gate structure 116 may be separated from the first channel layer 106 and the underlying doped region 104. Depending on different requirements, the gate electrode 116 may be a polysilicon gate or a metal gate, but is not limited thereto.

[0024] The source region 122 and the drain region 124 can be respectively disposed on both sides of the gate structure 116. Specifically, the conductivity type of each of the source region 122 and the drain region 124 is different from the conductivity type of the doped region 104. For example, when the source region 122 and the drain region 124 are n-type regions (or p-type regions), the doped region 104 is a p-type region (or n-type region).

[0025] Furthermore, to further reduce contact resistance, conductive regions made of silicide or other conductive materials can be formed on or above the gate electrode 114, source region 122, and drain region 124, respectively. For example, silicide regions 132 and 134 can be disposed on the source region 122 and drain region 124, respectively, and electrically connected to the source region 122 and drain region 124, respectively. Silicate region 136 can be disposed on the gate structure 116, for example, on the gate electrode 114 of the gate structure 116, and electrically connected to the gate electrode 114. The silicide region 136 on the gate structure 116 can be laterally (i.e., along the x-direction) separated from the silicide regions 132 and 134 disposed on the source region 122 and drain region 124, respectively. In this way, current will not be directly transmitted between two adjacent silicide regions, thereby preventing possible leakage current in the semiconductor device 100-1.

[0026] In addition, to prevent current from flowing between adjacent devices (e.g., leakage), an isolation structure 130 such as shallow trench isolation (STI) can be used to surround the active region of the semiconductor device 100-1.

[0027] During operation of the semiconductor device 100-1, the gate electrode 114 can be positively or negatively biased, allowing charge carriers (e.g., holes or electrons) to transport along the bottom surface of the gate dielectric 112 between the source region 122 and the drain region 124. A depletion region can be caused by the voltage bias from the gate electrode 114 and is generated near the interface between the doped region 104 and the channel region 110. Furthermore, since both the source region 122 and the drain region 124 are disposed above and separated from the doped region 104, they do not directly contact the underlying doped region 104. Therefore, current leakage between the source region 122 / drain region 124 and the underlying doped region 104 can be effectively reduced or avoided. Furthermore, since the charge carriers transported below the gate structure 116 mainly flow in the second channel layer 108, the electrical performance of the semiconductor device 100-1 can be well controlled by adjusting the thickness of the second channel layer 108 to a predetermined value.

[0028] Figure 2 This illustrates some embodiments according to the present invention. Figure 1 A schematic enlarged cross-sectional view of the concentration distribution curve in region A. (Refer to...) Figure 2 The doping concentration of the doped region 104 can gradually change from the bottom of the doped region 104 to a predetermined depth. Furthermore, the doping concentration of the doped region 104 at each depth level can remain substantially the same laterally. Figure 2As shown in Figures (a) and (b) on the right, the concentration distribution curve of the dopant in the doped region 104 may have at least one peak. This peak may have a maximum concentration at a predetermined depth (as shown in Figure (a)) or a maximum concentration distributed over a range along the depth direction (as shown in Figure (b)). According to some embodiments of the invention, in order to control the concentration distribution curve of the dopant in the doped region 104, the dopant can be implanted into the doped region 104 by performing one or more ion implantation processes with different implantation energies and doses. Preferably, the doping concentration of the doped region 104 may have a flat concentration profile, including the maximum concentration, within a range of + / -30% of the average value along the depth direction. More preferably, the doping concentration of the doped region 104 may have a flat concentration profile, including the maximum concentration, within a range of + / -20% of the average value along the depth direction. Even more preferably, the doping concentration of the doped region 104 may have a flat concentration profile, including the maximum concentration, within a range of + / -10% of the average value along the depth direction. Essentially, a flat concentration distribution curve can be obtained by alternating ion implantation several times under appropriate conditions with a selected precision for this range. It should be noted that the doping concentration of the doped region 104 can have its maximum at a depth below the lowest point of the second channel layer 108. In other words, the bottom surface of the second channel layer 108 below the gate structure 116 can be shallower than the depth of the maximum doping concentration.

[0029] Figure 3 This is a schematic cross-sectional view illustrating a semiconductor device according to some alternative embodiments of the present invention. (Refer to...) Figure 3 , Figure 3 The semiconductor device 100-2 shown is similar to Figure 1 The semiconductor device 100-1 shown differs primarily in that the channel region 110 is a single-layer structure rather than a double-layer structure. Therefore, the trench 150 formed in the channel region 110 may not be covered by a thin semiconductor layer (e.g., undoped silicon). Furthermore, the trench 150 can be considered as a gate trench 150 for accommodating the gate structure 116. According to... Figure 3 In the semiconductor device 100-2 shown, the doped region 104 is also separated from the gate structure 116, the source region 122, and the drain region 124. Since the source region 122 and the drain region 124 are both located above and separated from the doped region 104, they do not directly contact the underlying doped region 104. Therefore, current leakage between the source / drain region 122 and the underlying doped region 104 can be effectively reduced or avoided.

[0030] Figure 4 This is a schematic cross-sectional view illustrating a semiconductor device according to some alternative embodiments of the present invention. (Refer to...)Figure 4 , Figure 4 The semiconductor device 100-3 shown is similar to Figure 1 The semiconductor device 100-1 shown is primarily distinguished in that a portion of the gate electrode 114 with a width of, for example, 20 to 200 nm protrudes from the gate trench 150, such that the top surface of the gate electrode is higher than the top surfaces of the source region 122 and the drain region 134. Furthermore, spacers 118 with a width of, for example, 10 to 50 nm can be disposed on both sides of the gate structure 116. Therefore, the gate structure 116 can be laterally separated from the source region 122 and the drain region 124 by the spacers 118. The silicide region 136 disposed on the gate structure 116 can be laterally (i.e., along the x-direction) and vertically (i.e., along the z-direction) separated from the silicide regions 132 and 134 disposed on the source region 122 and the drain region 124, respectively. In this way, current will not be directly transmitted between two adjacent silicide regions, thereby further preventing current from flowing between the semiconductor device 100-3 and the source region 122. Figure 1 The semiconductor device 100-1 shown may have leakage current. Furthermore, due to the presence of spacers 118 respectively disposed on the two sidewalls of the gate electrode 114, and... Figure 1 Compared to the semiconductor device 100-1 without spacers shown in the figure, the silicide regions 132 and 134 can be disposed further away from the sidewall of the gate electrode 114.

[0031] Figure 5 This is a schematic top view illustrating a semiconductor device 100-4 according to some embodiments of the present invention. (Refer to...) Figure 5 , respectively in Figure 1 , Figure 3 and Figure 4 The cross-sectional view shown can be considered as along... Figure 5 The line A-A' in the diagram is used to cut the active region (not shown), which includes at least source region 122 and drain region 124. The active region 122 and drain region 124 may extend along a first direction, such as the x-direction, while the gate structure 116 may extend along a second direction, such as the y-direction. It is worth noting that the extension directions of source region 122 and drain region 124 are not limited to those perpendicular to the extension direction of gate structure 116.

[0032] To enable those skilled in the art to implement the present invention, a method for manufacturing the semiconductor device of the present invention is further described below.

[0033] Figures 6 to 9 This is a schematic cross-sectional view illustrating a process for manufacturing a semiconductor device according to some embodiments of the present invention. (Refer to...) Figure 6A substrate 102, such as a semiconductor substrate, is provided. A doped well (not shown) of a certain conductivity type can be formed in the substrate 102. According to some embodiments of the invention, the doped well can be formed by performing at least one ion implantation process. For example, for a p-type doped well, it can be formed at an energy of 100–300 keV with an ion implantation rate of 1 × 10⁻⁶ ohms. 12 ~1×10 14 cm -2 The substrate 102 is implanted with a p-type dopant, such as boron, but not limited to this. Alternatively, for an n-type doped well, it can be implanted at an energy of 200–400 keV with a dose of 1 × 10⁻⁶. 12 ~1×10 14 cm -2 The doped region 104 is formed on the substrate 102 by ion implantation or epitaxial growth. The conductivity type of the dopant in the doped region 104 is the same as that of the dopant in the doped well. According to some embodiments of the invention, the doped region 104 may be a p-type region including p-type dopant such as boron or indium. According to some alternative embodiments of the invention, the doped region 104 may be an n-type region including n-type dopant such as arsenic (As), antimony (Sb), or phosphorus (P). To control the concentration profile of the dopant, various dopants can be implanted at different energies and doses in one or more ion implantation processes. Furthermore, the doped region 104 may also include other dopant, such as carbon, germanium, or boron fluoride, which can be used to adjust the concentration profile of the p-type or n-type dopant. According to some embodiments of the present invention, for the case where the doped region 104 is p-type, the p-type doped region 104 can be formed by sequentially performing a number of ion implantation processes, for example at an energy of 10–50 keV and a frequency of 1 × 10⁻⁶ ions / kV. 13 ~1×10 15 cm -2 Germanium was injected into a p-type doped well at a dose of 2–10 keV at a rate of 1 × 10⁻⁶. 13 ~1×10 15 cm -2 Carbon is injected into the p-type doped well at a dose of 1×10⁻⁶ keV at an energy of 10–30 keV. 12 ~1×10 14 cm -2 Boron was injected into the p-type doped well at a dose of 1 × 10⁻⁶ keV at an energy of 200–400 keV. 12 ~1×10 14 cm -2 The dosage of boron fluoride is injected into the p-type doped well. According to some alternative embodiments of the invention, for the case where the doped region 104 is n-type, the n-type doped region 104 can also be formed by sequentially performing several ion implantation processes, for example at energies of 50–200 keV at a rate of 1 × 10⁻⁶ ions / times.12 ~1×10 14 cm -2 The dosage of antimony was injected into the n-type doped well, and the concentration was increased at 1×10⁻⁶ keV. 12 ~1×10 14 cm -2 The dosage of antimony is injected into the n-type doped well. After the process of forming the doped region 104, the dopant in the doped region 104 can be activated by performing heat treatment at a suitable temperature (e.g., in the range of 500 to 700 °C).

[0034] According to some embodiments of the present invention, the conditions and / or time of ion implantation for forming the doped region 104 can be adjusted to obtain the desired concentration distribution profile, for example... Figure 2 The concentration distribution curve is shown. To obtain... Figure 2 The concentration distribution curve shown in (b) demonstrates how a dopant with a certain conductivity can be implanted into the substrate 102 through multiple ion implantation processes instead of a single ion implantation process. For example, for the p-type doped region 104, a p-type dopant such as boron fluoride (BF2) can be implanted into the substrate 102 through four sequential ion implantation processes. For example, in the first implantation process, the dose is 1 × 10⁻⁶. 12 ~1×10 14 cm -2 The energy is 5–15 keV; the second injection process uses a dose of 1 × 10⁻⁶. 12 ~1×10 14 cm -2 The energy is 7–17 keV; the third injection process has a dose of 1 × 10⁻⁶. 12 ~1×10 14 cm -2 The energy is 10–20 keV; and the fourth injection process has a dose of 1 × 10⁻⁶. 12 ~1×10 14 cm -2 The energy ranges from 15 to 25 keV, but is not limited to this. Similarly, for the n-type doped region 104, an n-type dopant such as antimony (Sb) can be implanted into the substrate 102 by sequentially performing four ion implantation processes. For example, in the first implantation process, the dose is 1 × 10⁻⁶. 12 ~1×10 14 cm -2 The energy is 10–30 keV; the second injection process uses a dose of 1 × 10⁻⁶. 12 ~1×10 14 cm -2 The energy is 15–35 keV; the third injection process has a dose of 1 × 10⁻⁶. 12 ~1×10 14 cm-2 The energy is 20–40 keV; and the fourth injection process has a dose of 1 × 10⁻⁶. 12 ~1×10 14 cm -2 The energy ranges from 25 to 45 keV, but is not limited to this. To obtain an accurate range (i.e., small variation) of doping concentration along the depth direction as a flat concentration distribution curve, several alternating ion implantations can be performed to obtain the desired accurate concentration range, but is not limited to this. Furthermore, if it is sufficient to obtain an accurate range of doping concentration along the depth direction as a flat concentration distribution curve, fewer ion implantations can be used, but is not limited to this.

[0035] Still refer to Figure 6 A first channel layer 106 with a thickness of 300–500 nm can be formed on the doped region 104 using an epitaxial growth process. The first channel layer 106 can be an undoped layer or a lightly doped layer, and the doping concentration of the first channel layer 106 is at least 10 to 10⁻⁶ lower than the doping concentration of the doped region 104. 3 times.

[0036] Reference Figure 7 An isolation structure 130 can be formed in a predetermined area, and then a trench 140 with a width (along the x-direction) of 50–150 nm and a depth (along the z-direction) of 250–550 nm can be formed in the first trench layer 106, extending downwards to the upper part of the doped region 104. Therefore, a portion of the doped region 104 can be exposed from the bottom surface of the trench 140. It should be noted that, according to some alternative embodiments of the invention, the trench 140 may not reach the doped region 104, such that no portion of the doped region 104 is exposed from the bottom surface of the trench 140. Furthermore, even after the main process for forming the trench 140, and even if no portion of the doped region 104 is exposed from the bottom surface of the trench 140, additional post-processing, such as a wet etching process, can be performed on the bottom surface of the trench 140 until the doped region 104 is exposed from the bottom surface of the trench 140. In addition, during the formation of the isolation structure 130 and the trench 140, the top surface of the first trench layer 106 may be covered with a thin protective layer, such as SiO2, to protect the top surface of the first trench layer 106 from damage.

[0037] Reference Figure 8 A second channel layer 108 with a thickness of 10–40 nm can be formed on the surface of the trench 140 to define the gate trench 150. However, with the first channel layer 106 remaining on the bottom surface of the trench 140, according to some alternative embodiments of the invention, for example… Figure 3In the structure shown, the second channel layer 108 can be omitted and therefore not formed in the trench 140. The lower portion of the second channel layer 108 can be in direct contact with the doped region 104. Furthermore, the second channel layer 108 can be an undoped layer or a lightly doped layer, and the doping concentration of the second channel layer 108 is at least 10⁻⁶ lower than the doping concentration of the doped region 104. 3 Then, the gate dielectric layer 142 can be conformally formed on the exposed surfaces of the first channel layer 106 and the second channel layer 108. According to some embodiments of the invention, the gate dielectric layer 142 with a thickness of 1 to 3 nm can be formed by thermal oxidation at a processing temperature of 800 to 1000 °C. According to some alternative embodiments of the invention, the gate dielectric layer 142 made of silicon oxynitride, hafnium oxide, etc., can be formed by a deposition process. Subsequently, a gate electrode layer 144, which may be polysilicon or metal, is formed on the gate dielectric layer 142 and fills the gate trench 150. In order to completely fill the trench 150, the thickness of the gate electrode layer 144 can be in the range of 500 to 700 nm.

[0038] Reference Figure 9 The gate electrode layer 144 can be planarized to form the gate electrode 114 in the gate trench 150 and stop on the gate dielectric layer 142. Then, by implanting dopants into the first channel layer 106 and the second channel layer 108, the source region 122 and the drain region 124 can be formed on the side of the gate electrode 114. According to some embodiments of the present invention, if both the source region 122 and the drain region 124 are n-type, the source region 122 and the drain region 124 can also be formed by performing at least one ion implantation process, for example, with an energy implantation dose of 1 × 10⁻⁶ at an energy of 5–15 keV. 15 ~1×10 17 cm -2 Phosphorus. According to some alternative embodiments of the invention, when both source region 122 and drain region 124 are p-type, source region 122 and drain region 124 can be formed by sequentially performing a number of ion implantation processes, for example, with an implantation dose of 1 × 10⁻⁶ at an energy of 5–15 keV. 12 ~1×10 14 cm -2 Boron, injected with an energy dose of 1×10 at an energy level of 10–30 keV. 14 ~1×10 16 cm -2 Germanium, and with an energy injection dose of 1×10⁻⁶ at 3–10 keV. 14 ~1×10 16 cm -2Boron. After the process of forming the source region 122 and drain region 124, the dopants in the source region 122 and drain region 124 can be activated by heat treatment, such as spike annealing, at a suitable temperature, for example in the range of 1000 to 1100 °C. Then, a silicide process can be performed to form metal silicides in the source region 122, drain region 124, and gate electrode 114, respectively. Afterwards, other processes can be performed to obtain, for example... Figure 1 The structure shown.

[0039] Figure 10 This is a schematic cross-sectional view illustrating a process for manufacturing a semiconductor device according to some alternative embodiments of the present invention. (Refer to...) Figure 10 , Figure 10 The process shown is Figure 8 Subsequent alternative processes. According to some alternative embodiments of the invention, in... Figure 8 After the steps, in order to manufacture such Figure 4 The gate structure 116 shown can be patterned by photolithography to form the gate electrode layer 144. Figure 10 The gate electrode 114 is shown. After forming the gate electrode 114, the two relatively protruding spacers 118 (not shown) of the gate electrode 114 can be further formed to have a width of 50-150 nm (along the x-direction), as shown. Figure 4 As shown; after forming two relatively protruding spacers 118, the source region 122 and the drain region 124 (not shown) can be as follows: Figure 4 Further formation is shown; and after the formation of source region 122 and drain region 124, silicide regions 132, 134, 136 (not shown) can be formed as follows: Figure 4 The patterned gate electrode 114 and the two opposing spacers 118 both enable lateral (i.e., along the x-direction) and vertical (i.e., along the z-direction) separation between the silicide region 136 disposed on the gate structure 116 and the silicide regions 132, 134 disposed on the source region 122 and drain region 124, respectively, to further prevent silicide separation in the form of... Figure 4 The semiconductor device 100-3 shown Figure 10 (not shown in the image) instead of as shown in the image Figure 1 The possible leakage current in the semiconductor device 100-1 shown is due to the increased separation caused by the spacer 118. Furthermore, it should be noted that the thickness and width of the gate electrode 114 can be adjusted according to different requirements and should not be construed as limiting.

[0040] Subsequently, by implanting dopants into the first channel layer 106 and the second channel layer 108, a source region 122 and a drain region 124 can be formed on the side of the gate electrode 114. Therefore, the top surface of the gate electrode 114 can be higher than the top surfaces of the source region 122 and the drain region 124. A silicide process can then be performed to form metal silicides in the source region 122, the drain region 124, and the gate electrode 114, respectively. Further processes can then be performed to obtain, for example... Figure 4 The structure shown. It should be noted that, referring to... Figure 10 Although each sidewall of the protruding portion of the gate electrode 114 is substantially aligned with the outer edge of the second channel layer 108, the sidewalls of the protruding portion of the gate electrode 114 may also be laterally misaligned with the outer edge of the second channel layer 108. According to some embodiments of the invention, the sidewalls of the protruding portion of the gate electrode 114 may extend outward beyond the outer edge of the second channel layer 108, such that the gate electrode 114 may cover a portion of the first channel layer 106, preventing doped regions (i.e., S / D regions) from forming in the portion of the first channel layer 106 covered by the gate electrode 114. According to some alternative embodiments of the invention, the sidewalls of the protruding portion of the gate electrode 114 may be trimmed inward relative to the outer edge of the second channel layer 108, such that a portion of the doped region (i.e., S / D region) may be formed in the portion of the second channel layer 108 not covered by the gate electrode 114.

[0041] While various embodiments of the present technology have been described above, it should be understood that they are presented merely as examples and not as limitations. Many changes can be made to the disclosed embodiments based on the disclosure herein without departing from the spirit or scope of the present technology. Therefore, the breadth and scope of the present technology should not be limited by any of the above embodiments. Rather, the scope of the present technology should be defined by the following claims and their equivalents.

[0042] Although the technology has been shown and described with respect to one or more embodiments, equivalent changes and modifications will occur to those skilled in the art upon reading and understanding this specification and the accompanying drawings. Furthermore, while a particular feature in this technology may be disclosed only for one of several embodiments, such feature may be combined with one or more other features of other embodiments, which may be desirable and advantageous for any given or particular application.

[0043] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the technology. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, with regard to the terms “comprising,” “containing,” “having,” “with,” or variations thereof used in the detailed description and / or claims, these terms are intended to be included in a manner similar to the term “comprising.”

[0044] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which they pertain. Furthermore, the terms “approximately,” “substantially,” and “approximately,” as used herein with respect to said values ​​or properties, are intended to mean within 20% of said value or property, unless otherwise stated above. It should also be understood that terms, such as those defined in commonly used dictionaries, shall be interpreted as having meanings consistent with their meanings in the context of the relevant field; and, unless explicitly defined herein, they shall not be interpreted in an idealized or overly formal sense.

[0045] Those skilled in the art will readily observe that various modifications and alterations can be made to the apparatus and method while maintaining the teachings of this invention. Therefore, the above disclosure should be interpreted as being limited only by the boundaries and limits of the appended claims.

Claims

1. A semiconductor device, comprising: Substrate; A gate structure is disposed on the substrate; The source region and drain region are respectively disposed on both sides of the gate structure, and the source region and drain region are of the first conductivity type; A doped region is disposed below the gate structure, the source region, and the drain region and is separated from the gate structure, the source region, and the drain region, respectively. The doped region is a second conductivity type different from the first conductivity type. A channel region is disposed between the doped region and the gate structure, the channel region is in contact with the doped region, and the doping concentration of the channel region is less than the doping concentration of the doped region; as well as A trench surrounded by the channel region, wherein the gate structure is disposed in the trench.

2. The semiconductor device according to claim 1, wherein, A portion of the channel area conforms to the surface of the trench.

3. The semiconductor device according to claim 1, wherein, The top surface of the gate structure is higher than the top surfaces of the source region and the drain region.

4. The semiconductor device according to claim 1, wherein, The source region and the drain region are respectively separated from the gate structure.

5. The semiconductor device according to claim 1, further comprising: Multiple first silicide regions are disposed on the source region and the drain region; and A second silicide region is disposed on the gate structure, wherein each of the first silicide regions is laterally separated from the second silicide region.

6. The semiconductor device according to claim 1, wherein, A portion of the channel region is embedded in the doped region.

7. The semiconductor device according to claim 1, wherein, The channel region is also disposed between the doped region and the source region, and between the doped region and the drain region.

8. The semiconductor device according to claim 1, wherein, The doped region at the first depth includes a doping concentration equal to 5 × 10⁻⁶. 18 atoms / cm 3 Greater than 5×10 18 atoms / cm 3 And less than 1×10 20 atoms / cm 3 , or equal to 1×10 20 atoms / cm 3 .

9. The semiconductor device according to claim 1, wherein, The doped region has the maximum doping concentration at a first depth along the depth direction, and the bottom surface of the channel region below the gate structure is shallower than the first depth.

10. The semiconductor device according to claim 1, wherein, The doped region located below the source and drain regions includes a doping concentration of 5 × 10⁻⁶. 18 atoms / cm 3 Greater than 5×10 18 atoms / cm 3 And less than 1×10 20 atoms / cm 3 Or equal to 1×10 20 atoms / cm 3 .

11. A method of manufacturing a semiconductor device, comprising: Provide substrate; A doped region is formed on the substrate; A channel layer is formed on the doped region; Grooves are formed in the channel layer; A gate structure is formed in the trench, the gate structure being disposed above and separated from the doped region; as well as Source and drain regions are formed on both sides of the gate structure, and the source and drain regions are disposed above and separated from the doped region. The channel layer is in contact with the doped region, and the doping concentration of the channel layer is less than the doping concentration of the doped region.

12. The method according to claim 11, wherein, When the trench is formed in the channel layer, the doped region is exposed from the trench.

13. The method according to claim 12, wherein, The trench extends into the doped region.

14. The method of claim 12, further comprising: Before forming the gate structure in the trench, another channel layer is formed in the trench.

15. The method according to claim 14, wherein, The other channel layer conforms to the surface of the trench.

16. The method according to claim 11, wherein, The doped region is disposed below the gate structure, the source region, and the drain region, and is separated from the gate structure, the source region, and the drain region, respectively.

17. The method according to claim 11, wherein, The source region and the drain region are respectively separated from the gate structure.

18. The method of claim 11, further comprising: Forming a plurality of first silicide regions respectively disposed on the source region and the drain region; and A second silicide region is formed on the gate structure. Each of the first silicide regions is laterally separated from the second silicide region.

19. The method according to claim 11, wherein, The source region and the drain region are of a first conductivity type, and the doped region is of a second conductivity type different from the first conductivity type.

20. The method according to claim 11, wherein, The doped region at the first depth includes a doping concentration equal to 5 × 10⁻⁶. 18 atoms / cm 3 Greater than 5×10 18 atoms / cm 3 And less than 1×10 20 atoms / cm 3 , or equal to 1×10 20 atoms / cm 3 .

21. The method according to claim 11, wherein, The doped region has the maximum doping concentration at a first depth along the depth direction, and the bottom surface of the channel layer below the gate structure is shallower than the first depth.

22. The method according to claim 11, wherein, The doped region located below the source and drain regions includes a doping concentration of 5 × 10⁻⁶. 18 atoms / cm 3 Greater than 5×10 18 atoms / cm 3 And less than 1×10 20 atoms / cm 3 Or equal to 1×10 20 atoms / cm 3 .

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