analog front end device

Abstract

Analog front end device includes an amplifier circuit, a first gain control circuit, and a tracking circuit. The amplifier circuit is configured to generate a first output signal based on a first input signal. The first gain control circuit is configured to set a first electrical element based on a first gain control signal and transmit the first input signal to a first input terminal of the amplifier circuit via the first electrical element, wherein one end of the first electrical element is selectively coupled to the first input terminal or a first preset node. The tracking circuit is configured to adjust a level of the first preset node based on a level of the first input terminal to reduce a voltage difference between the first input terminal and the first preset node.

Description

Technical Field

[0001] This invention relates to an analog front-end device, and more particularly to an analog front-end device that can reduce the impact of transient errors. Background Technology

[0002] In analog front-end systems for communication applications, adjustable gain amplifier circuits are commonly used to amplify signals for processing by subsequent circuits. In existing technology, once the system determines the required specific gain based on the current signal, the gain of the adjustable gain amplifier circuit is fixed at that specific gain and cannot be adjusted further. However, during signal reception, temperature or other undesirable factors can cause a decrease in the signal-to-noise ratio (SNR) of the analog front-end system. If the gain of the adjustable gain amplifier circuit is adjusted during signal reception to mitigate the effects of temperature or other undesirable factors, the analog front-end system may be affected by transient responses during the gain adjustment process, leading to a decrease in the SNR and / or incorrect data output. Summary of the Invention

[0003] In some embodiments, the analog front-end device includes an amplifier circuit, a first gain control circuit, and a tracking circuit. The amplifier circuit generates a first output signal based on a first input signal. The first gain control circuit sets a first electrical component based on a first gain control signal and transmits the first input signal to a first input terminal of the amplifier circuit via the first electrical component, wherein one end of the first electrical component is selectively coupled to the first input terminal or a first preset node. The tracking circuit adjusts a level of the first preset node based on a level at the first input terminal to reduce the voltage difference between the first input terminal and the first preset node.

[0004] The features, implementation, and effects of the present invention are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0005] Figure 1A This is a schematic diagram illustrating a simulated front-end device according to some embodiments of the present invention;

[0006] Figure 1B This is a schematic diagram illustrating a simulated front-end device according to some embodiments of the present invention;

[0007] Figure 2A As illustrated in some embodiments of the present invention Figure 1A or Figure 1B A schematic diagram of the gain control circuit in the diagram;

[0008] Figure 2B As illustrated in some embodiments of the present invention Figure 1A orFigure 1B schematic diagram of a gain control circuit in

[0009] Figure 2C schematic diagram of a gain control circuit in Figure 1A or Figure 1B schematic diagram of a gain control circuit in

[0010] Figure 3A schematic diagram of a gain control circuit in Figure 1A or Figure 1B schematic diagram of a gain control circuit in

[0011] Figure 3B schematic diagram of a gain control circuit in Figure 1A or Figure 1B waveform diagram of a plurality of signals in

[0012] Figure 4A schematic diagram of a gain control circuit in Figure 2A waveform diagram of a plurality of bits in

[0013] Figure 4B schematic diagram of a gain control circuit in Figure 2A schematic diagram of a gain control circuit in DETAILED DESCRIPTION

[0014] All words used herein are to be interpreted in their normal and customary meaning. The words as described above are defined in the common and ordinary dictionary, and the use of any of the words discussed herein, as included in the context of the present invention, is merely by way of example and should not limit the scope and meaning of the present invention. Likewise, the present invention is not limited to only the various embodiments shown herein.

[0015] As used herein, "coupled" or "connected" can mean either a direct electrical or physical connection between two or more elements, or an indirect electrical or physical connection between two or more elements, and can mean that two or more elements are operatively or functionally associated or engaged with each other. As used herein, the term "circuitry" can mean a single system formed from at least one circuit, and the term "circuit" can mean a device that has at least one transistor and / or at least one passive element connected in a certain manner to process a signal.

[0016] As used herein, the term "and / or" includes any combination of one or more of the associated listed items. As used herein, the terms first, second, and third, etc. are used only to describe and distinguish various elements. Thus, the first element can also be referred to as the second element without departing from the spirit of the present invention. For ease of understanding, similar elements in the various drawings will be designated by identical reference numerals.

[0017] Figure 1A FIG. 1 shows a schematic diagram of an analog front-end device 100 according to some embodiments of the present disclosure. In some embodiments, the analog front-end device 100 can be applied in a communication system to perform preliminary processing (e.g., amplification, filtering, analog-to-digital conversion, etc.) on received signals (e.g., input signal VIN and input signal VIP) for use by subsequent circuits.

[0018] In some embodiments, the analog front-end device 100 includes an amplifier circuit 110, a gain control circuit 120, a gain control circuit 130, a tracking circuit 140, a deglitch circuit 150, a latch circuit 160, a latch circuit 170, and an analog-to-digital converter circuit 180.

[0019] The gain control circuits 120 and 130 are configured to set the amplification gain of the analog front-end device 100 according to a gain control signal PG1. In some embodiments, the gain control circuit 120 is configured to set an electrical element E1 (e.g., a capacitive element, a resistive element, etc.) in response to the gain control signal PG1 and to transmit the input signal VIN to a first input terminal (hereinafter referred to as terminal IN) of the amplifier circuit 110 via the electrical element E1. For example, the gain control circuit 120 can adjust the circuit configuration within the gain control circuit 120 to adjust the electrical element E1 according to a gain control signal PG3, which is generated based on the gain control signal PG1. Similarly, in some embodiments, the gain control circuit 130 is configured to set an electrical element E2 (e.g., a capacitive element, a resistive element, etc.) in response to the gain control signal PG1 and to transmit the input signal VIP to a second input terminal (hereinafter referred to as terminal IP) of the amplifier circuit 110 via the electrical element E2. For example, the gain control circuit 130 can adjust the circuit configuration within the gain control circuit 130 to adjust the electrical element E2 according to a gain control signal PG4, which is generated based on the gain control signal PG1. The amplifier circuit 110 can be a differential amplifier circuit (i.e., terminals IN and IP are differential input terminals) configured to generate output signals VO1 and VO2 according to the input signals VIN and VIP.

[0020] As Figure 1AAs shown, one end of electrical component E1 is selectively coupled to endpoint IN or preset node N1, and one end of electrical component E2 is selectively coupled to endpoint IP or preset node N2. In some embodiments, the tracking circuit 140 is used to adjust the level of preset node N1 according to the level of endpoint IN, and to adjust the level of preset node N2 according to the level of endpoint IP. For example, the tracking circuit 140 includes a single-gain buffer circuit 142 and a single-gain buffer circuit 144. The single-gain buffer circuit 142 is used to set the level of preset node N1 according to the level of endpoint IN. The single-gain buffer circuit 144 is used to set the level of preset node N2 according to the level of endpoint IP. Through the tracking circuit 140, the voltage difference between endpoint IN and preset node N1, and the voltage difference between endpoint IP and preset node N2 can be reduced. In this way, charge redistribution on electrical components E1 and E2 can be avoided during the adjustment of amplification gain, thereby reducing transient errors on output signals VO1 and VO2.

[0021] The surge suppression circuit 150 is used to suppress surges on the update signal U1 according to the clock signal CK1, so as to generate an update signal U2 (e.g., ...). Figure 3A As shown), it outputs a gain control signal PG2 based on the update signal U1 and the gain control signal PG1, and outputs the gain control signal PG2 and the update signal U2 to the latch circuit 160 and the latch circuit 170 based on the clock signal CK1. In this way, the impact of surges on the analog front-end circuit device 100 during the adjustment of the amplification gain can be reduced. The relevant settings of the surge elimination circuit 150 will be referred to below. Figure 3A This will be explained.

[0022] Latch circuit 160 can output gain control signal PG2 as gain control signal PG3 according to update signal U2. In this way, gain control circuit 120 can adjust electrical component E1 in response to gain control signal PG3 to adjust the amplification gain of analog front-end circuit device 100. Similarly, latch circuit 170 can output gain control signal PG2 as gain control signal PG4 according to update signal U2. Thus, gain control circuit 130 can adjust electrical component E2 in response to gain control signal PG4 to adjust the amplification gain of analog front-end circuit device 100. Through latch circuits 160 and 170, it can be ensured that gain control circuits 120 and 130 adjust electrical components E1 and E2 only after all bits of gain control signal PG1 have been switched. In this way, the time difference between the switching of multiple components in gain control circuits 120 and 130 can be reduced, thereby reducing transient errors on output signals VO1 and VO2. The configuration methods for latch circuits 160 and 170 will be provided below.Figure 4A and Figure 4B This will be explained.

[0023] The analog-to-digital converter circuit 180 samples the output signals VO1 and VO2 according to the clock signal CK2 to generate a digital output DO. In some embodiments, a phase difference between the clock signals CK1 and CK2 is set according to the transient error of the output signals VO1 (and / or VO2). This avoids the analog-to-digital converter circuit 180 sampling inaccurate output signals VO1 and VO2, thus providing an effective digital output DO. The relevant configuration method here will be referred to below. Figure 3B This will be explained.

[0024] Figure 1B This is a schematic diagram illustrating an analog front-end device 100A according to some embodiments of the present invention. Compared to Figure 1A The analog front-end device 100, in this example, has preset nodes N1 and N2 coupled to each other (e.g., both connected to AC ground) to have the same voltage level. A tracking circuit 140 is used to adjust the voltage levels of preset nodes N1 and N2 based on the voltage levels of endpoint IN and endpoint IP. For example, the tracking circuit 140 includes a sensing circuit 146 and a single-gain buffer circuit 148. The sensing circuit 146 generates a voltage V1 based on the voltage levels of endpoint IN and endpoint IP. In some embodiments, the sensing circuit 146 may include resistors R1 and R2. A first end of resistor R1 is coupled to endpoint IN, and a second end of resistor R1 is coupled to a first end of resistor R2, and is used to generate voltage V1. The second end of resistor R2 is coupled to endpoint IP. The single-gain buffer circuit 148 sets the voltage levels of preset nodes N1 and N2 based on voltage V1.

[0025] The above regarding Figure 1A or Figure 1B The arrangement of the tracking circuit 140 shown is merely an example, and the present invention is not limited thereto. Various arrangements of the tracking circuit 140 that can be used to reduce differential pressure are all within the scope of the present invention.

[0026] Figure 2A As illustrated in some embodiments of the present invention Figure 1A or Figure 1B A schematic diagram of the gain control circuit 120 is shown. In some embodiments, the gain control circuit 120 may be an AC coupling circuit, which can transmit the AC signal component in the input signal VIN to... Figure 1A or Figure 1Bthe input signal VIN. The second terminal of the capacitor C is coupled to the switch SW1 and the switch SW2. The switch SW1 is selectively turned on according to the bit B[1] to couple the second terminal of the capacitor C (equivalent to the electrical element El) to the end point IN. The switch SW2 is selectively turned on according to the bit b[1] to couple the second terminal of the capacitor C to the preset node Nl. In some embodiments, the analog front-end device 100 (and / or the analog front-end device 100A) can include a plurality of inverter circuits (not shown) that can generate a plurality of bits b[1] - b[n] (not all shown) according to the plurality of bits B[1] - B[n]. The corresponding one of the plurality of bits b[1] - b[n] (e.g., b[n]) has an opposite logic value from the corresponding one of the plurality of bits B[1] - B[n] (e.g., B[n]). For example, when the bit B[1] is logic value 1, the bit b[1] is logic value 0.

[0027] The plurality of switched-capacitor circuits 120[1] - 120[n] each includes a capacitor C, a switch SW1, and a switch SW2. The switches SW1 in the plurality of switched-capacitor circuits 120[1] - 120[n] are controlled via the plurality of bits B[1] - B[n], respectively, and the switches SW2 in the plurality of switched-capacitor circuits 120[1] - 120[n] are controlled via the plurality of bits B[1] - B[n], respectively. Taking the switched-capacitor circuit 120[1] as an example, a first terminal of the capacitor C receives the input signal VIN, and a second terminal of the capacitor C is coupled to the switch SW1 and the switch SW2. The switch SW1 is selectively turned on according to the bit B[1] to couple the second terminal of the capacitor C (equivalent to the electrical element El) to the end point IN. The switch SW2 is selectively turned on according to the bit b[1] to couple the second terminal of the capacitor C to the preset node Nl. In some embodiments, the analog front-end device 100 (and / or the analog front-end device 100A) can include a plurality of inverter circuits (not shown) that can generate a plurality of bits b[1] - b[n] (not all shown) according to the plurality of bits B[1] - B[n]. The corresponding one of the plurality of bits b[1] - b[n] (e.g., b[n]) has an opposite logic value from the corresponding one of the plurality of bits B[1] - B[n] (e.g., B[n]). For example, when the bit B[1] is logic value 1, the bit b[1] is logic value 0.

[0028] When the switch SW1 is turned on in response to the bit B[1], the switch SW2 is not turned on in response to the bit B[1]. Conversely, when the switch SW2 is turned on in response to the bit B[1], the switch SW1 is not turned on in response to the bit B[1]. In other words, the on period of the switch SW1 does not overlap with the on period of the switch SW2 to ensure that the second terminal of the capacitor C (equivalent to the electrical element El) is not simultaneously connected to the end point IN and the preset node Nl. By the above arrangement, the voltage disturbance generated by the gain control circuit 120 during the switching process can be reduced to reduce the charge redistribution among the plurality of capacitors C in the plurality of switched-capacitor circuits 120[1] - 120[n]. In this way, the transient error on the output signal VO1 and the output signal VO2 can be reduced.

[0029] When the number of capacitors C connected in parallel between the node of the end point IN and receiving the input signal VIN increases, the equivalent capacitance (i.e. the electrical element E1 formed by the plurality of capacitors C) increases, and the AC impedance of the electrical element E1 decreases. In this way, the energy of the AC component in the input signal VIN transmitted to the end point IN via the gain control circuit 120 can be increased. In this way, the amplification gain of the analog front-end device 100 can be increased. Alternatively, when the number of capacitors C connected in parallel between the node of the end point IN and receiving the input signal VIN decreases, the equivalent capacitance (i.e. the electrical element E1 formed by the plurality of capacitors C) decreases, and the AC impedance of the electrical element E1 increases. In this way, the energy of the AC component in the input signal VIN transmitted to the end point IN via the gain control circuit 120 can be decreased. In this way, the amplification gain of the analog front-end device 100 can be decreased.

[0030] In some embodiments, the capacitance of the capacitor C of at least a first one of the plurality of switched-capacitor circuits 120[1] to 120[n] can be set according to a transient error of the output signal VO1, and the at least a first one of the plurality of switched-capacitor circuits 120[1] to 120[n] corresponds to at least a most significant bit of the plurality of bits B[1] to B[n]. In some embodiments, the capacitance of the capacitor C of the at least a first one of the plurality of switched-capacitor circuits 120[1] to 120[n] is set according to a thermometer code, the capacitance of the capacitor C of at least a second one of the plurality of switched-capacitor circuits 120[1] to 120[n] is set according to a binary code, and the at least a second one of the plurality of switched-capacitor circuits 120[1] to 120[n] corresponds to at least a least significant bit of the plurality of bits B[1] to B[n]. It should be understood that the most significant bit and the least significant bit are used only for illustrating the difference in capacitance between the bits of the capacitor C, and are not used to limit the present application.

[0031] For example, if n equals 11, the capacitance of the capacitor C of the plurality of switched-capacitor circuits 120[1] to 120[n] can be set according to the following table:

[0032] Bit B

[11] B

[10] B[9] B[8] B[7] B[6] B[5] B[4] B[3] B[2] B[1] Capacity 128 64 64 64 64 32 32 16 8 4 2

[0033] wherein bits B[7] to B

[11] are the most significant bits, and bits B[1] to B[6] are the least significant bits. Assume that the transient error (i.e. voltage disturbance) on the output signal VO1 that can be tolerated by the current application is, for example, Figure 3BIf the upper limit of the transient error ER corresponds to a capacitance switching value of 128 unit capacitances, then during the output of the data by the analog front-end device 100, the capacitances C corresponding to the high-weight bits (e.g., bits B[7] to B

[10] ) that can be used to adjust the amplification gain will be set to no more than 64 unit capacitances. The capacitances C corresponding to the low-weight bits (i.e., the least significant bits) will be set in binary code to save the number of circuit elements (e.g., switches).

[0034] For example, the capacitances C corresponding to bits B[7] to B

[10] can be set to 64 unit capacitances in thermometer code, and the capacitances C corresponding to bits B[1] to B[6] can be set to 2 unit capacitances, 4 unit capacitances,..., 32 unit capacitances in binary sequence. The switching capacitance circuits 120[1] to 120

[10] corresponding to the bits B[1] to B

[10] can be set as fine tuning circuits that can be used to adjust the amplification gain of the analog front-end device 100 during the output of the data (i.e., the digital output DO) by the analog front-end device 100. In this way, the transient error on the output signal VO1 (and / or the output signal VO2) can be prevented from being too large, so as to reduce the impact on the signal-to-noise ratio of the analog front-end device 100. For example, during the output of the data by the analog front-end device 100, the fine tuning circuits can be dynamically adjusted by the switching capacitance circuits 120[1] to 120

[10] according to the current operating temperature, so as to instantaneously adjust the amplification gain of the analog front-end device 100. In addition, in this example, the capacitance C corresponding to bit B

[11] is set to 128 unit capacitances. The switching capacitance circuit 120

[11] corresponding to bit B

[11] can be set as a coarse tuning circuit that is used to adjust the amplification gain of the analog front-end device 100 before the output of the data (i.e., the digital output DO) by the analog front-end device 100, but cannot be adjusted during the output of the data by the analog front-end device 100. In this way, the adjustable range of the amplification gain of the analog front-end device 100 can be further improved. It should be understood that the values, the transient error, and the adjustable range in the foregoing embodiments are merely illustrative and are not intended to limit the present application.

[0035] Figure 2B FIG. 1 shows a schematic diagram of a gain control circuit 120 according to some embodiments of the present application. Figure 1A or Figure 1B FIG. 1 shows a schematic diagram of a gain control circuit 120 according to some embodiments of the present application.

[0036] For example, such as Figure 2B As shown, the feedback network FB1 and amplifier circuit 110 are configured as a bandpass filter, wherein the gain control circuit 120 can be used to implement the resistor R in the feedback network FB1. In other words, the gain control circuit 120 includes multiple switching resistor circuits, which can provide an equivalent resistance as an electrical element E1 (i.e., resistor R) according to multiple bits B[1]~B[n].

[0037] Figure 2C As illustrated in some embodiments of the present invention Figure 1A or Figure 1B A schematic diagram of the gain control circuit 120 is shown. Similarly, in this example, the gain control circuit 120 may be at least a portion of the feedback network FB2 of the amplifier circuit 110.

[0038] The feedback network FB2 and amplifier circuit 110 are configured as a bandpass filter, wherein the gain control circuit 120 can be used to implement capacitors C1 and C2 in the feedback network FB2. In other words, the gain control circuit 120 includes multiple switching capacitor circuits, which can provide an equivalent capacitance as an electrical element E1 (i.e., a combination of capacitors C1 and C2) according to multiple bits B[1] to B[n].

[0039] The above examples are for illustrative purposes only, and the invention is not limited thereto. The configuration of the gain control circuit 120 can be adjusted according to the needs of the actual application. For clarity, Figure 2B The example provided illustrates a single-ended signal application, but the invention is not limited thereto. In some embodiments, the gain control circuit 130 may be configured in the same way as the gain control circuit 120, and therefore will not be described again here.

[0040] Figure 3A As illustrated in some embodiments of the present invention Figure 1A or Figure 1B A schematic diagram of the surge suppression circuit 150 is shown. The surge suppression circuit 150 includes multiple flip-flop circuits 301-305 and a multiplexer circuit 306. The multiple flip-flop circuits 301-305 may be (but are not limited to) D-type flip-flops. The multiple flip-flop circuits 301-304 output the update signal U1 as the update signal U2' according to the clock signal CK1, and output the update signal U2' as the update signal U2 according to the clock signal CK1. In detail, flip-flop circuits 301 and 302 are connected in series to output the update signal U1 as the update signal U2' according to the clock signal CK1. In this way, surges on the update signal U1 can be eliminated. Flip-flop circuits 303 and 304 are connected in series to output the update signal U2' as the update signal U2 according to the clock signal CK1.

[0041] Multiplexer circuit 306 is used to output gain control signal PG2' from gain control signal PG2 or gain control signal PG1 according to update signal U2'. Flip circuit 305 can output gain control signal PG2' as gain control signal PG2 according to clock signal CK1. For example, if update signal U2' has a logic value of 1, multiplexer circuit 306 outputs gain control signal PG1 as gain control signal PG2'. In this way, flip circuit 305 can output gain control signal PG2' as gain control signal PG2 according to clock signal CK1, so as to update multiple bits of gain control signal PG3 (e.g., for...) according to gain control signal PG1. Figure 2A Multiple bits B[1] to B[n] in the signal are used to adjust the amplification gain. Alternatively, if the update signal U2' has a logic value of 0, the multiplexer circuit 306 outputs the previous gain control signal PG2 as the gain control signal PG2'. In this way, multiple bits in the gain control signal PG2 output by the flip-flop circuit 305 will remain unchanged to maintain the current amplification gain.

[0042] The above-described configuration of the surge suppression circuit 150 is merely an example, and the present invention is not limited thereto. In some embodiments, depending on actual application requirements, the surge suppression circuit 150 may include a level shifter (not shown) to adjust the level of one or more internal signals in the surge suppression circuit 150.

[0043] Figure 3B As illustrated in some embodiments of the present invention Figure 1A or Figure 1B Waveforms of multiple signals are shown. When the update signal U1 has a preset level (e.g., a high level, corresponding to logic value 1), latch circuit 160 and latch circuit 170 can be triggered to output gain control signal PG2, which serves as gain control signal PG3 and gain control signal PG4 to adjust the amplification gain. In some embodiments, in order to adjust the amplification gain, the gain control signal PG1 is switched before time T0 (i.e., there is a state transition between multiple bits B[1] to B[n]), and the update signal U1 only has the preset level after time T0. The multiplexer circuit 306 can output the updated gain control signal PG1 as gain control signal PG2' according to the update signal U2' (which is equivalent to the delayed update signal U1). In this way, when the update signal U2 has a preset level, latch circuit 160 and latch circuit 170 can be triggered to output gain control signal PG2, which serves as gain control signal PG3 and gain control signal PG4. By using the above configuration, it can be ensured that multiple gain control circuits 120 and gain control circuit 130 switch at the same time point, thereby reducing transient errors in output signals VO1 and VO2.

[0044] Further, as previously described, a phase difference between the clock signal CK1 and the clock signal CK2 is set according to a transient error (e.g., a transient error ER) of the output signal VO1 (and / or the output signal VO2). For example, during a circuit design stage, the glitch cancellation circuit 150 can be tested with the clock signal CK1 having different phases (e.g., phase 1 to phase 4 in FIG. 4, where a difference between each two adjacent phases is 90 degrees). As shown in FIG. 4, the time point when the gain control signal PG2 is output as the gain control signal PG3 (and / or the gain control signal PG4) is also different according to the clock signal CK1 having different phases. In this way, the output signal VO1 (and / or the output signal VO2) will generate a corresponding transient error ER at a corresponding time point. To avoid that the analog-to-digital converter circuit 180 samples the transient error ER, the clock signal CK1 having a suitable phase can be selected according to the test results. For example, the analog-to-digital converter circuit 180 samples the output signal VO1 and the output signal VO2 according to a rising edge of the clock signal CK2. The transient error ER corresponding to the phase 1 does not overlap with the rising edge of the clock signal CK2. Therefore, the clock signal CK1 having the phase 1 can be selected as the final clock signal CK1. Figure 3B Figure 3B Figure 3B

[0045] In the above example, the final clock signal CK1 has the same phase as the clock signal CK2 (i.e., a phase difference of 0), but the present disclosure is not limited thereto. According to different test results, the phase difference between the final clock signal CK1 and the clock signal CK2 can be a predetermined value.

[0046] Figure 4A FIG. 3 shows a partial waveform diagram of the bit B[1] and the bit B[1] in the circuit 100 according to some embodiments of the present disclosure. As previously described, the on period of the switch SW1 and the on period of the switch SW2 do not overlap with each other. If each of the switch SW1 and the switch SW2 is an N-type transistor (e.g., but not limited to a MOSFET), the switch SW1 is turned on when the level of the bit B[1] is higher than a threshold voltage TH of the switch SW1, and the switch SW2 is turned on when the level of the bit B[1] is higher than a threshold voltage TH of the switch SW2. As shown in FIG. 3, the on period of the switch SW1 and the on period of the switch SW2 do not overlap with each other. In this way, the switch SW1 and the switch SW2 are not turned on at the same time, and the glitch cancellation circuit 150 can effectively cancel the glitch. Figure 2A Figure 4A ​​​​As shown, during the transition between bits B[1] and b[1], the boundary between the rising edge of one of bits B[1] and b[1] and the falling edge of the other of bits B[1] and b[1] is below the critical voltage TH. By using the above configuration, it can be ensured that the conduction period of switch SW1 and the conduction period of switch SW2 do not overlap, thereby reducing the voltage disturbance experienced by multiple capacitors C during the switching process and reducing the charge redistribution among multiple capacitors C. In this way, the transient errors on output signals VO1 and VO2 can be reduced.

[0047] Figure 4B As illustrated in some embodiments of the present invention Figure 2A A schematic diagram of the latch circuit 160. The latch circuit 160 includes a positive feedback circuit 401 and multiple output stage circuits 402-403. For ease of understanding, Figure 4B Only the circuit portion that processes one bit of the gain control signal PG2 (e.g., B[1]', which corresponds to bit B[1] of the gain control signal PG3) is shown.

[0048] The positive feedback circuit 401 is used to trigger according to the update signal U2 to generate signals S1 and S1b according to bit B[1]' and the corresponding bit b[1]' (which has the opposite logic value to bit B[1]'). For example, when the positive feedback circuit 401 is triggered according to the update signal U2 and the update signal U2B (which has the opposite logic value to the update signal U2), the positive feedback circuit 401 can quickly adjust the level of signal S1 to a first preset level (e.g., system high voltage or system low voltage) and transmit signal S1 to the output stage circuit 402. Similarly, when the positive feedback circuit 401 is triggered according to the update signal U2 and the update signal U2B, the positive feedback circuit 401 can quickly adjust the level of signal S1b to a second preset level (which is opposite to the first preset level) and transmit signal S1b to the output stage circuit 403. Multiple output stage circuits 402 to 403 can output signals S1 and S1b as bit B[1] and bit b[1], respectively.

[0049] In some embodiments, the pull-up current of each of the plurality of output stage circuits 402-403 is different from the pull-down current of each of the plurality of output stage circuits 402-403. For example, taking output stage circuit 402 as an example, output stage circuit 402 includes pull-up transistor M1 and pull-down transistor M2. The aspect ratio of pull-up transistor M1 can be set to be smaller than the aspect ratio of pull-down transistor M2. In this way, the pull-up current I1 generated by pull-up transistor M1 will be smaller than the pull-down current I2 generated by pull-down transistor M2, so as to generate... Figure 4AThe waveforms at the low junctions in FIG. 6A are similar to those in FIG. 5A. The output stage circuit 403 is configured in the same manner as the output stage circuit 402, and thus is not repeated here.

[0050] The configuration of the latch circuit 160 is for illustration only, and the present application is not limited thereto. Any latch circuit 160 that can pass data according to the update signal U2, such as outputting bit B[l]' as bit B[l], is within the scope of the present application. It should be understood that in Figure 2A If the switches SWl and SW2 are implemented as P-type transistors, then in Figure 4A During the transitions of bit B[l] and bit b[l], the rising edge of one of bit B[l] and bit b[l] meets the falling edge of the other of bit B[l] and bit b[l] at a high junction. Correspondingly, during the transitions of bit B[l]' and bit b[l]', the rising edge of one of bit B[l]' and bit b[l]' meets the falling edge of the other of bit B[l]' and bit b[l]' at a low junction. Figure 4B In FIG. 6B, the aspect ratio of the pull-up transistor Ml can be configured to be greater than that of the pull-down transistor M2. In this way, the pull-up current I1 generated by the pull-up transistor Ml can be greater than the pull-down current I2 generated by the pull-down transistor M2, to generate the waveforms at the high junctions described above. The latch circuit 170 is configured in the same manner as the latch circuit 160, and thus is not repeated here.

[0051] The above embodiments are described with respect to differential circuits, but the present application is not limited thereto. For example, the analog front-end device 100 can be applied to single-ended signals, in which the end point IP can directly receive a common-mode voltage without using the gain control circuit 130 and the latch circuit 170.

[0052] It should be understood that the scope of the present application is not limited to the configurations shown in the figures. In different embodiments, the analog front-end device 100 can employ at least one of the gain control circuit 120 (and / or the gain control circuit 130), the tracking circuit 140, the glitch elimination circuit 150, or the latch circuit 160 (and / or the latch circuit 170) to reduce the transient errors on the output signal VOl (and / or the output signal VO2). In some embodiments, if the analog front-end device 100 does not employ the glitch elimination circuit 150, the gain control signal PGl can be directly input to the latch circuit 160 (and / or the latch circuit 170) (i.e., replacing the gain control signal PG2). In some embodiments, if the analog front-end device 100 does not employ the glitch elimination circuit 150 and the latch circuit 160 (and / or the latch circuit 170), the gain control signal PGl can be directly input to the gain control circuit 120 (and / or the gain control circuit 130) (i.e., replacing the gain control signal PG3 and the gain control signal PG4).

[0053] In summary, the analog front-end device provided in some embodiments of the present application can utilize various circuit techniques to reduce the influence of transient errors on the output signal during adjustment of the amplification gain, so as to improve the overall signal-to-noise ratio of the system. In this way, the amplification gain can be continuously adjusted during output of data by the analog front-end device, so as to instantaneously reduce the influence of temperature or other undesirable factors.

[0054] Although the embodiments of the present application are described above, these embodiments are not intended to limit the present application, and those skilled in the art can make changes to the technical features of the present application according to the content explicitly or implicitly disclosed in the present application, and these changes can all fall within the scope of the patent protection required by the present application. In other words, the scope of the patent protection of the present application should be defined according to the claims of the present application.

[0055] Legend of reference signs:

[0056] 100: analog front-end device

[0057] 100A: analog front-end device

[0058] 110: amplifier circuit

[0059] 120, 130: gain control circuit

[0060] 140: tracking circuit

[0061] 142, 144, 148: single-gain buffer circuit

[0062] 146: sensing circuit

[0063] 150: spike cancellation circuit

[0064] 160, 170: latch circuit

[0065] 180: analog-to-digital converter circuit

[0066] 301-305: flip-flop circuit

[0067] 306: multiplexer circuit

[0068] 401: positive feedback circuit

[0069] 402, 403: output stage circuit

[0070] B[1]-B[n], b[1]-b[n], B[1]', b[1]': bit

[0071] C, C1, C2: capacitor

[0072] CK1, CK2: clock signal

[0073] DO: digital output

[0074] E1, E2: electrical element

[0075] ER: transient error

[0076] FB1, FB2: feedback network

[0077] I1: pull-up current

[0078] I2: pull-down current

[0079] IN, IP: endpoint

[0080] M1: pull-up transistor

[0081] M2: pull-down transistor

[0082] N1, N2: preset node

[0083] PG1, PG2, PG2', PG3, PG4: gain control signal

[0084] R, R1, R2: resistance

[0085] S1, S1b: signal

[0086] SW1, SW2: switch

[0087] T0: time

[0088] TH: threshold voltage

[0089] U1, U2, U2B, U2': update signal

[0090] V1: voltage

[0091] VIN, VIP: input signal

[0092] VO1, VO2: output signal

Claims

1. An analog front-end device, comprising: An amplifier circuit for generating a first output signal based on a first input signal; A first gain control circuit is configured to set a first electrical component according to a first gain control signal, and transmit the first input signal to a first input terminal of the amplifier circuit via the first electrical component, wherein one end of the first electrical component is selectively coupled to the first input terminal or a first preset node. as well as A tracking circuit is used to adjust the voltage level of the first preset node according to the voltage level of the first input terminal, so as to reduce the voltage difference between the first input terminal and the first preset node.

2. The analog front-end device according to claim 1, characterized in that, The first gain control circuit is an AC coupling circuit or a feedback network.

3. The analog front-end device according to claim 1, characterized in that, The first gain control circuit includes: a plurality of switchable capacitor circuits, used to switch according to a plurality of bits of the first gain control signal to provide an equivalent capacitance as the first electrical element. Each of the plurality of switching capacitor circuits includes a capacitor, the capacitance value of the capacitor of at least one first circuit of the plurality of switching capacitor circuits is set according to the transient error of the first output signal, and the at least one first circuit corresponds to at least one most significant bit of the plurality of bits.

4. The analog front-end device according to claim 3, characterized in that, The capacitance value of the capacitor in the at least one first circuit is set based on a thermometer code, and the capacitance value of the capacitor in the at least one second circuit of the plurality of switching capacitor circuits is set based on a binary code, and the at least one second circuit corresponds to at least one least significant bit among the plurality of bits.

5. The analog front-end device according to claim 1, characterized in that, The tracking circuit is a single-gain buffer circuit, and the single-gain buffer circuit is used to set the level of the first preset node according to the level of the first input terminal.

6. The analog front-end device according to claim 1, characterized in that, The amplifier circuit is further configured to generate the first output signal and the second output signal based on the first input signal and the second input signal, and the analog front-end device further includes: A second gain control circuit is configured to set a second electrical element according to the first gain control signal and transmit the second input signal to a second input terminal of the amplifier circuit via the second electrical element, wherein one end of the second electrical element is selectively coupled to the second input terminal or a second preset node, wherein the tracking circuit is further configured to adjust a level of the second preset node according to a level of the second input terminal, or according to the level of the first input terminal and the level of the second input terminal, so as to reduce the voltage difference between the second input terminal and the second preset node.

7. The analog front-end device according to claim 6, characterized in that, The tracking circuit includes: A sensing circuit for generating a first voltage based on the level of the first input terminal and the level of the second input terminal; and A single-gain buffer circuit is used to set the level of the first preset node according to the first voltage, wherein the first preset node and the second preset node are coupled to each other.

8. The analog front-end device according to claim 1, further comprising: A surge suppression circuit is configured to suppress a surge on a first update signal based on a first clock signal to generate a second update signal, and to output a second gain control signal based on the first update signal and a first gain control signal, and to output the second update signal and the second gain control signal based on the first clock signal; and A latch circuit is used to output the second gain control signal as a third gain control signal based on the second update signal. The first gain control circuit is used to set the first electrical component according to the third gain control signal.

9. The analog front-end device according to claim 8, further comprising: An analog-to-digital converter circuit is used to sample the first output signal according to a second clock signal to generate a digital output. The phase difference between the first clock signal and the second clock signal is set according to the transient error of the first output signal.

10. The analog front-end device according to claim 1, characterized in that, The first gain control circuit includes multiple switches. When a first switch among the multiple switches is turned on, the end of the first electrical element is coupled to the first input terminal via the first switch. When a second switch among the multiple switches is turned on, the end of the first electrical element is coupled to the first preset node via the second switch. The on period of the first switch and the on period of the second switch do not overlap.

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