Semiconductor structure and method of fabrication

Abstract

The embodiment of the present application discloses a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor structure comprises the following steps: forming a first laminated structure with a plurality of first capacitor holes on a substrate, and filling the first capacitor holes with columnar lower electrodes; forming a first opening on the top of the first laminated structure between the columnar lower electrodes, and forming a second laminated structure on the first opening, the first laminated structure and the columnar lower electrodes; forming a second capacitor hole on the second laminated structure and the top of the first laminated structure, and exposing the top and part of the sidewall of the columnar lower electrode; and forming a cup-shaped lower electrode on the bottom and the sidewall of the second capacitor hole, that is, the cup-shaped lower electrode covers at least part of the sidewall of the columnar lower electrode, so that the columnar lower electrode and the cup-shaped lower electrode of the upper and lower two layers have good contact, and the cup-shaped lower electrode and the columnar lower electrode jointly form a high-aspect-ratio lower electrode, thereby improving the storage capacity of the semiconductor structure and obtaining a semiconductor structure with stable capacitor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in computers, composed of many repeating memory cells. With the continuous evolution of semiconductor memory technology, shrinking the size of DRAM structures is a crucial direction for increasing device density. High aspect ratio DRAM capacitors are fabricated to ensure sufficient storage capacity per unit area. However, with high aspect ratio capacitors, it is difficult to guarantee sufficient stability in the capacitor structure. Summary of the Invention

[0003] This application provides a semiconductor structure and fabrication method that improves the storage capacity of a capacitor while ensuring its stability.

[0004] According to some embodiments, a first aspect of this application provides a method for fabricating a semiconductor structure, comprising:

[0005] Provide substrate;

[0006] A first stacked structure having a plurality of first capacitor holes is formed on the substrate;

[0007] A columnar lower electrode is formed in the first capacitor hole;

[0008] A first opening is formed at the top of the first stacked structure between the columnar lower electrodes;

[0009] A second stacked structure is formed on the first opening, the first stacked structure, and the columnar lower electrode;

[0010] A second capacitor hole is formed in the top portion of the second stacked structure and the first stacked structure, the second capacitor hole exposing the top and part of the sidewall of the columnar lower electrode;

[0011] A cup-shaped lower electrode is formed at the bottom and sidewall of the second capacitor hole.

[0012] In one embodiment, the first stacked structure includes a first support layer, a first sacrificial layer, and a second support layer stacked sequentially;

[0013] The first opening is located between the columnar lower electrodes and is formed in the second support layer.

[0014] In one embodiment, the opening size of the second capacitor hole is larger than the opening size of the first capacitor hole; the opening of the second capacitor hole is directly opposite the first capacitor hole.

[0015] In one embodiment, the step of forming a cup-shaped lower electrode at the bottom and sidewall of the second capacitor hole includes:

[0016] A cup-shaped lower electrode material layer is formed on the sidewall of the second capacitor hole, the bottom of the second capacitor hole, and the upper surface of the second stacked structure;

[0017] A filling layer is formed, the filling layer filling the second capacitor hole;

[0018] Remove the cup-shaped lower electrode material layer located on the upper surface of the second stacked structure;

[0019] Remove the filler layer.

[0020] In one embodiment, the second stacked structure includes a second sacrificial layer and a third support layer.

[0021] In one embodiment, it further includes:

[0022] A second opening is formed on the third support layer;

[0023] The second sacrificial layer and the first sacrificial layer are removed using the second opening and the first opening, respectively.

[0024] In one embodiment, it further includes:

[0025] A dielectric layer is formed on the surfaces of the columnar lower electrode and the cup-shaped lower electrode;

[0026] An upper electrode is formed on the surface of the dielectric layer, and the upper electrode also fills the gap between the columnar lower electrode and the cup-shaped lower electrode.

[0027] In one embodiment, the filling layer comprises photoresist, and the filling layer at least fills the upper portion of the second capacitor hole opening.

[0028] In one embodiment, the bottom of the second capacitor hole exposes the first sacrificial layer or is located within the first sacrificial layer.

[0029] In one embodiment, the etching rate of the first sacrificial layer is greater than that of the second sacrificial layer.

[0030] In one embodiment,

[0031] The steps of forming the columnar lower electrode and the cup-shaped lower electrode described above are repeated at least once to form a multilayer stack of the columnar lower electrode and the cup-shaped lower electrode on the substrate.

[0032] According to some embodiments, a second aspect of this application provides a semiconductor structure comprising:

[0033] Substrate;

[0034] A plurality of columnar lower electrodes and cup-shaped lower electrodes are spaced apart on the substrate, wherein the cup-shaped lower electrodes are located above the columnar lower electrodes and are connected to the columnar lower electrodes one by one;

[0035] The first support layer and the second support layer are located between the bottom and top of the columnar lower electrode, respectively;

[0036] The bottom of the cup-shaped lower electrode at least covers a portion of the side surface of the columnar lower electrode.

[0037] In one embodiment, the width of the cup-shaped lower electrode is greater than the width of the columnar lower electrode.

[0038] In one embodiment, a third support layer is also included, which is located between the tops of the cup-shaped lower electrodes.

[0039] In one embodiment, the bottom of the cup-shaped lower electrode covers the top of the columnar lower electrode and a portion of the sidewall of the columnar lower electrode.

[0040] In one embodiment, the bottom surface of the cup-shaped lower electrode located on the sidewall portion of the columnar lower electrode is lower than the bottom surface of the second support layer.

[0041] In one embodiment, it further includes:

[0042] The dielectric layer located on the surfaces of the columnar lower electrode and the cup-shaped lower electrode;

[0043] And an upper electrode located on the surface of the dielectric layer, wherein the upper electrode also fills the gap between the columnar lower electrode and the cup-shaped lower electrode.

[0044] In the semiconductor structure and fabrication method provided in the above embodiments, a first stacked structure having a plurality of first capacitor holes is formed on a substrate, and a columnar lower electrode fills the first capacitor holes; a first opening is formed at the top of the first stacked structure between the columnar lower electrodes, and a second stacked structure is formed on the first opening, the first stacked structure, and the columnar lower electrode; a second capacitor hole is formed at the top of the second stacked structure and a portion of the top of the first stacked structure, and the second capacitor hole exposes the top and a portion of the sidewall of the columnar lower electrode, that is, the opening size of the second capacitor hole is larger than the opening size of the first capacitor hole; and a cup-shaped lower electrode is formed at the bottom and sidewall of the second capacitor hole, that is, the cup-shaped lower electrode at least covers a portion of the sidewall of the columnar lower electrode. The etched second capacitor hole solves the alignment problem of the upper and lower capacitor holes, ensuring good contact between the upper and lower columnar lower electrodes and the cup-shaped lower electrode. The cup-shaped lower electrode and the columnar lower electrode together form a lower electrode with a high aspect ratio, thereby improving the storage capacity of the semiconductor structure while obtaining a semiconductor structure with a stable capacitor structure. Attached Figure Description

[0045] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained from these drawings without creative effort.

[0046] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor structure provided in one embodiment of this application;

[0047] Figure 2 This is a partial cross-sectional schematic diagram of the structure obtained after forming a first stacked structure on a substrate according to an embodiment of this application;

[0048] Figure 3 This is a partial cross-sectional schematic diagram of the structure obtained after forming a first capacitor hole in the first stacked structure according to an embodiment of this application;

[0049] Figure 4 This is a partial cross-sectional schematic diagram of the structure obtained after forming a columnar lower electrode material layer in one embodiment of this application;

[0050] Figure 5 This is a partial cross-sectional schematic diagram of the structure obtained after forming a columnar lower electrode layer according to an embodiment of this application;

[0051] Figure 6 This is a schematic diagram of a partial cross-sectional structure of the structure obtained after forming the first opening, as provided in one embodiment of this application.

[0052] Figure 7This is a partial cross-sectional schematic diagram of the structure obtained after forming the second laminated structure according to an embodiment of this application;

[0053] Figure 8 This is a partial cross-sectional schematic diagram of the structure obtained after forming the second capacitor hole in one embodiment of this application;

[0054] Figure 9 This is a partial cross-sectional schematic diagram of the structure obtained after forming a cup-shaped lower electrode material layer in one embodiment of this application;

[0055] Figure 10 This is a partial cross-sectional structural diagram of the structure obtained after forming the filling layer in one embodiment of this application;

[0056] Figure 11 This is a partial cross-sectional schematic diagram of the structure obtained after forming a cup-shaped lower electrode layer according to an embodiment of this application;

[0057] Figure 12 This is a partial cross-sectional structural diagram of the structure obtained after removing the filler layer in one embodiment of this application;

[0058] Figure 13 This is a partial cross-sectional structural diagram of the structure obtained by removing the first sacrificial layer and the second sacrificial layer according to an embodiment of this application;

[0059] Figure 14 This is a partial cross-sectional schematic diagram of the structure obtained after forming dielectric layers on the surfaces of the columnar lower electrode and the cup-shaped lower electrode in one embodiment of this application.

[0060] Figure 15 This is a partial cross-sectional structural diagram of the structure obtained by forming the upper electrode in one embodiment of this application;

[0061] Figure 16 This is a partial cross-sectional structural diagram of the structure obtained after forming the second laminated structure according to another embodiment of this application;

[0062] Figure 17 This is a partial cross-sectional schematic diagram of the structure obtained after forming the second capacitor hole in another embodiment of this application;

[0063] Figure 18 This is a partial cross-sectional structural diagram of the structure obtained after forming a cup-shaped lower electrode material layer according to another embodiment of this application;

[0064] Figure 19 This is a partial cross-sectional structural diagram of the structure obtained after forming the filling layer according to another embodiment of this application;

[0065] Figure 20This is a partial cross-sectional schematic diagram of the structure obtained after forming a cup-shaped lower electrode layer according to another embodiment of this application;

[0066] Figure 21 This is a partial cross-sectional structural diagram of the structure obtained after removing the filler layer according to another embodiment of this application;

[0067] Figure 22 This is a partial cross-sectional structural diagram of the structure obtained after forming a second opening on the third support layer in one embodiment of this application;

[0068] Figure 23 This is a partial cross-sectional structural diagram of the structure obtained after removing the first sacrificial layer and the second sacrificial layer according to another embodiment of this application;

[0069] Figure 24 This is a partial cross-sectional schematic diagram of the structure obtained after forming dielectric layers on the surfaces of the columnar lower electrode and the cup-shaped lower electrode, as provided in another embodiment of this application.

[0070] Figure 25 This is a schematic diagram of a partial cross-sectional structure of the structure obtained by forming the upper electrode according to another embodiment of this application;

[0071] Figure 26 This is a partial cross-sectional schematic diagram of a four-layer stacked semiconductor structure formed in one step by repeatedly forming a columnar lower electrode and a cup-shaped lower electrode, as provided in one embodiment of this application.

[0072] Explanation of reference numerals in the attached figures: 11-substrate, 12-contact plug, 13-first stacked structure, 131-first support layer, 132-first sacrificial layer, 133-second support layer;

[0073] 14-First capacitor hole, 15-Columnar lower electrode layer, 151-Columnar lower electrode material layer;

[0074] 16 - First opening;

[0075] 21-Second stacked structure, 211-Second sacrificial layer, 212-Third support layer, 2121-Second opening;

[0076] 22 - Second capacitor hole;

[0077] 23-Cup-shaped lower electrode, 231-Cup-shaped lower electrode material layer;

[0078] 24-filling layer, 25-dielectric layer, 26-top electrode. Detailed Implementation

[0079] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of this application more thorough and complete.

[0080] In one embodiment of this application, such as Figure 1 As shown, a method for fabricating a semiconductor structure is provided, comprising the following steps:

[0081] Step S10: Provide a substrate;

[0082] Step S20: Form a first stacked structure having a plurality of first capacitor holes on the substrate;

[0083] Step S30: Form a columnar lower electrode in the first capacitor hole;

[0084] Step S40: A first opening is formed at the top of the first stacked structure between the columnar lower electrodes;

[0085] Step S50: A second stacked structure is formed on the first opening, the first stacked structure, and the columnar lower electrode;

[0086] Step S60: A second capacitor hole is formed in the top portion of the second stacked structure and the first stacked structure, the second capacitor hole exposing the top and part of the sidewall of the columnar lower electrode;

[0087] Step S70: A cup-shaped lower electrode is formed at the bottom and sidewall of the second capacitor hole.

[0088] In the semiconductor structure and fabrication method provided in the above embodiments, a first stacked structure with a plurality of first capacitor holes is formed on a substrate, and a columnar lower electrode fills the first capacitor holes; a first opening is formed at the top of the first stacked structure between the columnar lower electrodes, and a second stacked structure is formed on the first opening, the first stacked structure, and the columnar lower electrode; a second capacitor hole is formed at the top of the second stacked structure and a portion of the top of the first stacked structure, and the second capacitor hole exposes the top and part of the sidewall of the columnar lower electrode, that is, the opening size of the second capacitor hole is larger than the opening size of the first capacitor hole; and a cup-shaped lower electrode is formed at the bottom and sidewall of the second capacitor hole, that is, the cup-shaped lower electrode at least covers part of the sidewall of the columnar lower electrode. The etched second capacitor hole solves the alignment problem of the upper and lower capacitor holes, ensuring good contact between the upper and lower columnar lower electrodes and the cup-shaped lower electrode. The cup-shaped lower electrode and the columnar lower electrode together form a lower electrode with a high aspect ratio, thereby improving the storage capacity of the semiconductor structure while obtaining a semiconductor structure with a stable capacitor structure.

[0089] As an example, such as Figure 2 As shown, the substrate 11 provided in step S10 may include a silicon substrate, a silicon nitride substrate, or a silicon oxynitride substrate, etc. Contact plugs 12 are formed at intervals within the substrate 11 for electrical connection with the subsequently formed stacked lower electrode. The contact plugs 12 are made of any one or a combination of two or more of the following materials: tungsten, titanium nitride, and polycrystalline silicon.

[0090] As an example, please continue to refer to Figure 2 The first stacked structure 13 formed in step S20 includes a first support layer 131, a first sacrificial layer 132, and a second support layer 133 stacked sequentially from bottom to top. Atomic layer deposition (ALD) or chemical vapor deposition (CVD) can be used to form the first support layer 131, the first sacrificial layer 132, and the second support layer 133. The first sacrificial layer 132 is made of a different material than the first support layer 131 and the second support layer 133, and the etching rate of the first sacrificial layer 132 is different from the etching rates of the first support layer 131 and the second support layer 133 in the same etching process. For example, in the same etching process, the etching rate of the first sacrificial layer 132 is much greater than the etching rates of the first support layer 131 and the second support layer 133, such that when the first sacrificial layer 132 is completely removed, the second support layer is almost completely retained. The first sacrificial layer 132 can be made of polycrystalline silicon or silicon oxide, and the first support layer 131 and the second support layer 133 can be made of silicon nitride. Please refer to [reference needed]. Figure 3 As shown, a plurality of first capacitor holes 14 can be formed in the first stacked structure 13. The first capacitor holes 14 pass through the second support layer 133, the first sacrificial layer 132 and the first support layer 131 in sequence. The first capacitor holes 14 expose the contact plugs 12 in the substrate 11.

[0091] In some embodiments, the first stacked structure further includes a support layer and a sacrificial layer (not shown in the figure) that are alternately stacked from bottom to top. The sacrificial layer is not limited to one layer and can be multiple layers. The top and bottom layers of the first stacked structure are both support layers.

[0092] In one embodiment, step S30: forming a columnar lower electrode 15 in the first capacitor hole 14 includes the following steps:

[0093] Step S31: Form a columnar lower electrode material layer 151, which covers the upper surface of the second support layer 133 and fills the first capacitor hole 14, as shown. Figure 4 As shown;

[0094] Step S32: Planarize the columnar lower electrode material layer 151 to obtain the columnar lower electrode 15 and expose the second support layer 133, as shown. Figure 5As shown.

[0095] As an example, the columnar lower electrode material layer 151 above the second support layer 133 can be removed using an etch-back or chemical mechanical polishing process until the second support layer 133 is exposed. The material of the columnar lower electrode 15 can be any one or any combination of two or more of the following materials: titanium (Ti), titanium nitride (TiN), tungsten (W), and polycrystalline silicon.

[0096] In one embodiment, such as Figure 6 As shown, a portion of the second support 133 is etched away to form the first opening 16 in step S40. The first opening 16 is located between the columnar lower electrodes 15 and exposes the first sacrificial layer 132.

[0097] To facilitate understanding of this application, two technical solutions for fabricating semiconductor structures according to embodiments of this application are described below. For the first technical solution, please refer to [link to technical solution]. Figures 7 to 15 For the second technical solution, please refer to Figures 16 to 25 Although only two technical solutions are described, this application does not limit them. Multilayer stacked semiconductor structures derived from the semiconductor structure proposed in this application are all within the protection scope of this application.

[0098] The first semiconductor structure fabrication technique is described as follows:

[0099] In one embodiment, such as Figure 7 As shown, the second stacked structure 21 formed in step S50 includes a second sacrificial layer 211, which covers the first opening 16, the columnar lower electrode 15, and the first sacrificial layer 132. Optionally, the material of the second sacrificial layer 211 may be polycrystalline silicon or silicon oxide.

[0100] In one embodiment, the first sacrificial layer 132 and the second sacrificial layer 211 may be made of the same material, for example, both of them are silicon oxide, so as to facilitate the simultaneous removal of the first sacrificial layer 132 and the second sacrificial layer 211 in a subsequent one-step process.

[0101] In one embodiment, such as Figure 8 As shown, the second capacitor hole 22 formed in step S60 penetrates the second support layer 133 and extends into the first sacrificial layer 132 to expose the top and part of the sidewall of the columnar lower electrode 15. The bottom of the second capacitor hole 22 exposes the first sacrificial layer 132. The opening size w2 of the second capacitor hole 22 is larger than the opening size w1 of the first capacitor hole 14. The opening of the over-etched second capacitor hole 22 is directly opposite the first capacitor hole 14, solving the key alignment problem between the columnar lower electrode and the cup-shaped lower electrode of the upper and lower layers, and providing a basis for forming a multilayer stacked semiconductor structure.

[0102] In one embodiment, the distance between the top of the second support layer 133 and the bottom of the second capacitor hole 22 is 5nm to 15nm; for example, the distance between the top of the second support layer 133 and the bottom of the second capacitor hole 22 is 6nm, 7nm, 9nm, 10nm, 12nm, or 14nm, etc. The distance between the sidewall of the columnar lower electrode 15 and the sidewall of the second capacitor hole 22 is 1nm to 5nm; for example, the distance between the sidewall of the columnar lower electrode 15 and the sidewall of the second capacitor hole 22 is 1nm, 2nm, 3nm, 4nm, or 5nm, etc.

[0103] In one embodiment, step S70: forming a cup-shaped lower electrode 23 at the bottom and sidewall of the second capacitor hole 22 includes the following steps:

[0104] Step S711: A cup-shaped lower electrode material layer 231 is formed on the sidewall of the second capacitor hole 22, the bottom of the second capacitor hole 22, and the upper surface of the second sacrificial layer 211, as shown below. Figure 9 As shown;

[0105] Step S712: Form a filling layer 24, the filling layer 24 filling the second capacitor hole 22, such as... Figure 10 As shown;

[0106] Step S713: Remove the cup-shaped lower electrode material layer 231 located on the upper surface of the second sacrificial layer 211 to obtain the cup-shaped lower electrode 23, as shown. Figure 11 As shown;

[0107] Step S714: Remove the filler layer 24, as follows Figure 12 As shown;

[0108] Step S715: Sequentially remove the second sacrificial layer 211 and the first sacrificial layer 132, as follows: Figure 13 As shown.

[0109] In one embodiment, the width of the cup-shaped lower electrode 23 is greater than the width of the columnar lower electrode 15, so that the cup-shaped lower electrode 23 is stably present on the columnar lower electrode 15. The material of the cup-shaped lower electrode 23 may include, but is not limited to, any one or any combination of two or more materials selected from titanium (Ti), titanium nitride (TiN), tungsten (W), and polycrystalline silicon. The material of the cup-shaped lower electrode 23 may be the same as or different from that of the columnar lower electrode 15. The cup-shaped lower electrode 23 at least covers a portion of the side surface of the columnar lower electrode. For example, the cup-shaped lower electrode 23 may cover the outer periphery and top of the upper end of the columnar lower electrode 15. In other examples, the cup-shaped lower electrode 23 may only cover a portion of the sidewall of the outer periphery of the upper end of the columnar lower electrode 15.

[0110] In one embodiment, the filling layer 24 may include, but is not limited to, any one or a combination of a photoresist layer and a carbon-containing material layer. The filling layer 24 at least partially fills the upper part of the opening of the second capacitor hole 22, that is, the filling layer 24 fills the upper part of the opening of the second capacitor hole 22. There may be gaps in the middle or bottom of the second capacitor hole to prevent the cup-shaped lower electrode material layer 231 etched on the upper surface of the second sacrificial layer 211 from falling into the second capacitor hole 22, thereby preventing particle defects and affecting the performance of the semiconductor structure.

[0111] In one embodiment, a wet etching process can be used to remove the first sacrificial layer 132 and the second sacrificial layer 211, with the etching rate of the first sacrificial layer 132 being greater than that of the second sacrificial layer 211, to improve the removal effect and shorten the etching time. In other examples, the removal of the second sacrificial layer 211 and the first sacrificial layer 132 in step S715 can also be performed before the removal of the filler layer 24 in step S714, and this embodiment of the application does not limit this.

[0112] In one embodiment, step S70: forming a cup-shaped lower electrode 23 at the bottom and sidewall of the second capacitor hole 22 further includes the following steps:

[0113] Step S80: A dielectric layer 25 is formed on the surfaces of the columnar lower electrode 15 and the cup-shaped lower electrode 23, such as... Figure 14 As shown;

[0114] Step S90: An upper electrode 26 is formed on the surface of the dielectric layer 25, and the upper electrode 26 also fills the gap between the columnar lower electrode 15 and the cup-shaped lower electrode 23, such as... Figure 15 As shown, a two-layer capacitor stack structure is formed.

[0115] The second semiconductor structure fabrication technique is described below:

[0116] In one embodiment, such as Figure 16 As shown, the second stacked structure 21 formed in step S50 includes a second sacrificial layer 211 and a third support layer 212 stacked sequentially from bottom to top. The second sacrificial layer 211 covers the first opening 16, the columnar lower electrode 15, and the first sacrificial layer 132.

[0117] In one embodiment, such as Figure 17As shown, the formed second capacitor hole 22 sequentially penetrates the third support layer 212, the second sacrificial layer 211, and the second support layer 133, and extends into the first sacrificial layer 132 to expose the top and part of the sidewall of the columnar lower electrode 15. The opening size of the second capacitor hole 22 is larger than the opening size of the first capacitor hole 14. As an example, the distance between the top of the second support layer 133 and the bottom of the second capacitor hole 22 is 5nm to 15nm; for example, the distance between the top of the second support layer 133 and the bottom of the second capacitor hole 22 is 6nm, 7nm, 9nm, 10nm, 12nm, or 14nm, etc. The distance between the sidewall of the columnar lower electrode 15 and the sidewall of the second capacitor hole 22 is 1nm to 5nm; for example, the distance between the sidewall of the columnar lower electrode 15 and the sidewall of the second capacitor hole 22 is 1nm, 2nm, 3nm, 4nm, or 5nm, etc.

[0118] In one embodiment, step S70: forming a cup-shaped lower electrode 23 at the bottom and sidewall of the second capacitor hole 22 includes the following steps:

[0119] Step S721: A cup-shaped lower electrode material layer 231 is formed on the sidewall of the second capacitor hole 22, the bottom of the second capacitor hole 22, and the upper surface of the third support layer 212, as shown below. Figure 18 As shown;

[0120] Step S722: Form a filling layer 24, the filling layer 24 filling the second capacitor hole 22, such as... Figure 19 As shown;

[0121] Step S723: Remove the cup-shaped lower electrode material layer 231 located on the upper surface of the third support layer 212 to obtain the cup-shaped lower electrode 23, as shown. Figure 20 As shown;

[0122] Step S724: Remove the filler layer 24, as follows Figure 21 As shown;

[0123] Step S725: Form a second opening 2121 on the third support layer 212, as follows Figure 22 As shown;

[0124] Step S726: Remove the second sacrificial layer 211 and the first sacrificial layer 132 using the second opening 2121 and the first opening 16 respectively, such as Figure 23 As shown.

[0125] In one embodiment, the projections of the second opening 2121 and the first opening 16 onto the substrate 11 at least partially overlap. For example, a second opening 2121 is also formed between two cup-shaped lower electrodes 23 that are respectively connected to the two columnar lower electrodes 15 adjacent to the first opening 16.

[0126] The cup-shaped lower electrode 23 at least covers a portion of the side surface of the columnar lower electrode 15. For example, the cup-shaped lower electrode 23 may cover the outer periphery and top of the upper end of the columnar lower electrode 15. In other examples, the cup-shaped lower electrode 23 may only cover a portion of the sidewall of the outer periphery of the upper end of the columnar lower electrode 15.

[0127] As an example, the bottom surface of the cup-shaped lower electrode 23 located on the side wall portion of the columnar lower electrode 15 is lower than the bottom surface of the second support layer 133 to increase the support effect.

[0128] As an example, a wet etching process can be used to remove the first sacrificial layer 132 and the second sacrificial layer 211, wherein the etching rate of the first sacrificial layer 132 is different from that of the second sacrificial layer 211. For example, the etching rate of the first sacrificial layer 132 is greater than that of the second sacrificial layer 211. The material of the second sacrificial layer 211 may include, but is not limited to, polysilicon or silicon oxide. In other examples, the removal of the second sacrificial layer 211 and the first sacrificial layer 132 in step S725 may also be performed before the removal of the fill layer 24 in step S724, and this application does not limit this.

[0129] In one embodiment, such as Figure 24 and Figure 25 As shown in Figure S70: The cup-shaped lower electrode 23 formed at the bottom and sidewall of the second capacitor hole 22 also includes the dielectric layer 25 and the upper electrode 26 formed in steps S80 and S90 respectively.

[0130] As an example, the material of dielectric layer 25 can be selected as a high-k dielectric material to increase the capacitance per unit area of ​​the capacitor, including ZrO. x HfO x ZrTiO x RuO x SbO x AlO x The material of the upper electrode 26 may be one of tungsten, titanium, nickel, aluminum, platinum, titanium nitride, N-type polycrystalline silicon, P-type polycrystalline silicon, or a stack formed of two or more of the materials in the group consisting of the above materials.

[0131] In one embodiment of this application, the steps of forming the columnar lower electrode 15 and the cup-shaped lower electrode 23 described above are repeated at least once to form a multilayered, stably stacked columnar lower electrode 15 and cup-shaped lower electrode 23 on the substrate 11, such as... Figure 26 As shown, the adjacent columnar lower electrodes and cup-shaped lower electrodes have good contact, forming a capacitor stack structure with a stable structure and high capacitance storage capacity.

[0132] In one embodiment of this application, a semiconductor structure is also provided, comprising: a substrate 11; a plurality of columnar lower electrodes 15 and cup-shaped lower electrodes 23 disposed at intervals on the substrate 11, wherein the cup-shaped lower electrodes 23 are located above the columnar lower electrodes 15 and are connected to the columnar lower electrodes 15 in a one-to-one correspondence; a first support layer 131 and a second support layer 132 are respectively located between the bottom and the top of the columnar lower electrodes 15; wherein the bottom of the cup-shaped lower electrodes 23 at least covers a portion of the side surface of the columnar lower electrodes 15.

[0133] In one embodiment, the width of the cup-shaped lower electrode 23 is greater than the width of the columnar lower electrode 15; the bottom of the cup-shaped lower electrode 23 covers the top of the columnar lower electrode 15 and part of the sidewall of the columnar lower electrode 15.

[0134] In one embodiment, the semiconductor structure further includes a third support layer 212 located between the tops of the cup-shaped lower electrodes 23.

[0135] In one embodiment, the bottom surface of the cup-shaped lower electrode 23 located on the sidewall portion of the columnar lower electrode 15 is lower than the bottom surface of the second support layer 132.

[0136] In one embodiment, the semiconductor structure further includes: a dielectric layer 25 located on the surfaces of the columnar lower electrode 15 and the cup-shaped lower electrode 23; and an upper electrode 26 located on the surface of the dielectric layer 25, wherein the upper electrode 26 also fills the gap between the columnar lower electrode 15 and the cup-shaped lower electrode 23.

[0137] Please note that the above embodiments are for illustrative purposes only and do not imply any limitation on this application.

[0138] It should be understood that, unless otherwise expressly stated herein, there is no strict order in which the steps are performed, and these steps may be performed in other orders. Moreover, at least some of the steps may include multiple sub-steps or multiple stages, which are not necessarily completed at the same time, but may be performed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0139] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0140] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A method of fabricating a semiconductor structure, characterized by, The method comprises: providing a substrate; forming a first stack structure with a plurality of first capacitor holes on the substrate; forming columnar lower electrodes in the first capacitor holes; forming first openings on top of the first stack structure between the columnar lower electrodes; forming a second stack structure on the first openings, the first stack structure and the columnar lower electrodes; forming second capacitor holes in the second stack structure and part of the top of the first stack structure, the second capacitor holes exposing the top and part of the sidewall of the columnar lower electrodes; forming cup-shaped lower electrodes on the bottom and sidewall of the second capacitor holes.

2. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The first stack structure comprises a first support layer, a first sacrificial layer and a second support layer stacked in sequence. The first openings are located between the columnar lower electrodes and formed in the second support layer.

3. The method of claim 2, wherein the semiconductor structure is prepared by a method comprising: The opening size of the second capacitor holes is larger than that of the first capacitor holes; the openings of the second capacitor holes are directly opposite the first capacitor holes.

4. The method of claim 3, wherein the semiconductor structure is prepared by a method comprising: The step of forming cup-shaped lower electrodes on the bottom and sidewall of the second capacitor holes comprises: forming a cup-shaped lower electrode material layer on the sidewall of the second capacitor holes, the bottom of the second capacitor holes and the upper surface of the second stack structure; forming a filling layer filling the second capacitor holes; removing the cup-shaped lower electrode material layer on the upper surface of the second stack structure; removing the filling layer.

5. The method of claim 4, wherein the semiconductor structure is prepared by a method comprising: The second stack structure comprises a second sacrificial layer and a third support layer.

6. The method of claim 5, wherein the semiconductor structure is prepared by a method comprising: Further comprising: forming second openings on the third support layer; removing the second sacrificial layer and the first sacrificial layer using the second openings and the first openings respectively.

7. The method of claim 6, wherein the semiconductor structure is prepared by a method comprising: Further comprising: forming a dielectric layer on the surface of the columnar lower electrodes and the cup-shaped lower electrodes; forming an upper electrode on the surface of the dielectric layer, and the upper electrode also fills the gap between the columnar lower electrodes and the cup-shaped lower electrodes.

8. The method of claim 4, wherein the semiconductor structure is prepared by a method comprising: The filling layer comprises photoresist, and the filling layer at least fills the upper part of the opening of the second capacitor holes.

9. The method of claim 2, wherein the semiconductor structure is prepared by a method comprising: The bottom of the second capacitor hole exposes or is located in the first sacrificial layer.

10. The method of claim 6, wherein the semiconductor structure is prepared by a method comprising: The etching rate of the first sacrificial layer is greater than that of the second sacrificial layer.

11. The method of claim 1, wherein: the steps of forming columnar lower electrodes and forming cup-shaped lower electrodes are repeated at least once to form a plurality of stacked columnar lower electrodes and cup-shaped lower electrodes on the substrate.

12. A semiconductor structure, characterized by The method comprises: a substrate; a plurality of columnar lower electrodes and cup-shaped lower electrodes arranged at intervals on the substrate, the cup-shaped lower electrodes being located above the columnar lower electrodes and corresponding to the columnar lower electrodes; a first support layer and a second support layer are located between the bottom and top of the columnar lower electrodes respectively; wherein the bottom of the cup-shaped lower electrode covers the top of the columnar lower electrode and part of the sidewall of the columnar lower electrode.

13. The semiconductor structure of claim 12, wherein, The width of the cup-shaped lower electrode is greater than the width of the columnar lower electrode.

14. The semiconductor structure of claim 13, wherein, Further comprising a third support layer located between the top of the cup-shaped lower electrode.

15. The semiconductor structure of claim 12, wherein, The bottom surface of the cup-shaped lower electrode located on part of the sidewall of the columnar lower electrode is lower than the bottom surface of the second support layer.

16. The semiconductor structure of any one of claims 12 to 15, wherein, Further comprising: a dielectric layer on the surface of the columnar lower electrode and the cup-shaped lower electrode; and an upper electrode on the surface of the dielectric layer, and the upper electrode also fills the gap between the columnar lower electrode and the cup-shaped lower electrode.

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