FET array gas sensor and processing method thereof

Abstract

The present invention relates to the technical field of gas sensors, and discloses a FET array gas sensor and a processing method thereof. The FET array gas sensor comprises: a substrate provided with a heat-insulating chamber; an insulating layer located at one end of the heat-insulating chamber; a silicon island located on a first side of the insulating layer; a FET heating array comprising a plurality of FET heating units, each of which comprises a sensing electrode group and a plurality of doping electrodes, the doping electrodes being divided into a source electrode and a drain electrode; and a plurality of gas-sensitive layers, each of which is covered on a sensing electrode group. The FET array gas sensor disclosed in the present invention can uniformly heat at least two gas-sensitive layers to different temperatures under the same current, thereby increasing the accuracy of sensitive gas concentration detection, enabling identification of multiple gases, improving the application space of the FET array gas sensor, reducing the probability of cracks in the gas-sensitive layer, and facilitating mass production of the FET array gas sensor.

Description

Technical Field

[0001] The present invention relates to the technical field of gas sensors, and in particular to a FET array gas sensor and a processing method thereof. Background Art

[0002] Existing array gas sensors require complex conditioning circuits to achieve different temperatures in the gas-sensing layer under the same heating current. Because different sensitive gases have varying temperature requirements, the concentrations of sensitive gases detected by existing array gas sensors differ significantly from the actual values. Furthermore, existing array gas sensors utilize heating electrodes, utilizing their resistance, for heating. This results in uneven heating and the tendency for membrane cracks, resulting in poor performance. Summary of the Invention

[0003] Based on the above, the purpose of the present invention is to provide a FET array gas sensor and a processing method thereof, wherein a FET array gas sensor can uniformly heat different gas-sensitive layers to different temperatures, thereby facilitating heating the temperature of the gas-sensitive layer to an optimal temperature range, thereby reducing the concentration detection deviation of the sensitive gas. Compared with existing array gas sensors, the probability of cracks in the FET array gas sensor is reduced, thereby extending the service life of the FET array gas sensor.

[0004] To achieve the above object, the present invention adopts the following technical solutions:

[0005] A FET array gas sensor comprises: a substrate having an insulating chamber provided thereon; an insulating layer located at one end of the insulating chamber and fixed to the substrate; a silicon island located on a first side of the insulating layer and within the insulating chamber; a FET heating array comprising a plurality of FET heating units, each of the FET heating units comprising a sensing electrode group and a plurality of doped electrodes, the doped electrodes being divided into a source electrode and a drain electrode, the source electrode and the drain electrode being spaced apart and arranged within the silicon island and contacting the first side surface, the sensing electrode group being disposed on or within the insulating layer, the second side surface being disposed opposite the first side surface, the source electrode and the drain electrode being capable of generating heat when conductive; and a plurality of gas-sensitive layers, each of the gas-sensitive layers being overlaid on one of the sensing electrode groups or on the insulating layer facing the sensing electrode group, wherein at least two of the FET heating units, when supplied with the same current, are capable of heating the corresponding gas-sensitive layers to different temperatures within the same time period.

[0006] As a preferred solution of a FET array gas sensor, the cross-sectional area of ​​the doped electrode gradually decreases along the direction from the edge to the center of each FET heating unit.

[0007] As a preferred solution of a FET array gas sensor, the doped pole is arranged in a polygonal or ring shape along the circumference of the silicon island.

[0008] As a preferred solution of a FET array gas sensor, the depth of the doped pole of each FET heating unit is the same, and the width of the doped pole gradually decreases from the edge to the center of each FET heating unit.

[0009] As a preferred solution of a FET array gas sensor, the sensing electrode group includes a positive electrode and a negative electrode, and the positive electrode and the negative electrode are formed on the insulating layer with a gap therebetween.

[0010] As a preferred solution of a FET array gas sensor, the positive electrode and the negative electrode are both polysilicon electrodes, and the positive electrode and the negative electrode are both arranged in a polygonal or ring shape along the circumference of the insulating layer.

[0011] A method for processing a FET array gas sensor applicable to any of the above solutions, comprising:

[0012] providing a substrate, and implanting ions into a local region of the substrate to form a silicon island;

[0013] forming an insulating layer and the source, the drain, and the sensing electrode group of each FET heating unit, wherein the source and the drain are spaced apart and arranged in the silicon island, and the sensing electrode group is arranged on a side of the insulating layer away from the silicon island or in the insulating layer;

[0014] forming a gas-sensitive layer comprising a noble metal for detecting a content of a sensitive gas on the sensing electrode group or on the insulating layer facing the sensing electrode group;

[0015] Processing a heat-insulating cavity at one end of the substrate facing away from the insulating layer to form a semi-finished product;

[0016] The semi-finished product is annealed and cooled to form a FET gas sensor.

[0017] As a preferred solution of a method for processing a FET array gas sensor, the sensing electrode group includes a positive electrode and a negative electrode, and both the positive electrode and the negative electrode are polysilicon electrodes. The polysilicon electrodes are formed by:

[0018] chemically vapor depositing polysilicon on the insulating layer to form a polysilicon layer;

[0019] coating a first barrier layer on the polysilicon layer;

[0020] patterning the first barrier layer to form a first etching opening;

[0021] Etching the polysilicon layer facing the first etching opening to form the positive electrode and the negative electrode;

[0022] The patterned first barrier layer is removed.

[0023] As a preferred solution of a method for processing a FET array gas sensor, after processing the sensing electrode group and before forming the gas sensing layer, the method further includes:

[0024] coating a second barrier layer on the sensing electrode group and the insulating layer;

[0025] patterning the second barrier layer to form a second etching opening;

[0026] Etching the insulating layer and the silicon island facing the second etching opening so that the doped electrodes of the plurality of FET heating units are isolated from each other;

[0027] The patterned second barrier layer is removed.

[0028] As a preferred solution of a method for processing a FET array gas sensor, processing the thermal insulation chamber includes:

[0029] Applying glue on the gas-sensitive layer to form a protective layer;

[0030] chemically depositing an insulating material on the substrate to form a hard mask;

[0031] coating a third barrier layer on the hard mask;

[0032] Patterning the third barrier layer to form a third etching opening;

[0033] Etching the hard mask facing the third etching opening to form a thermal insulation hole;

[0034] Deep silicon etching the substrate facing the thermal insulation hole to form the thermal insulation chamber;

[0035] The patterned third barrier layer and the hard mask are removed, and the protection layer is removed.

[0036] The beneficial effects of the present invention are as follows: the FET array gas sensor disclosed in the present invention can generate different amounts of heat within the same period of time when the same current is passed through at least two FET heating units of the FET heating array, and each FET heating unit corresponds to a gas-sensitive layer, so that at least two gas-sensitive layers can reach different temperatures, which is beneficial for heating the temperature of the gas-sensitive layer to the optimal temperature range required for detecting the sensitive gas, thereby reducing the concentration detection deviation of the sensitive gas. Compared with the existing resistive heating, the FET heating array heats the gas-sensitive layer, improves the temperature uniformity of the gas-sensitive layer, reduces the probability of cracks in the FET array gas sensor, and extends the service life of the FET array gas sensor. If the gas-sensitive materials of the gas-sensitive layer are different, the FET array gas sensor can also realize the identification of multiple gases, thereby improving the application space of the FET array gas sensor.

[0037] The processing method of the FET array gas sensor disclosed in the present invention is conducive to the mass production of the FET array gas sensor. The processed FET array gas sensor can uniformly heat at least two gas-sensitive layers to different temperatures under the same current within the same time, thereby increasing the accuracy of sensitive gas concentration detection, improving the performance of the FET array gas sensor, reducing the probability of cracks in the gas-sensitive layer, and extending the service life of the FET array gas sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in describing the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the contents of the embodiments of the present invention and these drawings without any creative work.

[0039] Figure 1 is a cross-sectional view of a FET array gas sensor provided by a specific embodiment of the present invention;

[0040] Figure 2 1. It is a top view of a doped electrode of a FET heating unit of a FET array gas sensor provided by a specific embodiment of the present invention;

[0041] Figure 3 1 is a top view of a doped electrode of another FET heating unit of a FET array gas sensor provided by a specific embodiment of the present invention;

[0042] Figure 4 is a cross-sectional view of a FET array gas sensor according to a first alternative embodiment of the present invention;

[0043] Figure 5is a top view of the source electrode of the FET array gas sensor according to another embodiment of the present invention;

[0044] Figure 6 is a cross-sectional view of a FET array gas sensor according to a second alternative embodiment of the present invention;

[0045] Figure 7 This is a flow chart of a method for processing a FET array gas sensor provided by a specific embodiment of the present invention;

[0046] Figures 8 to 24 This is a process diagram of a method for manufacturing a FET array gas sensor according to a specific embodiment of the present invention;

[0047] Figure 25 and Figure 26 It is a partial process diagram of a method for manufacturing a FET array gas sensor provided by a third other embodiment of the present invention.

[0048] In the picture:

[0049] 1. Substrate; 10. Thermal insulation chamber; 11. Silicon island;

[0050] 2. Insulation layer; 201. First sub-insulation layer; 202. Second sub-insulation layer;

[0051] 3. FET heating unit; 30. Polysilicon layer; 31. Source; 32. Drain; 33. Sensing electrode group; 331. Positive electrode; 332. Negative electrode;

[0052] 4. Gas sensitive layer;

[0053] 100, first barrier layer; 1001, first etching opening; 200, second barrier layer; 2001, second etching opening; 300, third barrier layer; 3001, third etching opening; 400, first photoresist layer; 4001, first opening area; 500, hard mask; 5001, thermal insulation hole; 600, second photoresist layer; 6001, second opening area; 700, protective layer; 800, third photoresist layer; 8001, third opening area. DETAILED DESCRIPTION

[0054] To make the technical problems solved, the technical solutions adopted, and the technical effects achieved by the present invention more clearly understood, the technical solutions of the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. It is apparent that the described embodiments are only some of the embodiments of the present invention, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0055] In the description of the present invention, it should be noted that the terms "center," "up," "down," "left," "right," "vertical," "horizontal," "inside," and "outside" and the like, indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of the present invention and simplify the description. They are not intended to indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The terms "first position" and "second position" refer to two different positions.

[0056] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they may refer to fixed or detachable connections; mechanical or electrical connections; direct or indirect connections through an intermediary; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention.

[0057] This embodiment provides a FET array gas sensor, such as Figure 1 As shown, it includes a substrate 1, an insulating layer 2, a silicon island 11, a FET heating array and two gas-sensitive layers 4. An insulating chamber 10 is provided on the substrate 1. The insulating layer 2 is located at one end of the insulating chamber 10 and is fixed on the substrate 1. The silicon island 11 is located on a first side of the insulating layer 2 and is located in the insulating chamber 10. The FET heating array includes two FET heating units 3. Each FET heating unit 3 includes a sensing electrode group 33 and a plurality of doped electrodes. The doped electrodes are divided into a source 31 and a drain 32. The source 31 and the drain 32 are arranged at intervals in the silicon island 11 and contact the first side. The sensing electrode group 33 is arranged on the second side of the insulating layer 2 and is located between the source 31 and the drain 32. The second side is arranged opposite to the first side. The source 31 and the drain 32 can generate heat when they are turned on. Each gas-sensitive layer 4 is covered on the sensing electrode group 33 of a FET heating unit 3. When the same current is passed through the two FET heating units 3, the corresponding gas-sensitive layers 4 can be heated to different temperatures within the same time.

[0058] It should be noted that the total resistance of the two FET heating units 3 is different. When the same voltage is applied to each FET heating unit 3 or the same current is passed through, different amounts of heat are generated within the same time period, resulting in differences in the temperatures of the two gas-sensitive layers 4.

[0059] In other embodiments of the present invention, the number of FET heating units 3 included in the FET heating array is not limited to two in this embodiment, but can also be three, four or more than four. These FET heating units 3 can heat the gas-sensitive layer 4 to different temperatures, that is, within the same time, all gas-sensitive layers 4 can be uniformly heated to different temperatures under the same current; or, two or at least two FET heating units 3 can heat the gas-sensitive layer 4 to the same temperature, but there must be at least two FET heating units 3 that can heat the gas-sensitive layer 4 to different temperatures, which improves the application space of the FET array gas sensor and is specifically set according to actual needs.

[0060] Specifically, the gas-sensing layer 4 of this embodiment comprises the same gas-sensing material, which is tin dioxide, tungsten trioxide, or zinc oxide. The noble metal contained in the gas-sensing layer 4 may be platinum, gold, palladium, rhodium, or iridium, which has a catalytic effect. The noble metal can reduce the semiconductor barrier of tin dioxide, tungsten trioxide, or zinc oxide, thereby enhancing the selectivity of the FET array gas sensor. In other embodiments, the gas-sensing materials of different gas-sensing layers 4 of the same FET array gas sensor can be the same to detect the same sensitive gas, or different to detect different sensitive gases. The selection of the gas-sensing material is based on actual needs and is not specifically limited in this embodiment.

[0061] The FET array gas sensor provided in this embodiment can generate different amounts of heat within the same period of time when the same current is passed through the two FET heating units 3 of the FET heating array, and each FET heating unit 3 corresponds to a gas-sensitive layer 4, so that the two gas-sensitive layers 4 can reach different temperatures, which is beneficial for heating the temperature of the gas-sensitive layer 4 to the optimal temperature range required for detecting the sensitive gas, thereby reducing the concentration detection deviation of the sensitive gas. Compared with the existing resistive heating, the FET heating array heats the gas-sensitive layer 4, improves the temperature uniformity of the gas-sensitive layer 4, reduces the probability of cracks in the FET array gas sensor, and extends the service life of the FET array gas sensor.

[0062] like Figure 1 As shown, the heat-insulating chamber 10 of this embodiment is formed by dry etching. Dry etching has the advantages of both anisotropy and good selectivity. Compared with wet etching, it has low cost but slow etching rate. Of course, in other embodiments of the present invention, a wet self-stop etching process can also be used to form the heat-insulating chamber 10, such as Figure 4 The processing technology should be selected according to actual needs.

[0063] like Figure 2 and Figure 3As shown, the cross-sectional area of ​​the doped electrode gradually decreases along the direction from the edge to the center of each FET heating unit 3. The depth of the doped electrode of each FET heating unit 3 is the same, and the width of the doped electrode gradually decreases along the direction from the edge to the center of each FET heating unit 3. The depth direction of the doped electrode is defined as the thickness direction of the silicon island 11, and the width direction of the doped electrode is defined as the radial direction of the FET heating unit 3.

[0064] In conventional FET heating units 3, all doped electrodes have the same width, resulting in a higher temperature in the center of the gas-sensing layer 4 than in the outer region. By configuring the doped electrode widths according to the aforementioned structure for the same FET heating unit 3, this embodiment can increase the temperature of the outer region of the gas-sensing layer 4 and improve the uniformity of the temperature distribution in the gas-sensing layer 4, thereby enabling the gas-sensing layer 4 to better detect the concentration of the sensitive gas.

[0065] Specifically, one FET heating unit 3 of the present embodiment includes two sources 31 and two drains 32, both of which are annular and arranged on the silicon island 11 in sequence. Along the radial direction of the source 31 itself from the outside to the inside, the widths of the source 31, the drain 32, the source 31 and the drain 32 gradually decrease. Another FET heating unit 3 includes one source 31 and one drain 32, both of which are arranged on the silicon island 11 in sequence. The width of the source 31 is greater than the width of the drain 32. The source 31 and the drain 32 of the present embodiment are both in the shape of circular rings. This arrangement enables the FET heating unit 3 to heat the gas-sensitive layer 4 more evenly, thereby making the heating of each gas-sensitive layer 4 more evenly distributed. In other embodiments, the shape of the source 31 and the drain 32 can also be annular polygons. For example, the shape of the source 31 is an annular regular octagon, such as Figure 5 Please set it according to actual needs.

[0066] In other embodiments, when the number of source electrodes 31 and drain electrodes 32 included in the FET heating unit 3 is one, the distribution method is not limited to the limitation of this embodiment. The source electrodes 31 can also be distributed along the edge of the gas-sensitive layer 4, and the drain electrodes 32 can be spaced apart from the source electrodes 31, or the number of source electrodes 31 and drain electrodes 32 included in the FET heating unit 3 can be more than two, and the source electrodes 31 and drain electrodes 32 can be spaced apart in sequence, depending on actual needs.

[0067] like Figure 1As shown, the sensing electrode group 33 of this embodiment includes a positive electrode 331 and a negative electrode 332, which are spaced apart and formed on the insulating layer 2. The positive electrode 331 and the negative electrode 332 of the two FET heating units 3 of this embodiment are both polysilicon electrodes. The positive electrode 331 and the negative electrode 332 of the sensing electrode group 33 of one FET heating unit 3 are arranged in a straight line, while the positive electrode 331 and the negative electrode 332 of the sensing electrode group 33 of the other FET heating unit 3 are arranged in a circular ring along the circumference of the insulating layer 2. In other embodiments, the shapes of the positive electrode 331 and the negative electrode 332 are not limited to those of this embodiment and can also be circular or polygonal, depending on actual needs.

[0068] like Figure 6 As shown, the sensing electrode group 33 is disposed in the insulating layer 2 , and the gas-sensitive layer 4 covers the insulating layer 2 facing the sensing electrode group 33 , so that the sensing electrode group 33 can sense the change in the resistivity of the gas-sensitive layer 4 .

[0069] This embodiment also provides a processing method applicable to the above-mentioned FET array gas sensor, such as Figure 7 Shown, including:

[0070] S1. Provide a substrate 1, and implant ions into a local area of ​​the substrate 1 to form a silicon island 11.

[0071] Specifically, S1 includes the following steps:

[0072] S11, coating a first photoresist layer 400 on the upper surface of the substrate 1;

[0073] S12, patterning the first photoresist layer 400 to form a first opening area 4001;

[0074] S13, injecting concentrated phosphorus ions into the substrate 1 through the first opening area 4001 to form a square silicon island 11, as shown in FIG. Figure 8 As shown;

[0075] S14, remove the patterned first photoresist layer 400, as shown in FIG. Figure 9 shown.

[0076] Specifically, the substrate 1 of this embodiment is P-type silicon, and concentrated phosphorus ions are infiltrated into the P-type silicon to form an N-well silicon island, which is square in shape.

[0077] S2 , implanting ions into the silicon island 11 to form the source 31 and the drain 32 of each FET heating unit 3 , wherein the source 31 and the drain 32 are arranged in the silicon island 11 at intervals.

[0078] Specifically, S2 includes the following steps:

[0079] S21, coating a second photoresist layer 600 on the upper surface of the substrate 1 and the upper surface of the silicon island 11;

[0080] S22, patterning the second photoresist layer 600 to form a second opening area 6001, such as Figure 10 As shown;

[0081] S23, injecting concentrated boron ions into the silicon island 11 through the second opening area 6001 to form a source 31 and a drain 32, as shown in FIG. Figure 11 As shown;

[0082] S24, remove the patterned second photoresist layer 600, as shown in FIG. Figure 12 shown.

[0083] Specifically, the processed source electrode 31 and drain electrode 32 are both in the shape of a ring, and the number of source electrodes 31 and drain electrodes 32 is two, and the source electrodes 31 and drain electrodes 32 are spaced apart in sequence. In other embodiments, the source electrode 31 and drain electrode 32 may also be in the shape of a ring-shaped polygon, and the number of source electrodes 31 and drain electrodes 32 may be one or more than two, or the number of source electrodes 31 may be one more than the number of drain electrodes 32, depending on actual needs.

[0084] S3, depositing insulating material on the substrate 1 to form an insulating layer 2, such as Figure 13 shown.

[0085] Specifically, the insulating layer 2 of this embodiment is a silicon oxide layer. In other embodiments, the insulating layer 2 can also be a single-layer structure formed of an insulating material such as silicon nitride or aluminum oxide, or a structure of at least two layers formed of an insulating material such as silicon oxide, silicon nitride or aluminum oxide, which is selected according to actual needs.

[0086] S4 , forming a sensing electrode group 33 of each FET heating unit 3 on the insulating layer 2 . The sensing electrode group 33 is disposed on the second side surface of the insulating layer 2 and between the source electrode 31 and the drain electrode 32 .

[0087] In this embodiment, the induction electrode group 33 of each FET heating unit 3 includes a positive electrode 331 and a negative electrode 332. The positive electrode 331 and the negative electrode 332 are both polysilicon electrodes. When forming the polysilicon electrodes, S4 includes:

[0088] S41, chemical vapor deposition of polysilicon on the insulating layer 2 to form a polysilicon layer 30, such as Figure 14 As shown;

[0089] S42, coating a first barrier layer 100 on the polysilicon layer 30;

[0090] S43, patterning the first barrier layer 100 to form a first etching opening 1001, such as Figure 15 As shown;

[0091] S44, etching the polysilicon layer 30 facing the first etching opening 1001 to form a positive electrode 331 and a negative electrode 332, as shown in FIG. Figure 16 As shown;

[0092] S45, removing the patterned first barrier layer 100, as shown in FIG. Figure 17 shown.

[0093] The first barrier layer 100 is a photoresist layer, wherein the positive electrode 331 and the negative electrode 332 of one FET heating unit 3 are both in a straight line shape, and the positive electrode 331 and the negative electrode 332 of the other FET heating unit 3 are both in a circular ring shape.

[0094] After step S45 and before step S5, the method further includes:

[0095] S46, coating a second barrier layer 200 on the sensing electrode group 33 and the insulating layer 2, as shown in FIG. Figure 18 As shown;

[0096] S47, patterning the second barrier layer 200 to form a second etching opening 2001;

[0097] S48, etching the insulating layer 2 and the silicon island 11 facing the second etching opening 2001, so that the doping electrodes of the two FET heating units 3 are isolated from each other, as shown in FIG. Figure 19 As shown;

[0098] S49 , removing the patterned second barrier layer 200 .

[0099] The above-mentioned second barrier layer 200 is a photoresist layer, and the two FET heating units 3 are isolated from each other, so that each FET heating unit 3 can independently heat the corresponding gas-sensitive layer 4, avoiding the phenomenon that the two FET heating units 3 heat each other's gas-sensitive layer 4 due to electrical connection, and ensuring that each FET heating unit 3 can only heat the gas-sensitive layer 4 corresponding to it.

[0100] S5. A gas-sensitive layer 4 including a noble metal for detecting the content of sensitive gas is formed on the sensing electrode group 33. Specifically, in this embodiment, the gas-sensitive material is drop-coated on the sensing electrode group 33 by screen printing. The formed gas-sensitive layer 4 is in the shape of a water droplet, as shown in FIG. Figure 20 shown.

[0101] In other embodiments of the present invention, the gas-sensitive material may be formed on the sensing electrode group 33 by evaporation to form the gas-sensitive layer 4. In this case, S5 includes the following steps:

[0102] S51, coating a third photoresist layer 800 on the insulating layer 2 and the sensing electrode group 33;

[0103] S52, patterning the third photoresist layer 800 to form a third opening area 8001, such as Figure 25 As shown;

[0104] S53 , forming a gas-sensitive material on the sensing electrode group 33 by using an evaporation method in the third opening area 8001 to form a gas-sensitive layer 4 ;

[0105] S54, remove the patterned third photoresist layer 800, as shown in FIG. Figure 26 shown.

[0106] In other embodiments, the gas-sensitive layer 4 may be formed by inkjet printing.

[0107] Specifically, the gas-sensing layer 4 of this embodiment comprises the same gas-sensing material, namely, tin dioxide, tungsten trioxide, or zinc oxide. The noble metal contained in the gas-sensing layer 4 may be catalytic platinum, gold, palladium, rhodium, or iridium. The noble metal can lower the semiconductor barrier of tin dioxide, tungsten trioxide, or zinc oxide, thereby enhancing the selectivity of the FET array gas sensor. In other embodiments, the gas-sensing materials of different gas-sensing layers 4 of the same FET array gas sensor may be the same or different, depending on actual needs and not specifically limited in this embodiment.

[0108] S6. A heat-insulating chamber 10 is processed at one end of the substrate 1 away from the insulating layer 2 to form a semi-finished product.

[0109] Specifically, when processing the heat-insulating chamber 10, S6 includes:

[0110] S61, apply glue on the gas-sensitive layer 4 to form a protective layer 700, such as Figure 21 As shown;

[0111] S62, chemically depositing an insulating material on the substrate 1 to form a hard mask 500;

[0112] S63, coating a third barrier layer 300 on the hard mask 500;

[0113] S64, patterning the third barrier layer 300 to form a third etching opening 3001;

[0114] S65, etching the hard mask 500 facing the third etching opening 3001 to form a thermal insulation hole 5001, such as Figure 22 As shown;

[0115] S66, deep silicon etching the substrate 1 facing the thermal insulation hole 5001 to form a thermal insulation chamber 10, such as Figure 23 As shown;

[0116] S67, remove the patterned third barrier layer 300 and the hard mask 500, and remove the protective layer 700, as shown in FIG. Figure 24 shown.

[0117] The third barrier layer 300 of this embodiment is a photoresist layer, and the protective layer 700 can protect the gas-sensitive layer 4, thereby preventing damage to the gas-sensitive layer 4 during processing. The dry etching process in step S66 has the advantages of both anisotropy and good selectivity. Compared with wet etching, it is low-cost but has a slow etching rate. Of course, in other embodiments of the present invention, a wet self-stop etching process can also be used to form the thermal insulation chamber 10. For example, a potassium hydroxide solution or a tetramethylammonium hydroxide solution is used to wet-etch the substrate 1. Since the concentration of phosphorus ions in the silicon islands 11 is higher than the concentration of boron ions in the substrate 1, the etching rate of the etching solution on the substrate 1 with a low ion concentration is much higher than the etching rate of the silicon islands 11, thereby showing a self-stop effect, a fast etching rate, simple equipment, and high mechanical sensitivity. In actual processing, the processing technology can be selected according to actual needs.

[0118] S7. Annealing and cooling the semi-finished product to form a FET gas sensor.

[0119] The semi-finished product in this step refers to a single FET array gas sensor. After annealing, both gas-sensing layers 4 of the FET array gas sensor are porous, demonstrating higher linearity and sensitivity compared to processes without annealing and cooling. The annealing temperature and duration are commonly used techniques in the art and can be adjusted by those skilled in the art based on practical needs. This embodiment does not impose specific limitations thereon.

[0120] The processing method of the FET array gas sensor provided in this embodiment is conducive to the mass production of FET array gas sensors. The processed FET array gas sensor can uniformly heat at least two gas-sensitive layers 4 to different temperatures under the same current within the same time, thereby increasing the accuracy of sensitive gas concentration detection, improving the performance of the FET array gas sensor, reducing the probability of cracks in the gas-sensitive layer 4, and extending the service life of the FET array gas sensor.

[0121] Formed as Figure 6 The source electrode 31, the drain electrode 32, the sensing electrode group 33 and the insulating layer 2 shown include:

[0122] Depositing an insulating material on the substrate 1 to form a first sub-insulating layer 201;

[0123] A sensing electrode group 33 is formed on the first sub-insulating layer 201 . The processing method of the sensing electrode group 33 is the same as that of S4 .

[0124] Part of the first sub-insulating layer 201 is etched to form a source electrode 31 and a drain electrode 32 arranged at intervals on the silicon island 11;

[0125] A second sub-insulating layer 202 is formed on the source 31 , the drain 32 , the sensing electrode group 33 and the first sub-insulating layer 201 . The first sub-insulating layer 201 and the second sub-insulating layer 202 form an insulating layer 2 .

[0126] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the concept of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A FET array gas sensor, characterized in that: include: a substrate having a thermally insulating chamber disposed thereon; an insulating layer, located at one end of the thermal insulation chamber and fixed on the substrate; a silicon island located on the first side of the insulating layer and within the thermal insulation chamber; A FET heating array, comprising a plurality of FET heating units, each of the FET heating units comprising a sensing electrode group and a plurality of doped electrodes, the doped electrodes being divided into a source electrode and a drain electrode, the source electrode and the drain electrode being spaced apart and arranged within the silicon island and contacting the first side surface, the sensing electrode group being disposed on or within the second side surface of the insulating layer, the second side surface being disposed opposite the first side surface, the source electrode and the drain electrode being capable of generating heat when conductive, the cross-sectional area of ​​the doped electrode gradually decreasing from the edge to the center of each FET heating unit, the depth of the doped electrode of each FET heating unit being the same, and the width of the doped electrode gradually decreasing from the edge to the center of each FET heating unit; There are multiple gas-sensitive layers, each of which is covered on one of the sensing electrode groups or on the insulating layer facing the sensing electrode group. When the same current is supplied to at least two of the FET heating units, the corresponding gas-sensitive layers can be heated to different temperatures within the same time period.

2. The FET array gas sensor according to claim 1, characterized in that: The doping pole is arranged in a polygonal or ring shape along the circumference of the silicon island.

3. The FET array gas sensor according to claim 1, characterized in that: The sensing electrode group includes a positive electrode and a negative electrode, and the positive electrode and the negative electrode are formed on the insulating layer with an interval therebetween.

4. The FET array gas sensor according to claim 3, characterized in that: The positive electrode and the negative electrode are both polysilicon electrodes, and are arranged in a polygonal or ring shape along the circumference of the insulating layer.

5. A processing method for the FET array gas sensor according to any one of claims 1 to 4, characterized in that: include: providing a substrate, and implanting ions into a local region of the substrate to form a silicon island; forming an insulating layer and the source, the drain, and the sensing electrode group of each FET heating unit, wherein the source and the drain are spaced apart and arranged in the silicon island, and the sensing electrode group is arranged on a side of the insulating layer away from the silicon island or in the insulating layer; forming a gas-sensitive layer comprising a noble metal for detecting a content of a sensitive gas on the sensing electrode group or on the insulating layer facing the sensing electrode group; Processing a heat-insulating cavity at one end of the substrate facing away from the insulating layer to form a semi-finished product; annealing and cooling the semi-finished product to form a FET gas sensor; The sensing electrode group includes a positive electrode and a negative electrode, and both the positive electrode and the negative electrode are polysilicon electrodes. The polysilicon electrodes are formed by: chemically vapor depositing polysilicon on the insulating layer to form a polysilicon layer; coating a first barrier layer on the polysilicon layer; patterning the first barrier layer to form a first etching opening; Etching the polysilicon layer facing the first etching opening to form the positive electrode and the negative electrode; The patterned first barrier layer is removed.

6. The method for processing a FET array gas sensor according to claim 5, wherein: After processing the sensing electrode group and before forming the gas sensitive layer, the method further includes: coating a second barrier layer on the sensing electrode group and the insulating layer; patterning the second barrier layer to form a second etching opening; Etching the insulating layer and the silicon island facing the second etching opening so that the doped electrodes of the plurality of FET heating units are isolated from each other; The patterned second barrier layer is removed.

7. The method for processing a FET array gas sensor according to claim 5, wherein: When processing the heat-insulating chamber, the process includes: Applying glue on the gas-sensitive layer to form a protective layer; chemically depositing an insulating material on the substrate to form a hard mask; coating a third barrier layer on the hard mask; Patterning the third barrier layer to form a third etching opening; Etching the hard mask facing the third etching opening to form a thermal insulation hole; Deep silicon etching the substrate facing the thermal insulation hole to form the thermal insulation chamber; The patterned third barrier layer and the hard mask are removed, and the protection layer is removed.

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