PCIE Topology and PCIE Device Simulation Methods, Apparatuses, Devices and Media

Abstract

The present application discloses a method, device, equipment and medium for PCIE topology and PCIE device simulation, which relates to the technical field of the application of PCIE technology in heterogeneous computing. Applied to an ECPU simulator, the method includes: splitting the services in the ECPU simulator to obtain a PCIE simulator service and multiple device simulator services; wherein, the device simulator services generate different PCIE devices; obtaining a PCIE device channel table for querying data communication information allocated in the hardware layer base address register space; according to the PCIE device channel table, performing data communication between the PCIE simulator service and the device simulator services to simulate the PCIE topology and the PCIE devices. Through the technical solution of the present application, decoupling of the PCIE topology and the PCIE devices can be achieved, thereby improving the robustness of the PCIE topology while increasing the flexibility of PCIE device implementation.

Description

Technical Field

[0001] The present invention relates to the technical field of the application of PCIE technology in heterogeneous computing, and particularly relates to a PCIE topology and PCIE device simulation method, device, equipment and medium. Background Art

[0002] PCI, namely Peripheral Component Interconnect, whose Chinese meaning is "Peripheral Device Interconnection", is a local parallel bus standard launched by PCISIG (PCI Special Interest Group). The PCI bus is a tree structure and is independent of the CPU (Central Processing Unit) bus, and can operate in parallel with the CPU bus. PCI devices and PCI bridge chips can be connected to the PCI bus. There is only one PCI master device allowed on the PCI bus, and the others are all PCI slave devices. Moreover, read and write operations can only be performed between the master and slave devices, and data exchange between slave devices needs to be relayed through the master device.

[0003] PCI Express is derived from the early PCI expansion and is compatible with PCI. The main difference between the two lies in the switch from parallel to serial and faster speed. PCI Express is a hierarchical protocol, consisting of a transaction layer, a data link layer and a physical layer.

[0004] In the DPU (Data Processing Unit, Processor Dispersed Processing Unit) scenario, in order to enable the DPU to simulate multiple different types of standard PCIE devices for the HOST (host), the software on the ECPU (Embedded Central Processing Unit) side needs to simulate the entire PCIE topology and different types of PCIE devices; the operating system on the HOST side enumerates the PCIE topology and PCIE devices; finally, after the operating system on the HOST side enumerates the PCIE topology and PCIE devices, it will load different types of drivers to Probe different types of PCIE devices.

[0005] As described above, the simulation of the current PCIE topology and PCIE devices is all implemented by the software on the ECPU side, such as Figure 1As shown in the figure, when the software on the ECPU side has not implemented the PCIE topology and PCIE devices, only one Upstream port is presented to the HOST side. In order for the DPU to simulate multiple different types of standard PCIE devices for the HOST, when the HW (Hard Ware) receives a TLP (Transaction Layer Packet) message, it needs to transparently transmit it to the ECPU side for parsing, so as to simulate the entire PCIE topology structure and different types of PCIE devices. In the current technical solution, the ECPU Emulator needs to implement the entire PCIE topology, PCIE bridge devices, PCIE EP (End Point) devices, and the routing of TLP messages. The entire Emulator service is too complex and lacks flexibility. If new device types need to be supported, the entire Emulator service needs to be upgraded; moreover, an exception in a certain type of device will cause the entire PCIE topology to be unavailable, affecting the normal use of other types of devices.

[0006] In summary, how to decouple the PCIE topology and PCIE devices, so as to improve the robustness of the PCIE topology while increasing the flexibility of PCIE device implementation is an issue to be solved currently. Summary of the Invention

[0007] In view of this, the purpose of the present invention is to provide a method, device, equipment and medium for simulating PCIE topology and PCIE devices, which can decouple the PCIE topology and PCIE devices, so as to improve the robustness of the PCIE topology while increasing the flexibility of PCIE device implementation. The specific solutions are as follows:

[0008] In the first aspect, the present application discloses a method for simulating PCIE topology and PCIE devices, which is applied to an ECPU emulator and includes:

[0009] Split the services in the ECPU emulator to obtain a PCIE emulator service and multiple device emulator services; wherein, the device emulator services generate different PCIE devices;

[0010] Obtain a PCIE device channel table for querying data communication information allocated by the base address register space of the hardware layer;

[0011] According to the PCIE device channel table, perform data communication between the PCIE emulator service and the device emulator services to simulate the PCIE topology and the PCIE devices.

[0012] Optionally, each device simulator service in the PCIE device channel table occupies one entry; each device simulator service in the PCIE device channel table occupies one entry; the entry includes a first tag for recording the loading status of the device simulator service, a second tag representing the space for storing the data sent by the PCIE simulator service to the device simulator service, a third tag for counting the data requests notified by the PCIE simulator service to the device simulator service, a fourth tag representing the space for storing the data sent by the device simulator service to the PCIE simulator service, and a fifth tag for counting the data requests notified by the device simulator service to the PCIE simulator service.

[0013] Optionally, according to the PCIE device channel table, performing data communication between the PCIE simulator service and the device simulator service to simulate the PCIE topology and the PCIE device includes:

[0014] When the PCIE simulator service sends a first data request to the device simulator service, route the first data request to the corresponding downstream port of the PCIE simulator service through the PCIE simulator service, fill in the second tag, increase the value corresponding to the third tag, and then wait for the device simulator service to process the first data request.

[0015] Optionally, waiting for the device simulator service to process the first data request includes:

[0016] If the device simulator service detects an increase in the value corresponding to the third tag, read the second tag, then parse and process the first data request, and update the second tag when the first data request is processed.

[0017] Optionally, according to the PCIE device channel table, performing data communication between the PCIE simulator service and the device simulator service to simulate the PCIE topology and the PCIE device includes:

[0018] When the device simulator service sends a second data request to the PCIE simulator service, fill in the fourth tag through the device simulator service, increase the value corresponding to the fifth tag, and then wait for the PCIE simulator service to process the second data request.

[0019] Optionally, waiting for the PCIE simulator service to process the second data request includes:

[0020] If the PCIE simulator service detects an increase in the value corresponding to the fifth tag, it reads the fourth tag, then parses and processes the second data request, and updates the fourth tag after the second data request is processed.

[0021] Optionally, the data communication between the PCIE simulator service and the device simulator service according to the PCIE device channel table to simulate the PCIE topology and PCIE devices includes:

[0022] Based on the polling mechanism, the PCIE simulator service and the device simulator service are data-communicated according to the PCIE device channel table to simulate the PCIE topology and PCIE devices.

[0023] In a second aspect, the present application discloses a PCIE topology and PCIE device simulation apparatus, which is applied to an ECPU simulator and includes:

[0024] A service splitting module, configured to split the services in the ECPU simulator to obtain a PCIE simulator service and multiple device simulator services; wherein, the device simulator services generate different PCIE devices;

[0025] A PCIE device channel table acquisition module, configured to acquire a PCIE device channel table for querying data communication information allocated by a hardware layer base address register space;

[0026] A PCIE topology and PCIE device simulation module, configured to perform data communication between the PCIE simulator service and the device simulator service according to the PCIE device channel table to simulate the PCIE topology and PCIE devices.

[0027] In a third aspect, the present application discloses an electronic device, which includes a processor and a memory; wherein, the memory is used to store a computer program, and the computer program is loaded and executed by the processor to implement the PCIE topology and PCIE device simulation method as described above.

[0028] In a fourth aspect, the present application discloses a computer-readable storage medium, which is used to store a computer program; wherein the computer program, when executed by a processor, implements the PCIE topology and PCIE device simulation method as described above.

[0029] The PCIE topology and PCIE device simulation method provided by this application is applied to an ECPU simulator. By splitting the services in the ECPU simulator, a PCIE simulator service and multiple device simulator services are obtained. Among them, the device simulator services generate different PCIE devices. Then, a PCIE device channel table used to query data communication information allocated in the hardware layer base address register space is obtained. Finally, according to the PCIE device channel table, data communication is performed between the PCIE simulator service and the device simulator services to simulate the PCIE topology and the PCIE devices. It can be seen that splitting the services of the ECPU simulator into a lightweight PCIE simulator service and multiple lightweight device simulator services increases the robustness of the PCIE topology and the flexibility of PCIE device implementation. By means of the hardware layer base address register, a communication channel for the PCIE simulator service and the device simulator services is provided to implement the simulation of the entire PCIE topology structure and different types of PCIE devices. For the PCIE simulator service, it is responsible for the generation and maintenance of the PCIE topology. For the device simulator services, they are responsible for the generation and maintenance of the PCIE devices, and the resources between the device simulator services are isolated from each other. The crash of one device simulator service does not affect other device simulator services and does not affect the PCIE simulator service. In this way, the decoupling of the PCIE topology and the PCIE devices is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.

[0031] Figure 1 Schematic diagram of an existing PCIE topology and PCIE device architecture disclosed in this application;

[0032] Figure 2 Flowchart of a PCIE topology and PCIE device simulation method disclosed in this application;

[0033] Figure 3 Schematic diagram of a front-end and back-end system framework disclosed in this application;

[0034] Figure 4 Schematic diagram of an architecture for decoupling the PCIE topology and PCIE devices disclosed in this application;

[0035] Figure 5 Flowchart of a specific PCIE topology and PCIE device simulation method disclosed in this application;

[0036] Figure 6 Schematic diagram of the structure of a PCIE topology and PCIE device simulation apparatus disclosed in the present application;

[0037] Figure 7 Structural diagram of an electronic device disclosed in the present application. Detailed implementation manners

[0038] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0039] Currently, the simulation of PCIE topology and PCIE devices is both implemented by the software on the ECPU side. The ECPU simulator needs to implement the entire PCIE topology, PCIE bridge devices, PCIE EP devices, and the routing of TLP messages. The entire simulator service is too complex and lacks flexibility. If new device types need to be supported, the entire simulator service needs to be upgraded; moreover, an exception in a certain type of device will cause the entire PCIE topology to be unavailable, affecting the normal use of other types of devices.

[0040] Therefore, the present application provides a PCIE topology and PCIE device simulation solution, which can decouple the PCIE topology and PCIE devices, thereby improving the robustness of the PCIE topology while increasing the flexibility of PCIE device implementation.

[0041] The embodiments of the present invention disclose a method for simulating a PCIE topology and PCIE devices. Refer to Figure 2 as shown, which is applied to an ECPU simulator. The method includes:

[0042] Step S11: Split the services in the ECPU simulator to obtain a PCIE simulator service and multiple device simulator services; wherein, the device simulator services generate different PCIE devices.

[0043] Since the service of the entire emulator is too complex and lacks flexibility when simulating the PCIE topology and PCIE devices through the ECPU emulator currently, in the embodiments of the present application, the service of the ECPU emulator is split into a lightweight PCIE emulator service (PCIE Emulator) and multiple lightweight device emulator services (Device Emulator). The PCIE emulator service is responsible for generating and maintaining the PCIE topology, and the device emulator service is responsible for generating and maintaining the PCIE devices, thereby increasing the robustness of the PCIE topology and the flexibility of PCIE device implementation.

[0044] Step S12: Obtain a PCIE device channel table for querying data communication information allocated in the base address register space of the hardware layer.

[0045] As Figure 3 shown in the schematic diagram of the framework between the front-end and back-end systems, after the HOST front-end emulates the entire PCIE topology and multiple PCIE devices on the back-end side of the ECPU, it enumerates the PCIE topology and PCIE devices, and then loads different types of drivers to Probe different types of PCIE devices. Among them, it passes through the hardware back-end FPGA (Field-Programmable Gate Array) / ASIC (Application Specific Integrated Circuit). In the embodiments of the present application, with the help of the hardware back-end, the hardware layer base address register (BAR) space is used to provide a communication channel for the PCIE emulator service and the device emulator service. That is, a PCIE device channel table for querying data communication information is allocated through the hardware layer base address register space. The information required for communication between the PCIE emulator service and the device emulator service is stored in the PCIE device channel table. According to the PCIE device channel table, the PCIE emulator service and the device emulator service can perform data communication.

[0046] Step S13: According to the PCIE device channel table, perform data communication between the PCIE emulator service and the device emulator service to simulate the PCIE topology and the PCIE devices.

[0047] As Figure 4The figure shows an architecture diagram of simulating a PCIE topology and PCIE devices after decoupling the PCIE topology and PCIE devices provided in an embodiment of the present application. It can be seen that for the PCIE simulator service, it is not only responsible for generating and maintaining the PCIE topology, but also responsible for maintaining the information of the Upstream (upstream port) and Downstream (downstream port) of PCIE; different PCIE devices generated by different device simulator services are attached under the Downstream in the PCIE simulator service, and data communication between the PCIE simulator service and the device simulator service is carried out according to the PCIE-Device Channel Table provided by the HW hardware layer, so as to realize the simulation of the PCIE topology and PCIE devices.

[0048] It can be understood that when the PCIE simulator service and the device simulator service perform data communication, after the PCIE simulator service sends a data request to the device simulator service, if the current PCIE topology is generated during the process of simulating the PCIE topology, there is normal data interaction between the HOST and the devices created by the device simulator, such as the probe process between the Host driver and the device, or data interaction between other tools and the device. Correspondingly, after the device simulator service sends a data request to the PCIE simulator service and the current PCIE device is generated during the process of simulating the PCIE device, the current PCIE device can actively send some data requests to the PCIE simulator service and then to the HOST, such as an interrupt TLP packet, to notify the HOST of the occurrence of corresponding events.

[0049] It can be understood that in order to simulate the entire PCIE topology and all PCIE devices, all information in the PCIE device channel table needs to be polled during data communication. Therefore, in the embodiment of the present application, when performing data communication, a Poller thread is provided for the PCIE simulator service to process the requests of all device simulator services; a Poller thread is provided for the device simulator service to process the requests from the PCIE simulator service, that is, according to the PCIE device channel table, the PCIE simulator service and the device simulator service are data-communicated based on the polling mechanism to simulate the PCIE topology and PCIE devices.

[0050] The PCIE topology and PCIE device simulation method provided by this application is applied to an ECPU simulator. By splitting the services in the ECPU simulator, a PCIE simulator service and multiple device simulator services are obtained. Among them, the device simulator service generates different PCIE devices. Then, a PCIE device channel table for querying data communication information allocated in the hardware layer base address register space is obtained. Finally, according to the PCIE device channel table, data communication is performed between the PCIE simulator service and the device simulator service to simulate the PCIE topology and the PCIE device. It can be seen that the services of the ECPU simulator are split into a lightweight PCIE simulator service and multiple lightweight device simulator services, thereby increasing the robustness of the PCIE topology and the flexibility of the implementation of the PCIE device. By means of the communication channel provided by the hardware layer base address register for the PCIE simulator service and the device simulator service, the simulation of the entire PCIE topology structure and different types of PCIE devices is realized. For the PCIE simulator service, it is responsible for the generation and maintenance of the PCIE topology. For the device simulator service, it is responsible for the generation and maintenance of the PCIE device, and the resources between the device simulator services are isolated from each other. The crash of one device simulator service does not affect other device simulator services and does not affect the PCIE simulator service. In this way, the decoupling of the PCIE topology and the PCIE device is achieved.

[0051] The embodiment of this application discloses a specific PCIE topology and PCIE device simulation method. Refer to Figure 5 as shown, which is applied to an ECPU simulator. The method includes:

[0052] Step S21: Split the services in the ECPU simulator to obtain a PCIE simulator service and multiple device simulator services. Among them, the device simulator service generates different PCIE devices.

[0053] Among them, for a more specific processing process of the above step S21, reference can be made to the corresponding content disclosed in the foregoing embodiments, and details are not described herein again.

[0054] Step S22: Obtain a PCIE device channel table for querying data communication information allocated in the hardware layer base address register space.

[0055] In an embodiment of the present application, each device simulator service in the PCIE device channel table occupies one table entry; the table entry includes a first tag for recording the loading status of the device simulator service, a second tag representing the space for storing data sent by the PCIE simulator service to the device simulator service, a third tag for counting data requests notified by the PCIE simulator service to the device simulator service, a fourth tag representing the space for storing data sent by the device simulator service to the PCIE simulator service, and a fifth tag for counting data requests notified by the device simulator service to the PCIE simulator service.

[0056] Exemplarily, as Figure 4 shown, the PCIE device channel table stores information required for communication between the PCIE simulator service and the device simulator service, and each device simulator service occupies one table entry; in the corresponding PCIE device channel entry, Channel_enable is the first tag. After the device simulator service is loaded, Channel_enable needs to be set to indicate that Channel is valid; To_device_key is the second tag, which is used to store data sent by the PCIE simulator service to the device simulator service; To_device_seq is the third tag, and this count is incremented by 1 when there is a new data request; To_pcie_key is the fourth tag, which is used to store data sent by the device simulator service to the PCIE simulator service; To_pcie_seq is the fifth tag, and this count is incremented by 1 when there is a new data request.

[0057] Step S23: When the PCIE simulator service sends a first data request to the device simulator service, route the first data request to the corresponding downstream port of the PCIE simulator service through the PCIE simulator service, fill in the second tag, increase the value corresponding to the third tag, and then wait for the device simulator service to process the first data request.

[0058] In an embodiment of the present application, when the PCIE simulator service sends a first data request to the device simulator service, the PCIE simulator service is responsible for routing the PCIE TLP packet and sending the TLP packet to the corresponding device simulator service.

[0059] Specifically, for the process in which the PCIE simulator service sends the first data request (TLP) to the device simulator: The PCIE simulator service routes the TLP to the corresponding Downstream port; the PCIE simulator service fills in the second tag To_device_key; the PCIE simulator service increments the third tag To_device_seq; then the PCIE simulator service waits for the device simulator to complete the TLP processing. It should be noted that before filling in the second tag To_device_key and incrementing the third tag To_device_seq, the PCIE simulator service needs to first check whether the first tag is valid. If the first tag is invalid, then the TLP packet may be an incorrect packet and needs to be discarded; only when the first tag is valid will the data communication process be executed according to the above steps.

[0060] In the embodiment of the present application, the device simulator receives and processes the TLP packet sent by the PCIE simulator service. Specifically, the device simulator service detects an increment in the value of the third tag To_device_seq; the device simulator service reads the value of the second tag To_device_key, parses and processes the TLP packet; when the device simulator service updates the value of the second tag To_device_key, it indicates that the TLP processing is complete.

[0061] It should be noted that the second tag is a block of space used to store the data sent from the PCIE simulator service to the device simulator service. Most of it is used to store interactive data, but there are also some flag fields (marking fields) in the second tag. When the device simulator service updates the value of the second tag To_device_key, it also updates the flag fields.

[0062] For example, during the process of waiting for the device simulator service to process the first data request, if the first data request is a write-type TLP, then the device simulator service will perform corresponding processing on the data stored in the data space of the second tag read, and update the flag field of the second tag after the processing is completed, such as setting it to 1 to indicate that the processing is complete; if the first data request is a read-type TLP, then the device simulator service will fill in the relevant data corresponding to the read request into the data space in the second tag, and then update the flag field of the second tag, such as setting it to 1 to indicate that the processing is complete.

[0063] In the embodiments of the present application, the PCIE simulator cyclically reads a certain bit of the flag field, such as determining whether the bit is 1. If it is not 1, it will keep cycling. When the PCIE simulator service detects that this bit is 1, it will exit the loop and then process other transactions. For example, after exiting the loop, for a write-type TLP, there is no other transaction to process; for a read-type TLP, it is necessary to encapsulate the updated data in the data space within the second tag into a read reply TLP packet and send it to the Host.

[0064] Step S24: When the device simulator service sends a second data request to the PCIE simulator service, the device simulator service fills in the fourth tag and increases the value corresponding to the fifth tag, and then waits for the PCIE simulator service to process the second data request.

[0065] In the embodiments of the present application, when the device simulator service sends a second data request to the PCIE simulator service, the resources between the device simulator services are isolated from each other. The crash of one device simulator service does not affect other device simulator services and does not affect the PCIE simulator service.

[0066] Specifically, for the process of the device simulator service sending a second data request (creating a PCIE device / interrupt) to the PCIE simulator service: the device simulator service fills in the fourth tag To_pcie_key; the device simulator service increases the fifth tag To_pcie_seq; and then the device simulator service waits for the PCIE simulator service to finish processing.

[0067] In the embodiments of the present application, the PCIE simulator service is responsible for maintaining the Downstream information. Specifically, the PCIE simulator service detects an increase in the value of the fifth tag To_pcie_seq; the PCIE simulator service reads the value of the fourth tag To_pcie_key, parses and processes the second data request; and when the PCIE simulator service updates the value of the fourth tag To_pcie_key, it indicates that the request processing is completed.

[0068] Similarly, it can be understood that the fourth tag is also a piece of space, which is a section of space used to store the data sent by the device simulator service to the PCIE simulator service. Most of it is used to store interaction data, and there are also some flag fields. When the PCIE simulator service updates the value of the fourth tag To_pcie_key, it also updates the flag field.

[0069] For example, during the process of waiting for the PCIE simulator service to process the second data request, if the second data request is an interrupt type request, the PCIE simulator service will encapsulate the data stored in the data space within the fourth tag into a write type TLP packet and send it to the Host, and then update the flag field of the fourth tag. For example, setting it to 1 indicates that the processing is completed. If the second data request is a device creation request, the PCIE simulator service will perform corresponding processing on the data stored in the data space within the fourth tag. For example, it will create a device according to the type, attributes, etc., and then attach the device to a certain Downstream in the PCIE topology. At the same time, it will actively send a write type TLP packet of the bridge interrupt type to the Host (triggering the Host hot plug interrupt service program to probe the new device), then put the returned data into the data space within the fourth tag to overwrite the previous data, and finally update the flag field of the fourth tag. For example, setting it to 1 indicates that the processing is completed.

[0070] In the embodiment of this application, the device simulator service has been continuously looping to read a certain bit of the flag field. For example, it determines whether this bit is 1. If it is not 1, it will keep looping. After the device simulator service detects that this bit is 1, it will exit the loop and then process other transactions. For example, after exiting the loop, for an interrupt type request, there are no other transactions to process; for a device creation request, it is necessary to process the data in the data space within the fourth tag.

[0071] The PCIE topology and PCIE device simulation method provided by this application is applied to an ECPU simulator. By splitting the services in the ECPU simulator, a PCIE simulator service and multiple device simulator services are obtained. Among them, the device simulator services generate different PCIE devices. Then, a PCIE device channel table for querying data communication information allocated in the hardware layer base address register space is obtained. When the PCIE simulator service sends a first data request to the device simulator service, the PCIE simulator service routes the first data request to the corresponding downstream port of the PCIE simulator service, fills in the second tag, and increases the value corresponding to the third tag, and then waits for the device simulator service to process the first data request. When the device simulator service sends a second data request to the PCIE simulator service, the device simulator service fills in the fourth tag, increases the value corresponding to the fifth tag, and then waits for the PCIE simulator service to process the second data request. It can be seen that splitting the services of the ECPU simulator into a lightweight PCIE simulator service and multiple lightweight device simulator services increases the robustness of the PCIE topology and the flexibility of PCIE device implementation. By means of the hardware layer base address register, a communication channel for the PCIE simulator service and the device simulator service is provided to implement the simulation of the entire PCIE topology structure and different types of PCIE devices. For the PCIE simulator service, it is responsible for the generation and maintenance of the PCIE topology. For the device simulator service, it is responsible for the generation and maintenance of PCIE devices, and the resources between device simulator services are isolated from each other. The crash of one device simulator service does not affect other device simulator services or the PCIE simulator service. In this way, the decoupling of the PCIE topology and PCIE devices is achieved.

[0072] Correspondingly, an embodiment of this application also discloses a PCIE topology and PCIE device simulation device. Refer to Figure 6 As shown, it is applied to an ECPU simulator. The device includes:

[0073] A service splitting module 11, configured to split the services in the ECPU simulator to obtain a PCIE simulator service and multiple device simulator services. Among them, the device simulator services generate different PCIE devices;

[0074] A PCIE device channel table acquisition module 12, configured to acquire a PCIE device channel table for querying data communication information allocated in the hardware layer base address register space;

[0075] The PCIE topology and PCIE device simulation module 13 is used to perform data communication between the PCIE simulator service and the device simulator service according to the PCIE device channel table, so as to simulate the PCIE topology and PCIE devices.

[0076] Among them, for the more specific working processes of the above-mentioned various modules, reference can be made to the corresponding content disclosed in the foregoing embodiments, and details will not be elaborated here.

[0077] Thus, through the above solution of this embodiment, when applied to the ECPU simulator, by splitting the services in the ECPU simulator, a PCIE simulator service and multiple device simulator services are obtained; among them, the device simulator services generate different PCIE devices; then, a PCIE device channel table for querying data communication information allocated by the hardware layer base address register space is obtained; finally, according to the PCIE device channel table, data communication is performed between the PCIE simulator service and the device simulator service to simulate the PCIE topology and the PCIE devices. It can be seen that the services of the ECPU simulator are split into a lightweight PCIE simulator service and multiple lightweight device simulator services, thereby increasing the robustness of the PCIE topology and the flexibility of the implementation of PCIE devices. With the help of the hardware layer base address register to provide a communication channel for the PCIE simulator service and the device simulator service, the simulation of the entire PCIE topology structure and different types of PCIE devices is realized. For the PCIE simulator service, it is responsible for the generation and maintenance of the PCIE topology; for the device simulator service, it is responsible for the generation and maintenance of the PCIE devices, and the resources between the device simulator services are isolated from each other. The crash of one device simulator service does not affect other device simulator services and does not affect the PCIE simulator service; in this way, the decoupling of the PCIE topology and the PCIE devices is realized.

[0078] Furthermore, the embodiment of the present application also discloses an electronic device Figure 7 It is a structural diagram of an electronic device 20 shown according to an exemplary embodiment. The content in the figure should not be considered as any limitation to the scope of use of the present application.

[0079] Figure 7 It is a schematic structural diagram of an electronic device 20 provided by an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. Among them, the memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor 21 to implement the relevant steps in the PCIE topology and PCIE device simulation method disclosed in any of the foregoing embodiments. In addition, the electronic device 20 in this embodiment may specifically be an ECPU simulator.

[0080] In this embodiment, the power supply 23 is used to provide operating voltages for the various hardware devices on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and specific limitations thereof are not provided herein; the input / output interface 25 is used to obtain external input data or output data to the outside, and the specific interface type thereof can be selected according to specific application requirements, and specific limitations are not provided herein.

[0081] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, a random access memory, a magnetic disk, an optical disk, etc., and the resources stored thereon can include an operating system 221, a computer program 222, and data 223, etc., and the data 223 can include various kinds of data. The storage method can be transient storage or permanent storage.

[0082] Among them, the operating system 221 is used to manage and control the various hardware devices and the computer program 222 on the electronic device 20, and it can be Windows Server, Netware, Unix, Linux, etc. In addition to the computer program that can be used to complete the PCIE topology and PCIE device simulation methods executed by the electronic device 20 disclosed in any of the foregoing embodiments, the computer program 222 can further include computer programs that can be used to complete other specific tasks.

[0083] Furthermore, the embodiments of this application also disclose a computer-readable storage medium, and the computer-readable storage medium mentioned here includes a random access memory (Random Access Memory, RAM), internal memory, read-only memory (Read-Only Memory, ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, magnetic disks, optical disks, or any other form of storage medium known in the technical field. Among them, when the computer program is executed by a processor, the foregoing PCIE topology and PCIE device simulation methods are implemented. For the specific steps of this method, reference can be made to the corresponding content disclosed in the foregoing embodiments, and details are not described herein again.

[0084] The various embodiments in this specification are described in a progressive manner, and the key point of each embodiment is to illustrate the differences from other embodiments. For the same or similar parts between the various embodiments, reference can be made to each other. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and reference can be made to the description of the method part for related parts.

[0085] The steps of the PCIE topology and PCIE device simulation or algorithm described in combination with the embodiments disclosed in this article can be implemented directly in hardware, software modules executed by a processor, or a combination of both. The software module can be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, or any other form of storage medium well known in the technical field.

[0086] Finally, it should also be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the said element.

[0087] The above has introduced in detail a method, device, equipment and medium for simulating a PCIE topology and a PCIE device provided by the present invention. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A PCIE topology and PCIE device simulation method, characterized in that Applied to an ECPU simulator, including: Splitting the services in the ECPU simulator to obtain a PCIE simulator service and multiple device simulator services; wherein, the device simulator services generate different PCIE devices; Obtaining a PCIE device channel table for querying data communication information allocated in the base address register space of the hardware layer; each device simulator service occupies one entry in the PCIE device channel table; the entry includes a first tag for recording the loading status of the device simulator service, a second tag representing the space for storing the data sent by the PCIE simulator service to the device simulator service, a third tag for counting the data requests notified by the PCIE simulator service to the device simulator service, a fourth tag representing the space for storing the data sent by the device simulator service to the PCIE simulator service, and a fifth tag for counting the data requests notified by the device simulator service to the PCIE simulator service; According to the PCIE device channel table, performing data communication between the PCIE simulator service and the device simulator services to simulate the PCIE topology and the PCIE devices.

2. The PCIE topology and PCIE device simulation method according to claim 1, characterized in that The performing data communication between the PCIE simulator service and the device simulator services according to the PCIE device channel table to simulate the PCIE topology and the PCIE devices includes: When the PCIE simulator service sends a first data request to the device simulator service, routing the first data request to the corresponding downstream port of the PCIE simulator service through the PCIE simulator service, filling in the second tag, increasing the value corresponding to the third tag, and then waiting for the device simulator service to process the first data request.

3. The PCIE topology and PCIE device simulation method according to claim 2, characterized in that The waiting for the device simulator service to process the first data request includes: If the device simulator service detects an increase in the value corresponding to the third tag, reading the second tag, then parsing and processing the first data request, and updating the second tag when the first data request is processed.

4. The PCIE topology and PCIE device simulation method according to claim 1, characterized in that The performing data communication between the PCIE simulator service and the device simulator services according to the PCIE device channel table to simulate the PCIE topology and the PCIE devices includes: When the device simulator service sends a second data request to the PCIE simulator service, filling in the fourth tag and increasing the value corresponding to the fifth tag through the device simulator service, and then waiting for the PCIE simulator service to process the second data request.

5. The PCIE topology and PCIE device simulation method according to claim 4, characterized in that The waiting for the PCIE simulator service to process the second data request includes: If the PCIE simulator service detects an increase in the value corresponding to the fifth tag, reading the fourth tag, then parsing and processing the second data request, and updating the fourth tag when the second data request is processed.

6. The PCIE topology and PCIE device simulation method according to any one of claims 1 to 5, characterized in that Performing data communication between the PCIE simulator service and the device simulator service according to the PCIE device channel table to simulate a PCIE topology and PCIE devices includes: Performing data communication between the PCIE simulator service and the device simulator service based on a polling mechanism according to the PCIE device channel table to simulate a PCIE topology and PCIE devices.

7. A PCIE topology and PCIE device simulation apparatus, characterized in that Applied to an ECPU simulator, it includes: A service splitting module for splitting the services in the ECPU simulator to obtain a PCIE simulator service and multiple device simulator services; wherein, the device simulator services generate different PCIE devices. A PCIE device channel table acquisition module for acquiring a PCIE device channel table for querying data communication information allocated in the base address register space of the hardware layer; each device simulator service in the PCIE device channel table occupies an entry; the entry includes a first tag for recording the loading status of the device simulator service, a second tag representing the space for storing data sent from the PCIE simulator service to the device simulator service, a third tag for counting data requests notified by the PCIE simulator service to the device simulator service, a fourth tag representing the space for storing data sent from the device simulator service to the PCIE simulator service, and a fifth tag for counting data requests notified by the device simulator service to the PCIE simulator service. A PCIE topology and PCIE device simulation module for performing data communication between the PCIE simulator service and the device simulator service according to the PCIE device channel table to simulate a PCIE topology and PCIE devices.

8. An electronic device, characterized in that The electronic device includes a processor and a memory; wherein, the memory is used to store a computer program, and the computer program is loaded and executed by the processor to implement the PCIE topology and PCIE device simulation method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that For storing a computer program; wherein the computer program, when executed by a processor, implements the PCIE topology and PCIE device simulation method according to any one of claims 1 to 6.

Images