Method for protecting metal interface at bottom of via hole in copper wire interconnection process

Abstract

The present invention provides a method for protecting the metal interface at the bottom of a via hole in a copper wire interconnect process. A substrate is provided, and a first interlayer dielectric layer is formed on the substrate. A first opening is formed in the first interlayer dielectric layer, and a first interconnect layer is filled in the first opening. The first interconnect layer includes a first metal layer and a second metal layer formed on the surface of the first metal layer. An etch stop layer is formed on the first interconnect layer and the first interlayer dielectric layer, and a second interlayer dielectric layer is formed on the etch stop layer. The second interlayer dielectric layer and the etch stop layer thereunder are etched by a dry etching method to form a second opening, so that the second metal layer is exposed. In the dry etching, the gas flow rate of the oxygen-containing gas is controlled within a preset range and / or a protective gas is added. Under the atmosphere of the protective gas, the substrate is cleaned with an electrically neutral liquid. The method of the present invention solves the problem that it is difficult to completely solve the damage defects on the surface of the contact metal under the via hole due to a single process adjustment.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for protecting the metal interface at the bottom of a via in a copper wire interconnect process. Background Art

[0002] In the copper wire interconnect process after 14 nm, in order to improve the filling ability and reliability, a new element cobalt is introduced, and at the same time, higher purity copper is used to replace the alloy copper used in the past nodes. However, certain physical and chemical properties of cobalt, as well as the high-purity copper, make it necessary to pay more attention to certain variables in the process integration to ensure that the electrical and reliable performance meet the requirements.

[0003] In the initial stage of 14 nm development, in order to maintain continuity between generations, many processes make as small changes as possible based on the previous nodes. However, in the final electrical tests and reliability tests, serious problems will be found, mainly the lack of copper at the bottom of the via, as Figure 1 shown.

[0004] Through analysis and a large amount of experimental data, it is proved that this kind of failure cannot be solved by adjusting a single process parameter, and a cross-process adjustment plan needs to be proposed from the level of process integration.

[0005] To solve the above problems, a new method for protecting the metal interface at the bottom of a via in a copper wire interconnect process needs to be proposed. Summary of the Invention

[0006] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a method for protecting the metal interface at the bottom of a via in a copper wire interconnect process, which is used to solve the problem that in the copper wire interconnect process in the prior art, a new element cobalt is introduced, and at the same time, higher purity copper is used to replace the alloy copper used in the past nodes, which will cause the lack of copper at the bottom of the via, and this kind of failure cannot be solved by adjusting a single process parameter.

[0007] To achieve the above purpose and other related purposes, the present invention provides a method for protecting the metal interface at the bottom of a via in a copper wire interconnect process, including:

[0008] Step 1: Provide a substrate, on which a first interlayer dielectric layer is formed, a first opening is formed on the first interlayer dielectric layer, the first opening is filled with a first interconnect layer, the first metal interconnect layer includes a first metal layer and a second metal layer formed on the surface of the first metal layer, an etch stop layer is formed on the first interconnect layer and the first interlayer dielectric layer, and a second interlayer dielectric layer is formed on the etch stop layer;

[0009] Step 2: Use dry etching to etch the second interlayer dielectric layer and the underlying etch stop layer to form a second opening, exposing the second metal layer. In the dry etching process, control the gas flow rate of the oxygen-containing gas within a preset range and / or add a protective gas;

[0010] Step 3: Under the atmosphere of the protective gas, clean the substrate with an electrically neutral liquid;

[0011] Step 4: Under the atmosphere of the protective gas, use a metrology tool to detect whether the critical dimension after etching meets the design standard. If so, form a third metal layer on the second opening.

[0012] Preferably, the substrate in Step 1 includes a bulk semiconductor substrate or a silicon-on-insulator substrate.

[0013] Preferably, the materials of the first and second interlayer dielectric layers in Step 1 are both silicon dioxide.

[0014] Preferably, the material of the first metal layer in Step 1 is copper.

[0015] Preferably, the material of the second metal layer in Step 1 is cobalt.

[0016] Preferably, the material of the etch stop layer in Step 1 is silicon nitride.

[0017] Preferably, the oxygen-containing gas in Step 2 includes oxygen and carbon dioxide.

[0018] Preferably, the protective gas in Steps 2 to 4 is nitrogen.

[0019] Preferably, in the LRM step of the dry etching in Step 2, the gas flow rate of the oxygen-containing gas is less than or equal to 45 ccm.

[0020] Preferably, in the PET step of the dry etching in Step 2, the gas flow rate of the protective gas is less than or equal to 200 ccm.

[0021] Preferably, the material of the third metal layer in Step 4 is tantalum nitride.

[0022] Preferably, the third metal layer is formed by physical vapor deposition in Step 4.

[0023] Preferably, the third metal layer is formed by physical vapor deposition within 10 seconds in Step 4, and the magnetic field strength in the anti-sputtering process does not exceed 0.2 T.

[0024] Preferably, any of the above methods is used for the back-end copper wire interconnect process at a 14-nanometer and below technology node.

[0025] As described above, the method for protecting the metal interface at the bottom of the via hole in the copper wire interconnection process of the present invention has the following beneficial effects:

[0026] From the perspective of process integration, the method of the present invention solves the problem of damage defects on the surface of the contact metal under the via hole from the root cause (environmental oxygen content and oxygen contact time) by modifying various relevant process parameters (involving etching, cleaning, annealing, physical vapor deposition) and the overall environment of the wafer. The method of the present invention focuses on the integrated adjustment of each process and does not introduce new defect problems; in the comparison of experimental data, the average resistance of the via hole decreases, the convergence of the via hole resistance value of the overall wafer improves, and the reliability (electromigration performance) of the via hole increases by an order of magnitude, and remains at the same level in the defect inspection after etching and subsequent physical polishing. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 Schematic diagram showing the copper deficiency at the bottom of the via hole in the prior art;

[0028] Figure 2 Schematic diagram showing the process flow of the present invention;

[0029] Figure 3 Schematic diagram showing the dry etching of the present invention;

[0030] Figure 4 Schematic diagram showing the cleaning of the present invention;

[0031] Figure 5 Schematic diagram showing the measurement of critical dimensions of the present invention;

[0032] Figure 6 Schematic diagram showing the formation of the third metal layer of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0033] The following specific examples illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0034] Please refer to Figure 2 , the present invention provides a method for protecting the metal interface at the bottom of the via hole in the copper wire interconnection process, including:

[0035] Step 1, please refer to Figure 3, a substrate is provided. A first interlayer dielectric layer 101 is formed on the substrate. A first opening is formed on the first interlayer dielectric layer 101. The shape of the first opening is set by recipe parameters. The first opening is filled with a first interconnect layer. The first metal interconnect layer includes a first metal layer 102 and a second metal layer 103 formed on the surface of the first metal layer 102. An etch stop layer 104 is formed on the first interconnect layer and the first interlayer dielectric layer 101. A second interlayer dielectric layer 105 is formed on the etch stop layer 104;

[0036] In an embodiment of the present invention, the substrate in step one includes a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulator layer under a thin semiconductor layer that serves as the active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor generally include the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloy, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or their alloys (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.) or their combinations. The semiconductor material may be doped or undoped. Other substrates that can be used include multi-layer substrates, gradient substrates or mixed-orientation substrates.

[0037] In an embodiment of the present invention, the materials of the first and second interlayer dielectric layers in step one are both silicon dioxide.

[0038] In an embodiment of the present invention, the material of the first metal layer 102 in step one is copper, and it can generally be formed by chemical vapor deposition.

[0039] In an embodiment of the present invention, the material of the second metal layer 103 in step one is cobalt, and it can generally be formed by chemical vapor deposition, that is, a layer of cobalt is formed on the first opening by chemical vapor deposition, and then a layer of copper and another layer of cobalt on the copper layer are formed.

[0040] In an embodiment of the present invention, the material of the etch stop layer 104 in step one is silicon nitride.

[0041] Step two, please continue to refer to Figure 3 , use a dry etching 106 method to etch the second interlayer dielectric layer 105 and the etch stop layer 104 thereunder to form a second opening. The shape of the second opening is set by recipe parameters. Contact holes for metal interconnection are formed at the first and second openings, exposing the second metal layer 103. In the dry etching 106, control the gas flow rate of the oxygen-containing gas within a preset range and / or add a protective gas 107. The protective gas 107 is a gas that slows down the oxidation of the copper layer;

[0042] In an embodiment of the present invention, the oxygen-containing gas in step two includes oxygen and carbon dioxide.

[0043] In an embodiment of the present invention, the protective gas 107 in steps two to four is nitrogen.

[0044] In an embodiment of the present invention, in the LRM (Line Remove) step of the dry etching 106 in step two, the gas flow rate of the oxygen-containing gas is less than or equal to 45 ccm.

[0045] In an embodiment of the present invention, in the PET (Post Etch) step of the dry etching 106 in step two, the gas flow rate of the protective gas 107 is less than or equal to 200 ccm. In addition, the gas flow rate can be adjusted to ensure that the etching time does not need to be extended. Please refer to Figure 3 , the function of the protective gas 107 is to protect the underlying copper from excessive oxidation and the cobalt film from chemical damage.

[0046] Step three, please refer to Figure 4 , in the post-etch cleaning process 108, since cobalt will undergo a chemical reaction in water containing any ions, it is necessary to use an electro-neutral liquid as much as possible (weakly acidic carbonic acid is usually added, which has an etching effect on the oxidized copper on the surface). The electro-neutral solution can use the Neutral_Solution product of ACM Research. Therefore, in the atmosphere of the protective gas 107, the substrate is cleaned with the electro-neutral liquid;

[0047] Step four, please refer to Figure 5 , in the atmosphere of the protective gas 107, use a metrology tool (such as an electron microscope metrology tool) to detect whether the critical dimensions after etching (such as the line width of the opening and the thickness of the interconnect layer) meet the design standards. If so, a third metal layer 109 is formed on the second opening, forming a structure as shown in Figure 6 . The inventors of the present invention found that the effect of the single-wafer annealing process after etching in the new cleaning process 108 is not as good as before, so it can be deleted. Therefore, before the metrology step, the single-wafer annealing process is deleted compared to the prior art.

[0048] In an embodiment of the present invention, the material of the third metal layer 109 in step four is tantalum nitride.

[0049] In an embodiment of the present invention, the third metal layer 109 is formed by physical vapor deposition in step four. After that, copper metal can be deposited on the third metal layer 109 to form the second interconnect layer.

[0050] In an embodiment of the present invention, in step four, a third metal layer is formed within 10 seconds by physical vapor deposition, and the magnetic field strength in the reverse sputtering process does not exceed 0.2 T (Tesla).

[0051] In an embodiment of the present invention, any of the above methods is used for the back-end copper wire interconnection process of 14-nanometer and below technology nodes.

[0052] In an embodiment of the present invention, in the experimental data comparison, the average resistance at the opening, i.e., the via hole, decreased by 40%, the convergence of the via hole resistance value of the overall wafer became 100% better, the reliability (electromigration performance) of the via hole increased by one order of magnitude, and it remained at the same level in the defect inspection after etching and subsequent physical polishing.

[0053] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, number, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0054] In summary, considering process integration, the method of the present invention solves the problem of damage defects on the surface of the contact metal under the via hole, which is difficult to completely solve by a single process adjustment, from the root (environmental oxygen content and oxygen contact time) by modifying various process parameters (involving etching, cleaning, annealing, physical vapor deposition) and the overall wafer environment. The method of the present invention focuses on the integrated adjustment of each process and does not introduce new defect problems; in the experimental data comparison, the average resistance of the via hole decreases, the convergence of the via hole resistance value of the overall wafer improves, the reliability (electromigration performance) of the via hole increases by one order of magnitude, and it remains at the same level in the defect inspection after etching and subsequent physical polishing. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0055] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for protecting the metal interface at the bottom of vias in a copper wire interconnection process, characterized in that, At least including: Step 1: Provide a substrate, on which a first interlayer dielectric layer is formed. A first opening is formed on the first interlayer dielectric layer, and a first interconnect layer is filled in the first opening. The first interconnect layer includes a first metal layer and a second metal layer formed on the surface of the first metal layer. The material of the first metal layer is copper, and the material of the second metal layer is cobalt. An etch stop layer is formed on the first interconnect layer and the first interlayer dielectric layer, and a second interlayer dielectric layer is formed on the etch stop layer. Step 2: Use a dry etching method to etch the second interlayer dielectric layer and the etch stop layer thereunder to form a second opening, so that the second metal layer is exposed. During the dry etching, control the gas flow rate of the oxygen-containing gas within a preset range and add a protective gas, and the protective gas is nitrogen. Wherein, in the LRM step of the dry etching, the gas flow rate of the oxygen-containing gas is less than or equal to 45 ccm, and in the PET step of the dry etching, the gas flow rate of the protective gas is less than or equal to 200 ccm. Step 3: Clean the substrate with an electrically neutral liquid in the atmosphere of the protective gas. Step 4: In the atmosphere of the protective gas, use a metrology tool to detect whether the critical dimension after etching meets the design standard. If so, form a third metal layer on the second opening.

2. The method for protecting the metal interface at the bottom of the via hole in the copper wire interconnection process according to claim 1, wherein: The substrate in Step 1 includes a bulk semiconductor substrate or a silicon-on-insulator substrate.

3. The method for protecting the metal interface at the bottom of the via hole in the copper wire interconnection process according to claim 1, characterized in that: The materials of the first and second interlayer dielectric layers in Step 1 are both silicon dioxide.

4. The method for protecting the metal interface at the bottom of the via hole in the copper wire interconnection process according to claim 1, wherein: The material of the etch stop layer in Step 1 is silicon nitride.

5. The method for protecting the metal interface at the bottom of the via hole in the copper wire interconnection process according to claim 1, wherein: The oxygen-containing gas in Step 2 includes oxygen and carbon dioxide.

6. The method for protecting the metal interface at the bottom of the via hole in the copper wire interconnection process according to claim 1, wherein: The material of the third metal layer in Step 4 is tantalum nitride.

7. The method for protecting the metal interface at the bottom of the via hole in the copper wire interconnection process according to claim 6, wherein: The third metal layer is formed by physical vapor deposition in Step 4.

8. The method for protecting the metal interface at the bottom of the via hole in the copper wire interconnection process according to claim 7, wherein: The third metal layer is formed within 10 seconds by physical vapor deposition in Step 4, and the magnetic field strength in the anti-sputtering process does not exceed 0.2 T.

9. The method for protecting the metal interface at the bottom of the via hole in the copper wire interconnection process according to claim 1, characterized in that: The method is used for the back-end copper wire interconnect process of 14-nanometer and below technology nodes.

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