A Gallium Nitride-based HEMT device, its manufacturing method, and a chip

Abstract

This application belongs to the field of semiconductor technology and provides a gallium nitride-based HEMT device, a preparation method, and a chip. By integrating a Schottky diode into the gallium nitride-based HEMT device, the Schottky diode is composed of a channel layer, a barrier layer, a back capping layer, and a back gate layer. The back gate layer is disposed on the back surface of the back capping layer and is not in contact with the substrate layer that is also located on the back surface of the back capping layer. By dynamically controlling the voltage of the back gate layer, a lower forward conduction resistance and a higher device breakdown voltage are achieved, improving the performance of the device in the unclamped inductive load switching process test, and solving the technical problem in the related art that due to the lack of a corresponding parasitic diode in the GaN-based HEMT, the backflow current generated during the UIS test oscillates inside the device, causing devastating damage to the device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a gallium nitride-based HEMT device, a preparation method, and a chip. Background Art

[0002] As a representative of the third-generation semiconductor materials, gallium nitride (GaN) has many excellent properties, such as high critical breakdown electric field, high electron mobility, high two-dimensional electron gas concentration and good high-temperature working ability.

[0003] During the unclamped inductive switching (UIS) test, silicon-based metal-oxide-semiconductor field-effect transistors (MOSFETs) have parasitic diodes that block reverse current conduction. However, GaN-based high electron mobility transistors (HEMTs) lack these diodes, causing the recharge current generated during UIS testing to oscillate within the device, potentially damaging it. Summary of the Invention

[0004] To address the aforementioned technical issues, the present invention provides a gallium nitride (GaN)-based HEMT device, a preparation method, and a chip. These devices aim to address the technical issue in related technologies where GaN-based HEMTs lack corresponding parasitic diodes, causing the recharge current generated during UIS testing to oscillate within the device, potentially causing devastating damage to the device.

[0005] The present invention provides a gallium nitride-based HEMT device, wherein a Schottky diode is integrated in the gallium nitride-based HEMT device. The Schottky diode includes:

[0006] channel layer;

[0007] a barrier layer provided on the front surface of the channel layer;

[0008] a back cap layer disposed on the back side of the channel layer;

[0009] an ohmic metal layer disposed on a first side of the barrier layer;

[0010] a Schottky metal layer provided on a second side of the barrier layer; wherein the ohmic metal layer is connected to the drain electrode of the gallium nitride-based HEMT device, and the Schottky metal layer is connected to the source electrode of the gallium nitride-based HEMT device;

[0011] a substrate layer disposed on the back side of the back cap layer;

[0012] A back gate layer disposed on the back surface of the back capping layer, and the back gate layer is not in contact with the substrate layer.

[0013] In one embodiment, the ohmic metal layer and the Schottky metal layer are in an L-shaped structure.

[0014] In one embodiment, the Schottky diode further includes a passivation layer, and the passivation layer is disposed between the horizontal portion of the ohmic metal layer and the barrier layer, and between the horizontal portion of the Schottky metal layer and the barrier layer;

[0015] The vertical portion of the ohmic metal layer is disposed on the surface of the first side of the barrier layer, and the vertical portion of the Schottky metal layer is disposed on the surface of the second side of the barrier layer.

[0016] In one embodiment, the width of the horizontal portion of the ohmic metal layer is greater than the width of the vertical portion of the ohmic metal layer.

[0017] In one embodiment, the width of the horizontal portion of the Schottky metal layer is greater than the width of the vertical portion of the Schottky metal layer.

[0018] In one embodiment, the barrier layer is AlGaN and the channel layer is gallium nitride.

[0019] In one embodiment, the back capping layer is P-type gallium nitride.

[0020] In one embodiment, the Schottky diode is disposed under the gate electrode, drain electrode or source electrode of the gallium nitride-based HEMT device, and the Schottky metal layer is connected to the source electrode of the gallium nitride-based HEMT device, and the ohmic metal layer is connected to the drain electrode of the gallium nitride-based HEMT device.

[0021] A second aspect of the embodiments of the present application further provides a method for manufacturing a gallium nitride-based HEMT device, including:

[0022] Forming a back capping layer, a channel layer and a barrier layer which are stacked on the front surface of the substrate layer;

[0023] Forming an ohmic metal layer on the first side of the barrier layer and forming a Schottky metal layer on the second side of the barrier layer; wherein, the ohmic metal layer is connected to the drain electrode of the gallium nitride-based HEMT device, and the Schottky metal layer is connected to the source electrode of the gallium nitride-based HEMT device;

[0024] Etching a specified area on the back surface of the substrate layer to form an etching area; wherein, the etching area penetrates into the back capping layer;

[0025] A back gate layer that does not contact the substrate layer is formed in the etching region; wherein, the position of the back gate layer is staggered from the positions of the ohmic metal layer and the Schottky metal layer.

[0026] In a third aspect of the embodiments of the present application, a chip is further provided. The chip includes a gallium nitride-based HEMT device as described in any one of the above; or the chip includes a gallium nitride-based HEMT device prepared by the preparation method as described in any one of the above.

[0027] The beneficial effects of the embodiments of the present application compared with the prior art are as follows: By integrating a Schottky diode in a gallium nitride-based HEMT device, the Schottky diode is composed of a channel layer, a barrier layer, a back cap layer, and a back gate layer. The back gate layer is disposed on the back surface of the back cap layer and does not contact the substrate layer that is also located on the back surface of the back cap layer. By dynamically controlling the voltage of the back gate layer, a lower forward conduction resistance and a higher device breakdown voltage are achieved, improving the performance of the device in the non-clamped inductive load switching process test, and solving the technical problem in the related art that due to the lack of a corresponding parasitic diode in the GaN-based HEMT, the backflow current generated in the UIS test oscillates inside the device, causing devastating damage to the device. Description of the Drawings

[0028] Figure 1 It is a schematic structural diagram of a Schottky diode integrated in a gallium nitride-based HEMT device provided by an embodiment of the present application;

[0029] Figure 2 It is a partial cross-sectional structural diagram of a gallium nitride-based HEMT device provided by an embodiment of the present application;

[0030] Figure 3 It is a schematic flow diagram of integrating a Schottky diode in a gallium nitride-based HEMT device provided by an embodiment of the present application;

[0031] Figure 4 It is a schematic structural diagram of forming a back cap layer 200, a channel layer 300, and a barrier layer 400 provided by an embodiment of the present application;

[0032] Figure 5 It is a schematic structural diagram of forming an ohmic metal layer 510 and a Schottky metal layer 520 provided by an embodiment of the present application;

[0033] Figure 6 It is a schematic structural diagram of forming an etching region 101 provided by an embodiment of the present application;

[0034] Figure 7 It is a schematic structural diagram after forming a back gate layer 700 provided by an embodiment of the present application. Detailed Embodiments

[0035] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clear and understandable, the following further details this application in combination with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not used to limit this application.

[0036] It should be noted that when an element is referred to as "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0037] It should be understood that the orientation or positional relationship indicated by the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to this application.

[0038] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of this application, "a plurality" means one or more than one, unless otherwise specifically defined.

[0039] The reference to "one embodiment", "some embodiments" or "embodiments" in the description of this application means that a specific feature, structure or characteristic described in connection with the embodiment is included in one or more embodiments of this application. Thus, the statements "in one embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments", "in a specific embodiment", "in a specific application", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. In addition, in one or more embodiments, specific features, structures or characteristics can be combined in any suitable manner.

[0040] As a representative of third-generation semiconductor materials, gallium nitride (GaN) has many excellent properties, such as high critical breakdown electric field, high electron mobility, high two-dimensional electron gas concentration, and good high-temperature working ability. Third-generation semiconductor devices based on gallium nitride, such as high electron mobility transistors (HEMTs) and heterostructure field effect transistors (HFETs), have been applied, especially in fields such as radio frequency and microwave that require high power and high frequency, showing obvious advantages.

[0041] In the UIS test, due to the existence of parasitic diodes in silicon-based MOSFETs, the reverse conduction of the cut-off current can be blocked. However, GaN-based HEMTs lack corresponding parasitic diodes, resulting in the backflow current generated in the UIS test oscillating inside the device, causing devastating damage to the device.

[0042] To solve the above technical problems, the embodiment of the present application provides a GaN-based HEMT device. The GaN-based HEMT device in this embodiment is integrated with a Schottky diode, and the Schottky diode is composed of a channel layer, a barrier layer, a back capping layer, and a back gate layer.

[0043] Specifically, as shown in Figure 1 the Schottky diode in this embodiment includes: a channel layer 300, a barrier layer 400, a back capping layer 200, an ohmic metal layer 510, a Schottky metal layer 520, a substrate layer 100, and a back gate layer 700.

[0044] In this embodiment, the barrier layer 400 is disposed on the front of the channel layer 300, the back capping layer 200 is disposed on the back of the channel layer 300, the ohmic metal layer 510 is disposed on the first side of the barrier layer 400, the Schottky metal layer 520 is disposed on the second side of the barrier layer 400, the substrate layer 100 is disposed on the back of the back capping layer 200, the back gate layer 700 is disposed on the back of the back capping layer 200, and the back gate layer 700 and the substrate layer 100 do not contact each other.

[0045] In this embodiment, the ohmic metal layer 510 is connected to the drain electrode of the gallium nitride-based HEMT device, and the Schottky metal layer 520 is connected to the source electrode of the gallium nitride-based HEMT device. The Schottky diode is composed of a channel layer 300, a barrier layer 400, a back capping layer 200, and a back gate layer 700. The back gate layer 700 is disposed on the back surface of the back capping layer 200 and does not contact the substrate layer 100 which is also located on the back surface of the back capping layer 200. By dynamically controlling the voltage of the back gate layer 700, a lower forward conduction resistance and a higher device breakdown voltage are achieved, improving the performance of the device in the non-clamped inductive load switching process test, and solving the technical problem in the related art that due to the lack of a corresponding parasitic diode in the GaN-based HEMT, the backflow current generated in the UIS test oscillates inside the device, causing devastating damage to the device.

[0046] In one embodiment, the ohmic metal layer 510 can form an ohmic contact with the barrier layer 400 and the channel layer 300, and the Schottky metal layer 520 can form a Schottky contact with the barrier layer 400 and the channel layer 300.

[0047] In one embodiment, as shown in Figure 1 the ohmic metal layer 510 and the Schottky metal layer 520 are in an L-shaped structure.

[0048] In one embodiment, as shown in Figure 1 the Schottky diode further includes a passivation layer 600. The passivation layer 600 is disposed between the horizontal portion of the ohmic metal layer 510 and the barrier layer 400, and between the horizontal portion of the Schottky metal layer 520 and the barrier layer 400. The vertical portion of the ohmic metal layer 510 is disposed on the surface of the first side of the barrier layer 400, and the vertical portion of the Schottky metal layer 520 is disposed on the surface of the second side of the barrier layer 400.

[0049] In this embodiment, the passivation layer 600 is disposed between the horizontal portion of the ohmic metal layer 510 and the barrier layer 400, and between the horizontal portion of the Schottky metal layer 520 and the barrier layer 400. The horizontal portions of the ohmic metal layer 510 and the Schottky metal layer 520 can help weaken the electric field spikes near the anode or cathode of the Schottky diode.

[0050] In one embodiment, the width of the horizontal portion of the ohmic metal layer 510 is greater than the width of the vertical portion of the ohmic metal layer 510.

[0051] In one embodiment, the width of the horizontal portion of the Schottky metal layer 520 is greater than the width of the vertical portion of the Schottky metal layer 520.

[0052] In one embodiment, the barrier layer 400 is AlGaN and the channel layer 300 is gallium nitride.

[0053] In this embodiment, the channel layer 300 can be entirely prepared from gallium nitride material.

[0054] In one embodiment, it can be formed by depositing gallium nitride material or epitaxially growing gallium nitride material on the back capping layer 200, and its thickness is greater than that of the back capping layer 200.

[0055] In one embodiment, the back capping layer 200 is a P-type gallium nitride.

[0056] In this embodiment, the back capping layer 200 can be entirely prepared by implanting P-type doping ions into gallium nitride material.

[0057] In one embodiment, the back capping layer 200 can be formed by depositing P-type gallium nitride material or epitaxially growing P-type gallium nitride material on the substrate layer 100.

[0058] In one embodiment, the thickness of the channel layer 300 is greater than that of the barrier layer 400.

[0059] In one embodiment, the Schottky diode is disposed below the gate electrode, drain electrode or source electrode of the gallium nitride-based HEMT device, and the Schottky metal layer is connected to the source electrode of the gallium nitride-based HEMT device, and the ohmic metal layer is connected to the drain electrode of the gallium nitride-based HEMT device.

[0060] In one embodiment, in combination with Figure 2 As shown, the source metal layer 801, gate metal layer 802 and drain metal layer 803 of the gallium nitride-based HEMT device are respectively disposed on the barrier layer 400.

[0061] In this embodiment, the source metal layer 801 of the gallium nitride-based HEMT device is connected to its source electrode, the drain metal layer 803 of the gallium nitride-based HEMT device is connected to its drain electrode, and the gate metal layer 802 of the gallium nitride-based HEMT device is connected to its gate electrode.

[0062] In combination with Figure 2 As shown, the back gate layer 700 is also disposed on both sides of the back capping layer 700 of the gallium nitride-based HEMT device. The back capping layer 700 of the gallium nitride-based HEMT device in this embodiment can be used to access the back gate voltage to adjust the two-dimensional electron gas channel inside the device. For example, if the back gate voltage is greater than 0V, the two-dimensional electron gas is enhanced, and the forward conduction resistance can be reduced. If the back gate voltage is less than 0V, the two-dimensional electron gas is weakened, and the breakdown voltage of the device under reverse bias can be increased.

[0063] In one embodiment, if the back gate layer 700 is disposed between the ohmic metal layer 510 and the Schottky metal layer 520, the ohmic metal layer 510 and the Schottky metal layer 520 are symmetrically arranged with respect to the central axis where the back gate layer 700 is located.

[0064] In one embodiment, an isolation material layer is used for isolation between the channel layer 300, the barrier layer 400, and the back cap layer 200 below the ohmic metal layer 510 and the Schottky metal layer 520 and the channel layer 300, the barrier layer 400, and the back cap layer 200 below the source metal layer 801, the gate metal layer 802, and the drain metal layer 803 of the gallium nitride-based HEMT device.

[0065] In one embodiment, the isolation material layer can be silicon oxide or silicon nitride, or can also be an organic insulating isolation material.

[0066] The embodiment of the present application also provides a manufacturing method of a gallium nitride-based HEMT device. Refer to Figure 3 As shown, the manufacturing method in this embodiment includes steps S10 to step S40.

[0067] In step S10, a back cap layer 200, a channel layer 300, and a barrier layer 400 are formed in a stacked manner on the front surface of the substrate layer 100.

[0068] In this embodiment, in combination with Figure 4 As shown, the back cap layer 200, the channel layer 300, and the barrier layer 400 are stacked on the front surface of the substrate layer 100. The back cap layer 200 is disposed on the back surface of the channel layer 300, and the barrier layer 400 is disposed on the front surface of the channel layer 300.

[0069] In one embodiment, the barrier layer 400 is AlGaN, and the channel layer 300 is gallium nitride.

[0070] In one embodiment, the back cap layer 200, the channel layer 300, and the barrier layer 400 can be formed on the substrate 100 through a conventional epitaxial process.

[0071] In one embodiment, the back cap layer 200 is P-type gallium nitride.

[0072] In one embodiment, the thickness of the channel layer 300 is greater than the thickness of the barrier layer 400.

[0073] In step S20, an ohmic metal layer 510 is formed on the first side of the barrier layer 400, and a Schottky metal layer 520 is formed on the second side of the barrier layer 400.

[0074] In this embodiment, in combination with Figure 5As shown, an ohmic metal layer 510 is disposed on a first side of the barrier layer 400, and a Schottky metal layer 520 is disposed on a second side of the barrier layer 400.

[0075] In one embodiment, an ohmic contact may be formed between the ohmic metal layer 510, the barrier layer 400, and the channel layer 300, and a Schottky contact may be formed between the Schottky metal layer 520, the barrier layer 400, and the channel layer 300.

[0076] In one embodiment, the ohmic metal layer 510 and the Schottky metal layer 520 may have an L-shaped structure, as shown in Figure 1 shown.

[0077] In one embodiment, before step S20, a passivation layer 600 is further formed on the barrier layer 400, and the position of the passivation layer 600 is as shown in Figure 1 shown.

[0078] The passivation layer 600 is disposed between the horizontal portion of the ohmic metal layer 510 and the barrier layer 400, and between the horizontal portion of the Schottky metal layer 520 and the barrier layer 400. The vertical portion of the ohmic metal layer 510 is disposed on the surface of the first side of the barrier layer 400, and the vertical portion of the Schottky metal layer 520 is disposed on the surface of the second side of the barrier layer 400.

[0079] In this embodiment, the passivation layer 600 is disposed between the horizontal portion of the ohmic metal layer 510 and the barrier layer 400, and between the horizontal portion of the Schottky metal layer 520 and the barrier layer 400. The horizontal portions of the ohmic metal layer 510 and the Schottky metal layer 520 can help weaken the electric field spikes near the anode or cathode of the Schottky diode.

[0080] In one embodiment, the width of the horizontal portion of the ohmic metal layer 510 is greater than the width of the vertical portion of the ohmic metal layer 510.

[0081] In one embodiment, the width of the horizontal portion of the Schottky metal layer 520 is greater than the width of the vertical portion of the Schottky metal layer 520.

[0082] In this embodiment, the source metal layer 801 of the gallium nitride-based HEMT device is connected to its source electrode, the drain metal layer 803 of the gallium nitride-based HEMT device is connected to its drain electrode, and the gate metal layer 802 of the gallium nitride-based HEMT device is connected to its gate electrode.

[0083] In step S30, an etching region 101 is formed by etching a specified region on the back surface of the substrate layer 100.

[0084] In this embodiment, as shown in combination with Figure 6 shown, the etching region 101 penetrates into the back capping layer 200.

[0085] In one embodiment, the etching region 101 covers at least the region between the ohmic metal layer 510 and the Schottky metal layer 520.

[0086] In step S40, in combination with Figure 7 as shown, a back gate layer 700 that is not in contact with the substrate layer 100 is formed in the etching region 101.

[0087] In this embodiment, the position of the back gate layer 700 is staggered from the positions of the ohmic metal layer 510 and the Schottky metal layer 520.

[0088] In one embodiment, if the back gate layer 700 is disposed between the ohmic metal layer 510 and the Schottky metal layer 520, then the ohmic metal layer 510 and the Schottky metal layer 520 are symmetrically disposed with respect to the central axis where the back gate layer 700 is located.

[0089] The embodiment of the present application further provides a chip, and the chip includes a gallium nitride-based HEMT device as described in any one of the above.

[0090] In one embodiment, the chip includes a gallium nitride-based HEMT device prepared by the preparation method as described in any one of the above.

[0091] In this embodiment, in combination with Figure 2 as shown, the Schottky diode is prepared based on the channel layer 300, the barrier layer 400, and the back capping layer 200 of the gallium nitride-based HEMT device. In practical applications, the back gate layer 700 is also disposed on both sides of the back capping layer 700 of the gallium nitride-based HEMT device.

[0092] In one embodiment, the channel layer 300, the barrier layer 400, and the back capping layer 200 below the ohmic metal layer 510 and the Schottky metal layer 520 are isolated from the channel layer 300, the barrier layer 400, and the back capping layer 200 below the source metal layer 801, the gate metal layer 802, and the drain metal layer 803 of the gallium nitride-based HEMT device by an isolation material layer.

[0093] The back capping layer 700 of the gallium nitride-based HEMT device in this embodiment can be used to access the back gate voltage to adjust the two-dimensional electron gas channel inside the device. For example, if the back gate voltage is greater than 0V, the two-dimensional electron gas is enhanced, and the forward conduction resistance can be reduced. If the back gate voltage is less than 0V, the two-dimensional electron gas is weakened, and the breakdown voltage of the device under reverse bias can be increased.

[0094] The beneficial effects of the embodiments of the present application compared with the prior art are as follows: By integrating a Schottky diode in a gallium nitride-based HEMT device, the Schottky diode is composed of a channel layer, a barrier layer, a back capping layer, and a back gate layer. The back gate layer is disposed on the back surface of the back capping layer and does not contact the substrate layer that is also located on the back surface of the back capping layer. By dynamically controlling the voltage of the back gate layer, a lower forward conduction resistance and a higher device breakdown voltage are achieved, improving the performance of the device in the non-clamped inductive load switching process test, and solving the technical problem in the related art that due to the lack of a corresponding parasitic diode in the GaN-based HEMT, the backflow current generated in the UIS test oscillates inside the device, causing devastating damage to the device.

[0095] Those skilled in the art can clearly understand that for the convenience and brevity of description, only the above division of each doping region is used as an example. In practical applications, the above functional regions can be allocated to different doping regions according to needs, that is, the internal structure of the device is divided into different doping regions to complete all or part of the functions described above.

[0096] The doping regions in the embodiments can be integrated into one functional region, or each doping region can exist physically alone, or two or more doping regions can be integrated into one functional region. The above integrated functional regions can be realized by the same doping ions or by a combination of multiple doping ions. In addition, the specific names of the doping regions are only for the convenience of mutual distinction and do not limit the protection scope of the present application. The specific working process of the doping region in the preparation method of the above device can refer to the corresponding process in the foregoing method embodiments and will not be elaborated here.

[0097] The above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A gallium nitride-based HEMT device, in which a Schottky diode is integrated, characterized in that, The Schottky diode includes: A channel layer; A barrier layer disposed on the front surface of the channel layer; A back cap layer disposed on the back surface of the channel layer; An ohmic metal layer disposed on the first side of the barrier layer; A Schottky metal layer disposed on the second side of the barrier layer; wherein, the ohmic metal layer is connected to the drain electrode of the gallium nitride-based HEMT device, and the Schottky metal layer is connected to the source electrode of the gallium nitride-based HEMT device; A substrate layer disposed on the back surface of the back cap layer; A back gate layer disposed on the back surface of the back cap layer, and the back gate layer is not in contact with the substrate layer.

2. The gallium nitride-based HEMT device according to claim 1, wherein The ohmic metal layer and the Schottky metal layer are in an L-shaped structure.

3. The gallium nitride-based HEMT device according to claim 2, wherein The Schottky diode further includes a passivation layer, and the passivation layer is disposed between the horizontal portion of the ohmic metal layer and the barrier layer, and between the horizontal portion of the Schottky metal layer and the barrier layer; The vertical portion of the ohmic metal layer is disposed on the surface of the first side of the barrier layer, and the vertical portion of the Schottky metal layer is disposed on the surface of the second side of the barrier layer.

4. The gallium nitride-based HEMT device according to claim 2, wherein, The width of the horizontal portion of the ohmic metal layer is greater than the width of the vertical portion of the ohmic metal layer.

5. The gallium nitride-based HEMT device according to claim 2, wherein, The width of the horizontal portion of the Schottky metal layer is greater than the width of the vertical portion of the Schottky metal layer.

6. The gallium nitride-based HEMT device according to any one of claims 1-5, characterized in that, The barrier layer is AlGaN, and the channel layer is gallium nitride.

7. The gallium nitride-based HEMT device according to any one of claims 1-5, characterized in that, The back cap layer is P-type gallium nitride.

8. The gallium nitride-based HEMT device according to any one of claims 1-5, characterized in that The Schottky diode is disposed below the gate electrode, drain electrode or source electrode of the gallium nitride-based HEMT device, and the Schottky metal layer is connected to the source electrode of the gallium nitride-based HEMT device, and the ohmic metal layer is connected to the drain electrode of the gallium nitride-based HEMT device.

9. A preparation method of a gallium nitride-based HEMT device, characterized in that, Including: Forming a back cap layer, a channel layer and a barrier layer stacked on the front surface of the substrate layer; Forming an ohmic metal layer on the first side of the barrier layer and forming a Schottky metal layer on the second side of the barrier layer; wherein, the ohmic metal layer is connected to the drain electrode of the gallium nitride-based HEMT device, and the Schottky metal layer is connected to the source electrode of the gallium nitride-based HEMT device; Etching a designated area on the back surface of the substrate layer to form an etching area; wherein, the etching area penetrates into the back cap layer; Forming a back gate layer that is not in contact with the substrate layer in the etching area; wherein, the position of the back gate layer is staggered with the positions of the ohmic metal layer and the Schottky metal layer.

10. A chip, characterized in that, The chip includes a gallium nitride-based HEMT device according to any one of claims 1-8; or the chip includes a gallium nitride-based HEMT device prepared by the preparation method according to claim 9.

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