A topology circuit combining an operational amplifier and a comparator

Abstract

The application provides a topology circuit combining an operational amplifier and a comparator, which comprises an active load, two single-ended conversion circuits, a differential current conversion circuit, a differential input circuit and a driving circuit; wherein when a first differential input voltage of the differential input circuit is less than a second differential input voltage, four MOS transistors of the active load are in a first connection mode to realize the function of the operational amplifier; when the first differential input voltage of the differential input circuit is greater than the second differential input voltage, the four MOS transistors of the active load are in a second connection mode to realize the function of the comparator. The operational amplifier and the comparator circuit structure are shared on the circuit topology, the positive voltage drop and the reverse blocking voltage mechanism become related mechanisms, the advantages of keeping the positive voltage drop as low as possible are maintained, the reverse blocking point is not far away from the origin too much, the purpose of reducing the reverse current and avoiding oscillation during the reverse blocking period is achieved.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of circuits, in particular to a topology circuit combining an operational amplifier and a comparator. BACKGROUND

[0002] In the field of ideal diode and load switch related controller chips, in order to obtain low voltage drop and fast turn-off characteristics, an operational amplifier and a comparator are often involved. The operational amplifier obtains a low on-voltage drop through negative feedback to reduce power loss on the path. The comparator compares the voltage drop between the two ends of the path, and rapidly turns off some external devices when a certain voltage difference is met, to avoid reverse current flow. For example, in the field of ideal diode controllers, as shown in FIG. 1, an operational amplifier forms a closed loop with an external power NMOS, and obtains a low on-voltage drop Vos_ea, for example, 30 mV, under the action of negative feedback. Since the voltage drop from the input source end to the output out end is very low, the power loss on the path is effectively reduced when a large current flows through the external power NMOS. The comparator compares the voltage drop from the input source end to the output out end, and rapidly turns off the external power NMOS when a certain voltage difference Vos_com, for example, 30 mV, is met, to avoid reverse current flow. Figure 1

[0003] At present, the forward on-voltage drop Vos_ea is obtained by negative feedback of the operational amplifier, and the monitoring turn-off voltage Vos_com is realized by the comparator. In order to realize as low on-voltage drop as possible, Vos_ea is often reduced, but the reduction of Vos_ea is limited by the mismatch factor of manufacturing process. Reducing the central expected value of Vos_ea will lead to a too low voltage drop under negative feedback (combined with the mismatch introduced by manufacturing), and the negative feedback will fail. The monitoring voltage Vos_com of the comparator is also affected by the mismatch caused by manufacturing. From the distribution, there is a possibility that the forward on-voltage drop distribution function Vos_ea(X) and the reverse turn-off distribution function Vos_com(Y) have an overlapping region. Once the overlap occurs, it means that the forward on-voltage drop of some chips is not higher than the reverse turn-off point, which will cause the technical problem of oscillation. Therefore, how to avoid oscillation in the use process of the operational amplifier and the comparator has become a technical problem that cannot be ignored. SUMMARY

[0004] ​Therefore, the application aims to provide a topology circuit combining an operational amplifier and a comparator, which shares the circuit structure of the operational amplifier and the comparator on the circuit topology, and makes the forward voltage drop and the reverse blocking voltage mechanism become relevant mechanisms, so as to keep the forward voltage drop as low as possible, and make the reverse blocking point not too far from the origin, thereby reducing the reverse current and avoiding oscillation during the reverse blocking.

[0005] The application provides a topology circuit combining an operational amplifier and a comparator, which comprises an active load including four MOS transistors, two single-ended conversion circuits, a differential current conversion circuit, a differential input circuit and a driving circuit.

[0006] The first end of the first single-ended conversion circuit is electrically connected with the first end of the active load, the second end of the first single-ended conversion circuit is electrically connected with the second end of the active load, the third end of the first single-ended conversion circuit is electrically connected with the third end of the second single-ended conversion circuit, and the fourth end of the first single-ended conversion circuit is electrically connected with the fourth end of the second single-ended conversion circuit and the second end of the driving circuit.

[0007] The first end of the second single-ended conversion circuit is electrically connected with the third end of the active load, the second end of the second single-ended conversion circuit is electrically connected with the fourth end of the active load, and the fifth end of the second single-ended conversion circuit is electrically connected with the first end of the driving circuit.

[0008] The fifth end of the active load is electrically connected with the first end of the differential current conversion circuit, the sixth end of the active load is electrically connected with the second end of the differential current conversion circuit, the third end of the differential current conversion circuit is electrically connected with the first end of the differential input circuit, the fourth end of the differential current conversion circuit is electrically connected with the second end of the differential input circuit, the third end of the differential input circuit is electrically connected with the second end of the driving circuit, and a power supply is electrically connected with the seventh end of the active load.

[0009] When the first differential input voltage of the differential input circuit is less than the second differential input voltage, the four MOS transistors of the active load are in a first connection mode to realize the function of the operational amplifier.

[0010] When the first differential input voltage of the differential input circuit is greater than the second differential input voltage, the four MOS transistors of the active load are in a second connection mode to realize the function of the comparator.

[0011] In a possible implementation, the active load comprises a first MOS transistor, a second MOS transistor, a third MOS transistor and a fourth MOS transistor.

[0012] The source of the first MOS is electrically connected with the source of the second MOS, the gate of the first MOS is electrically connected with the drain of the second MOS and the drain of the first MOS, wherein the source of the first MOS is the first end of the active load, the gate of the first MOS is the second end of the active load, and the drain of the first MOS is the fifth end of the active load.

[0013] The source of the third MOS is electrically connected with the source of the fourth MOS, the drain of the third MOS is electrically connected with the drain of the fourth MOS and the gate of the fourth MOS, wherein the source of the fourth MOS is the third end of the active load, the gate of the fourth MOS is the fourth end of the active load, and the drain of the third MOS is the sixth end of the active load.

[0014] The gate of the second MOS is electrically connected with the drain of the third MOS, and the source of the second MOS is electrically connected with the gate of the third MOS.

[0015] In a possible implementation, the first connection mode is:

[0016] The gate of the first MOS is electrically connected with the gate of the second MOS and the drain of the first MOS, the second MOS is electrically connected with the gate of the third MOS, and the third MOS is electrically connected with the gate of the fourth MOS.

[0017] In a possible implementation, the second connection mode is:

[0018] The gate of the second MOS is electrically connected with the gate of the fourth MOS, the drain of the fourth MOS is electrically connected with the gate of the fourth MOS, and the first MOS and the third MOS are turned off.

[0019] In a possible implementation, the first single-ended conversion circuit includes two MOSs; wherein,

[0020] The drain of the fifth MOS is electrically connected with the drain and the gate of the sixth MOS, wherein the source of the fifth MOS is the first end of the first single-ended conversion circuit, the gate of the fifth MOS is the second end of the first single-ended conversion circuit, the gate of the sixth MOS is the third end of the first single-ended conversion circuit, and the source of the sixth MOS is the fourth end of the first single-ended conversion circuit.

[0021] In a possible implementation, the second single-ended conversion circuit comprises two MOS transistors; wherein,

[0022] The drain of the seventh MOS transistor is electrically connected with the drain of the eighth MOS transistor, wherein the source of the seventh MOS transistor is the first end of the second single-ended conversion circuit, the gate of the seventh MOS transistor is the second end of the second single-ended conversion circuit, the gate of the eighth MOS transistor is the third end of the second single-ended conversion circuit, the source of the eighth MOS transistor is the fourth end of the second single-ended conversion circuit, and the drain of the eighth MOS transistor is the fifth end of the second single-ended conversion circuit.

[0023] In a possible implementation, the differential current conversion circuit comprises four MOS transistors and a first bias current source; wherein,

[0024] The gate of the ninth MOS transistor is electrically connected with the gate of the tenth MOS transistor, the drain of the tenth MOS transistor and the first bias current source, the source of the ninth MOS transistor is electrically connected with the source of the tenth MOS transistor, the gate of the eleventh MOS transistor is electrically connected with the gate of the twelfth MOS transistor, the drain of the eleventh MOS transistor and the first bias current source, and the source of the eleventh MOS transistor is electrically connected with the source of the twelfth MOS transistor;

[0025] The drain of the tenth MOS transistor is the first end of the differential current conversion circuit, the drain of the twelfth MOS transistor is the second end of the differential current conversion circuit, the source of the tenth MOS transistor is the third end of the differential current conversion circuit, and the source of the twelfth MOS transistor is the fourth end of the differential current conversion circuit.

[0026] In a possible implementation, the differential input circuit comprises two MOS transistors; wherein,

[0027] The drain of the thirteenth MOS transistor is electrically connected with the drain of the fourteenth MOS transistor and the gate of the fourteenth MOS transistor, wherein the source of the thirteenth MOS transistor is the first end of the differential input circuit, the source of the fourteenth MOS transistor is the second end of the differential input circuit, and the gate of the fourteenth MOS transistor is the third end of the differential input circuit.

[0028] In a possible implementation, the driving circuit comprises two MOS transistors and a second bias current source; wherein,

[0029] The drain of the fifteenth MOS transistor is electrically connected with the second bias current source and the gate of the sixteenth MOS transistor respectively, the source of the sixteenth MOS transistor is electrically connected with the source of the fifteenth MOS transistor, wherein the gate of the fifteenth MOS transistor is the first end of the driving circuit, and the source of the fifteenth MOS transistor is the second end of the driving circuit.

[0030] In a possible implementation, a ratio between a width-length ratio of the first MOS transistor, a width-length ratio of the second MOS transistor, a width-length ratio of the third MOS transistor, and a width-length ratio of the fourth MOS transistor is 3.5:2.5:2:3.

[0031] The embodiment of the present application provides a topology circuit of an operational amplifier combined with a comparator, the topology circuit comprises an active load including four MOS transistors, two single-ended conversion circuits, a differential current conversion circuit, a differential input circuit, and a driving circuit; the active load includes four MOS transistors, and each single-ended conversion circuit includes two MOS transistors; wherein a first end of the first single-ended conversion circuit is electrically connected with a first end of the active load, a second end of the first single-ended conversion circuit is electrically connected with a second end of the active load, a third end of the first single-ended conversion circuit is electrically connected with a third end of the second single-ended conversion circuit, a fourth end of the first single-ended conversion circuit is electrically connected with a fourth end of the second single-ended conversion circuit and a second end of the driving circuit; a first end of the second single-ended conversion circuit is electrically connected with a third end of the active load, a second end of the second single-ended conversion circuit is electrically connected with a fourth end of the active load, a fifth end of the second single-ended conversion circuit is electrically connected with a first end of the driving circuit; a seventh end of the active load is electrically connected with a power supply; when a first differential input voltage of the differential input circuit is less than a second differential input voltage, the four MOS transistors of the active load are in a first connection mode to realize the function of the operational amplifier; when the first differential input voltage of the differential input circuit is greater than the second differential input voltage, the four MOS transistors of the active load are in a second connection mode to realize the function of the comparator. By sharing the circuit structure of the operational amplifier and the comparator on the circuit topology, the related mechanisms of the positive voltage drop and the reverse blocking voltage mechanism are realized, the advantage that the positive voltage drop is as low as possible is maintained, and the reverse blocking point does not deviate from the origin too much, so that the purpose of reducing the reverse current and avoiding oscillation during the reverse blocking period is achieved.

[0032] In order to make the above objectives, characteristics and advantages of the present application more apparent, clear and easy to understand, the following preferred embodiments are specifically described below with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced as follows. It should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0034] Figure 1 The control circuit diagram of the external power NMOS for the operational amplifier and the comparator;

[0035] Figure 2 The structure schematic diagram of the topology circuit of the operational amplifier and the comparator provided by the embodiments of the present application;

[0036] Figure 3 The structure schematic diagram of the topology circuit of the operational amplifier and the comparator provided by the embodiments of the present application;

[0037] Figure 4 The structure schematic diagram of the topology circuit of the operational amplifier and the comparator provided by the embodiments of the present application;

[0038] Figure 5 The structure schematic diagram of the topology circuit of the operational amplifier and the comparator provided by the embodiments of the present application;

[0039] Figure 6 The comparison diagram of the topology circuit of the operational amplifier and the comparator provided by the embodiments of the present application and the independent design of the operational amplifier and the comparator.

[0040] Figure: 200-topology circuit of the operational amplifier and the comparator; 210-active load; 211-first MOS tube; 212-second MOS tube; 213-third MOS tube; 214-fourth MOS tube; 220-first single-ended conversion circuit; 221-fifth MOS tube; 222-sixth MOS tube; 230-second single-ended conversion circuit; 231-seventh MOS tube; 232-eighth MOS tube; 240-differential current conversion circuit; 241-ninth MOS tube; 242-tenth MOS tube; 243-eleventh MOS tube; 244-twelfth MOS tube; 245-first bias current source; 250-differential input circuit; 251-thirteenth MOS tube; 252-fourteenth MOS tube; 260-driving circuit; 261-fifteenth MOS tube; 262-sixteenth MOS tube; 263-second bias current source. DETAILED DESCRIPTION

[0041] In order to make the purposes, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of description and illustration, and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn according to the actual proportions. The flowcharts used in the present application show the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowcharts can not be implemented in sequence, and the steps without logical context relationship can be reversed in sequence or implemented simultaneously. In addition, one or more other operations can be added to the flowcharts or one or more operations can be removed from the flowcharts by those skilled in the art under the guidance of the content of the present application.

[0042] In addition, the described embodiments are only some of the embodiments of the present application, not all the embodiments. The components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0043] In order to enable those skilled in the art to use the content of the present application, the following implementation is given in combination with a specific application scenario "circuit for fusing operational amplifier and comparator", and those skilled in the art can apply the general principles defined herein to other embodiments and application scenarios without departing from the spirit and scope of the present application.

[0044] The circuit described in the embodiments of the present application can be applied to any scenario that needs to fuse an operational amplifier and a comparator, and the embodiments of the present application do not limit the specific application scenario. Any solution using the topology circuit provided by the embodiments of the present application for combining an operational amplifier and a comparator is within the scope of protection of the present application.

[0045] First, the application scenarios applicable to the present application are introduced. The present application can be applied to the field of circuit.

[0046] It is found through research that, at the present stage, the positive conduction voltage drop Vos_ea is obtained by negative feedback of the operational amplifier, and the monitoring off voltage Vos_com is realized by the comparator. In order to realize as low a conduction voltage drop as possible, Vos_ea is often reduced, but the reduction of Vos_ea is limited by the mismatch factor of the manufacturing process. Blindly reducing the central expected value of Vos_ea will cause the voltage drop value to be too low under negative feedback (combined with the mismatch introduced by manufacturing), and the negative feedback will fail. The monitoring voltage Vos_com of the comparator is also affected by the mismatch caused by manufacturing. From the distribution, there is a possibility that the positive conduction voltage drop distribution function Vos_ea(X) and the reverse off distribution function Vos_com(Y) have an overlapping region. Once the overlap occurs, it means that the positive conduction voltage drop of some chips is not higher than the reverse off point, which will cause the technical problem of oscillation. Therefore, how to avoid oscillation during the use of the operational amplifier and the comparator has become a technical problem that cannot be underestimated.

[0047] There are two contradictions in the prior art. One is that there is a contradiction between reducing the positive voltage drop Vos_ea(X) and the mismatch of the manufacturing process, so that the designer cannot blindly reduce the positive voltage drop. The second is that the reverse off voltage Vos_com(Y) must be far away from the distribution of the positive voltage drop Vos_ea(X) to avoid oscillation, so that the designer cannot blindly arrange the reverse off voltage close to the positive voltage drop. Therefore, in order to reduce the positive voltage drop Vos_ea(X) while maintaining the stability of the controller, the common technology in the industry is to symmetrically arrange the above two distributions around the center 0 axis. However, although this design strategy is safe enough, it has a defect that the reverse off point Vos_com(Y) is arranged on the left side of the 0 axis, which means that the controller must be turned off when out is significantly greater than source by a certain value, which inevitably brings the problem of reverse current. Therefore, in the design, a differential circuit structure is used to assist in reducing the reverse current problem at the moment of turning off. As can be seen from the above analysis, the fundamental reason for the occurrence of reverse current is that, in order to maintain a low voltage drop and the stability of the controller, the off detection voltage must be far away from the region of the positive voltage drop, and it is very easy to enter the left side of the 0 axis. Combined with the mismatch of the comparator, the distribution center μos_com of Vos_com(Y) is arranged on the left side of the 0 axis by a lot. Considering the transmission delay of the comparator, the occurrence of reverse current is almost inevitable.

[0048] Based on this, the embodiment of the present application provides a topology circuit combined with an operational amplifier and a comparator. The operational amplifier and the comparator circuit structure are shared on the circuit topology, the positive voltage drop and the reverse off voltage mechanism become related mechanisms, the positive voltage drop is kept as low as possible, and the reverse off point is not far away from the origin. Therefore, the purpose of reducing the reverse current and avoiding oscillation during the reverse off period is achieved.

[0049] Referring to Figure 2 , Figure 2 Figure 1 is a schematic diagram of a topology circuit provided by an embodiment of the present application, which combines an operational amplifier and a comparator. Figure 2 As shown in Figure 1, the topology circuit 200 provided by the embodiment of the present application includes an active load 210 including four MOS transistors, two single-ended conversion circuits each including two MOS transistors, a differential current conversion circuit 240, a differential input circuit 250, and a driving circuit 260.

[0050] Specifically, a first end of the first single-ended conversion circuit 220 is electrically connected to a first end of the active load 210, a second end of the first single-ended conversion circuit 220 is electrically connected to a second end of the active load 210, a third end of the first single-ended conversion circuit 220 is electrically connected to a third end of the second single-ended conversion circuit 230, and a fourth end of the first single-ended conversion circuit 220 is electrically connected to a fourth end of the second single-ended conversion circuit 230 and a second end of the driving circuit 260.

[0051] For example, the first single-ended conversion circuit 220 is configured to convert a differential signal into a single-ended signal.

[0052] For example, the first single-ended conversion circuit 220 includes two MOS transistors.

[0053] For example, the active load 210 includes four MOS transistors. Due to the existence of the forward voltage drop of the operational amplifier and the reverse blocking voltage drop of the comparator, the active load 210 needs to be specially designed, and the width-length ratio of the four MOS transistors needs to be designed.

[0054] Specifically, a first end of the first single-ended conversion circuit 220 is electrically connected to a first end of the active load 210, a second end of the first single-ended conversion circuit 220 is electrically connected to a second end of the active load 210, a third end of the first single-ended conversion circuit 220 is electrically connected to a third end of the second single-ended conversion circuit 230, and a fourth end of the first single-ended conversion circuit 220 is electrically connected to a fourth end of the second single-ended conversion circuit 230 and a second end of the driving circuit 260.

[0055] Specifically, a first end of the first single-ended conversion circuit 220 is electrically connected to a first end of the active load 210, a second end of the first single-ended conversion circuit 220 is electrically connected to a second end of the active load 210, a third end of the first single-ended conversion circuit 220 is electrically connected to a third end of the second single-ended conversion circuit 230, and a fourth end of the first single-ended conversion circuit 220 is electrically connected to a fourth end of the second single-ended conversion circuit 230 and a second end of the driving circuit 260.

[0056] For example, the second single-ended conversion circuit 230 is configured to convert a differential signal into a single-ended signal.

[0057] For example, the second single-ended conversion circuit 230 includes two MOS transistors.

[0058] For example, the first end of the second single-ended conversion circuit 230 is electrically connected with the third end of the active load 210, the second end of the second single-ended conversion circuit 230 is electrically connected with the fourth end of the active load 210, and the fifth end of the second single-ended conversion circuit 230 is electrically connected with the first end of the driving circuit 260.

[0059] Specifically, the fifth end of the active load 210 is electrically connected with the first end of the differential current conversion circuit 240, the sixth end of the active load 210 is electrically connected with the second end of the differential current conversion circuit 240, the third end of the differential current conversion circuit 240 is electrically connected with the first end of the differential input circuit 250, the fourth end of the differential current conversion circuit 240 is electrically connected with the second end of the differential input circuit 250, the third end of the differential input circuit 250 is electrically connected with the second end of the driving circuit 260, and the power supply is electrically connected with the seventh end of the active load 210.

[0060] Here, the power supply can be 3V, 5V, etc., and the type of the power supply is not limited here.

[0061] For example, the differential current conversion circuit 240 is used to convert the tail current input by the differential input circuit 250 into differential current.

[0062] For example, the differential input circuit 250 is used for differential input, and the differential input using PMOS allows the common-mode level to be 0. The symmetric differential input caused by the differential input has very low mismatch under the premise that the width-length ratio is sufficient.

[0063] For example, the fifth end of the active load 210 is electrically connected with the first end of the differential current conversion circuit 240, the sixth end of the active load 210 is electrically connected with the second end of the differential current conversion circuit 240, the third end of the differential current conversion circuit 240 is electrically connected with the first end of the differential input circuit 250, the fourth end of the differential current conversion circuit 240 is electrically connected with the second end of the differential input circuit 250, the third end of the differential input circuit 250 is electrically connected with the second end of the driving circuit 260, and the power supply is electrically connected with the seventh end of the active load 210.

[0064] Specifically, when the first differential input voltage of the differential input circuit 250 is less than the second differential input voltage, the four MOS tubes of the active load 210 are in a first connection mode to realize the function of an operational amplifier; when the first differential input voltage of the differential input circuit 250 is greater than the second differential input voltage, the four MOS tubes of the active load 210 are in a second connection mode to realize the function of a comparator.

[0065] The working principle of the circuit is as follows:

[0066] In the topology circuit combining an operational amplifier and a comparator, when the first differential input voltage of the differential input circuit 250 is lower than the second differential input voltage, the current flowing from the first end of the differential current conversion circuit 240 through the fifth end of the active load 210 is higher than the current flowing from the second end of the differential current conversion circuit 240 through the sixth end of the active load 210, the four MOS transistors inside the active load 210 are in the first connection mode so that the topology circuit is equivalent to an operational amplifier; when the first differential input voltage of the differential input circuit 250 is higher than the second differential input voltage, the current flowing from the first end of the differential current conversion circuit 240 through the sixth end of the active load 210 is higher. When the current flowing through the fifth terminal of the active load 210 is lower than the current flowing through the sixth terminal of the active load 210 from the second terminal of the differential current conversion circuit 240, the four MOS transistors within the active load 210 are in the second connection mode, so that the topological circuit is equivalent to a comparator. This allows the forward voltage drop generated by the operational amplifier and the reverse shutdown voltage generated by the comparator to become a correlation mechanism. Even if there is an overlapping area between the two, there is no oscillation. This not only maintains the advantage of keeping the forward voltage drop as low as possible, but also prevents the reverse shutdown point from moving too far away from the zero axis, thereby achieving the purpose of reducing reverse current and avoiding oscillation during the reverse shutdown period.

[0067] For further information, see Figure 3 , Figure 3 This is a second structural diagram of a topological circuit combining an operational amplifier and a comparator provided in an embodiment of the present application. Figure 3 As shown, the active load 210 includes a first MOS transistor 211, a second MOS transistor 212, a third MOS transistor 213, and a fourth MOS transistor 214; the first single-ended conversion circuit 220 includes a fifth MOS transistor 221 and a sixth MOS transistor 222; the second single-ended conversion circuit 230 includes a seventh MOS transistor 231 and an eighth MOS transistor 232; the differential current conversion circuit 240 includes a ninth MOS transistor 241, a tenth MOS transistor 242, an eleventh MOS transistor 243, a twelfth MOS transistor 244, and a first bias current source 245; the differential input circuit 250 includes a thirteenth MOS transistor 251 and a fourteenth MOS transistor 252; and the drive circuit 260 includes a fifteenth MOS transistor 261, a sixteenth MOS transistor 262, and a second bias current source 263.

[0068] Specifically, the source of the first MOS transistor 211 is electrically connected with the source of the second MOS transistor 212, the gate of the first MOS transistor 211 is electrically connected with the drain of the second MOS transistor 212 and the drain of the first MOS transistor 211, wherein the source of the first MOS transistor 211 is the first end of the active load 210, the gate of the first MOS transistor 211 is the second end of the active load 210, and the drain of the first MOS transistor 211 is the fifth end of the active load 210; the source of the third MOS transistor 213 is electrically connected with the source of the fourth MOS transistor 214, the drain of the third MOS transistor 213 is electrically connected with the drain of the fourth MOS transistor 214 and the gate of the fourth MOS transistor 214, wherein the source of the fourth MOS transistor 214 is the third end of the active load 210, the gate of the fourth MOS transistor 214 is the fourth end of the active load 210, and the drain of the third MOS transistor 213 is the sixth end of the active load 210; the gate of the second MOS transistor 212 is electrically connected with the drain of the third MOS transistor 213, and the source of the second MOS transistor 212 is electrically connected with the gate of the third MOS transistor 213.

[0069] For example, the gate of the second MOS transistor 212 is electrically connected with the drain of the third MOS transistor 213, so that the current of the gate of the second MOS transistor 212 is consistent with the current of the drain of the third MOS transistor 213, and the gate of the third MOS transistor 213 is electrically connected with the drain of the second MOS transistor 212, so that the current of the gate of the third MOS transistor 213 is consistent with the current of the drain of the second MOS transistor 212.

[0070] For example, the type of the MOS transistor can be NPN type, and the type of the MOS transistor is not limited herein.

[0071] Specifically, the drain of the fifth MOS transistor 221 is electrically connected with the drain and the gate of the sixth MOS transistor 222, wherein the source of the fifth MOS transistor 221 is the first end of the first single-ended conversion circuit 220, the gate of the fifth MOS transistor 221 is the second end of the first single-ended conversion circuit 220, the gate of the sixth MOS transistor 222 is the third end of the first single-ended conversion circuit 220, and the source of the sixth MOS transistor 222 is the fourth end of the first single-ended conversion circuit 220.

[0072] For example, the drain of the fifth MOS transistor 221 is electrically connected with the drain and the gate of the sixth MOS transistor 222, wherein the source of the fifth MOS transistor 221 is electrically connected with the source of the first MOS transistor 211, the gate of the fifth MOS transistor 221 is electrically connected with the gate of the first MOS transistor 211, the gate of the sixth MOS transistor 222 is electrically connected with the gate of the eighth MOS transistor 232, and the source of the sixth MOS transistor 222 is electrically connected with the source of the eighth MOS transistor 232.

[0073] Specifically, the drain of the seventh MOS transistor 231 is electrically connected with the drain of the eighth MOS transistor 232, wherein the source of the seventh MOS transistor 231 is the first end of the second single-ended conversion circuit 230, the gate of the seventh MOS transistor 231 is the second end of the second single-ended conversion circuit 230, the gate of the eighth MOS transistor 232 is the third end of the second single-ended conversion circuit 230, the source of the eighth MOS transistor 232 is the fourth end of the second single-ended conversion circuit 230, and the drain of the eighth MOS transistor 232 is the fifth end of the second single-ended conversion circuit 230.

[0074] Specifically, the drain of the seventh MOS transistor 231 is electrically connected with the drain of the eighth MOS transistor 232, the source of the seventh MOS transistor 231 is electrically connected with the source of the fourth MOS transistor 214, the gate of the seventh MOS transistor 231 is electrically connected with the gate of the fourth MOS transistor 214, the gate of the eighth MOS transistor 232 is electrically connected with the gate of the sixth MOS transistor 222, and the drain of the eighth MOS transistor 232 is electrically connected with the gate of the fifteenth MOS transistor 261.

[0075] Specifically, the gate of the ninth MOS transistor 241 is electrically connected with the gate of the tenth MOS transistor 242, the drain of the tenth MOS transistor 242 and the first bias current source 245, the source of the ninth MOS transistor 241 is electrically connected with the source of the tenth MOS transistor 242, the gate of the eleventh MOS transistor 243 is electrically connected with the gate of the twelfth MOS transistor 244, the drain of the eleventh MOS transistor 243 and the first bias current source 245, and the source of the eleventh MOS transistor 243 is electrically connected with the source of the twelfth MOS transistor 244; wherein the drain of the tenth MOS transistor 242 is the first end of the differential current conversion circuit 240, the drain of the twelfth MOS transistor 244 is the second end of the differential current conversion circuit 240, the source of the tenth MOS transistor 242 is the third end of the differential current conversion circuit 240, and the source of the twelfth MOS transistor 244 is the fourth end of the differential current conversion circuit 240.

[0076] For example, the gate of the ninth MOS 241 is electrically connected with the gate of the tenth MOS 242, the drain of the tenth MOS 242 and the first bias current source 245, the source of the ninth MOS 241 is electrically connected with the source of the tenth MOS 242, the gate of the eleventh MOS 243 is electrically connected with the gate of the twelfth MOS 244, the drain of the eleventh MOS 243 and the first bias current source 245, the source of the eleventh MOS 243 is electrically connected with the source of the twelfth MOS 244, the drain of the ninth MOS 241 is electrically connected with the drain of the second MOS 212, the drain of the eleventh MOS 243 is electrically connected with the drain of the third MOS 213, the source of the tenth MOS 242 is electrically connected with the source of the thirteenth MOS 251, and the source of the twelfth MOS 244 is electrically connected with the source of the fourteenth MOS 252.

[0077] Specifically, the drain of the thirteenth MOS 251 is electrically connected with the drain of the fourteenth MOS 252 and the gate of the fourteenth MOS 252, wherein the source of the thirteenth MOS 251 is the first end of the differential input circuit 250, the source of the fourteenth MOS 252 is the second end of the differential input circuit 250, and the gate of the fourteenth MOS 252 is the third end of the differential input circuit 250.

[0078] For example, the drain of the thirteenth MOS 251 is electrically connected with the drain of the fourteenth MOS 252 and the gate of the fourteenth MOS 252, the source of the thirteenth MOS 251 is electrically connected with the source of the tenth MOS 242, the source of the fourteenth MOS 252 is electrically connected with the source of the twelfth MOS 244, and the gate of the eleventh MOS 243 is electrically connected with the source of the fifteenth MOS 261.

[0079] Here, the thirteenth MOS 251 and the fourteenth MOS 252 form a differential input, and the differential input using PMOS allows the common mode level to be 0, and the differential mode current controlled by the first differential input voltage (out) and the second differential input voltage (source) is embodied as the drain current of the ninth MOS 241 and the twelfth MOS 244. The differential input is a symmetrical differential input, and the mismatch caused by the differential input is very low on the premise that the width-length ratio is sufficient.

[0080] Specifically, the drain of the fifteenth MOS 261 is electrically connected with the second bias current source 263 and the gate of the sixteenth MOS 262 respectively, and the source of the sixteenth MOS 262 is electrically connected with the source of the fifteenth MOS 261, wherein the gate of the fifteenth MOS 261 is the first end of the drive circuit 260, and the source of the fifteenth MOS 261 is the second end of the drive circuit 260.

[0081] For example, the drain of the fifteenth MOS transistor 261 is electrically connected with the second bias current source 263 and the gate of the sixteenth MOS transistor 262 respectively, the source of the sixteenth MOS transistor 262 is electrically connected with the source of the fifteenth MOS transistor 261, and the gate of the fifteenth MOS transistor 261 is electrically connected with the gate of the eighth MOS transistor 232.

[0082] Here, the fifteenth MOS transistor 261 is designed by the sixteenth MOS transistor 262, which can generate a pull-down current or a driving current of at most Ip at the gate end. When in the operational amplifier state, the fifteenth MOS transistor 261 is controlled in the loop of the high-gain operational amplifier, and the size of the drain current of the fifteenth MOS transistor 261 is adjusted, and then the level of the gate relative to the second differential input voltage source is adjusted. The voltage difference of the gate relative to the second differential input voltage source is the driving voltage of the external power sixteenth MOS transistor 262, so as to ensure that the second differential input voltage always maintains a high positive voltage drop relative to the first differential input voltage under a certain range of current load. When external factors change, causing the first differential input voltage out to rise relative to the second differential input voltage source, the gate voltage of the fifteenth MOS transistor 261 will gradually rise, and the charge injected by the constant current source on the gate will be discharged. However, if the first differential input voltage out exceeds the reverse blocking voltage of the second differential input voltage source, the gate of the fifteenth MOS transistor 261 will be lifted to the maximum value, and the charge on the gate will be discharged with the maximum capacity, and the power sixteenth MOS transistor 262 will be turned off.

[0083] Here, the sixteenth MOS transistor 262 can be an NMOS transistor.

[0084] For example, the gate of the thirteenth MOS transistor is electrically connected with the drain of the sixteenth MOS transistor.

[0085] Further, please refer to Figure 4 , Figure 4 The topology circuit provided by the embodiment of the present application, which is combined with the operational amplifier and the comparator, is equivalent to the structural schematic diagram of the operational amplifier. As shown in Figure 4 , the first MOS transistor 211 and the second MOS transistor 212 are connected in parallel to form a first target MOS transistor, the third MOS transistor 213 and the fourth MOS transistor 214 are connected in parallel to form a second target MOS transistor, the gate of the first target MOS transistor is electrically connected with the gate of the second target MOS transistor and the drain of the first target MOS transistor respectively, and the second target MOS transistor is electrically connected with the gate of the third MOS transistor 213.

[0086] For example, a first target MOS transistor obtained by connecting the first MOS transistor 211 and the second MOS transistor 212 in parallel, and a second target MOS transistor obtained by connecting the third MOS transistor 213 and the fourth MOS transistor 214 in parallel, the gate of the first target MOS transistor is electrically connected to the gate of the second target MOS transistor and the drain of the first target MOS transistor, respectively, the second target MOS transistor is electrically connected to the gate of the third MOS transistor 213, the source of the first target MOS transistor is electrically connected to the source of the first MOS transistor 211, the drain of the first target MOS transistor is electrically connected to the drain of the seventh MOS transistor 231, the source of the second target MOS transistor is electrically connected to the source of the third MOS transistor 213, and the drain of the second target MOS transistor is electrically connected to the drain of the tenth MOS transistor 242 and the gate of the third MOS transistor 213.

[0087] Here, when the first differential input voltage of the differential input circuit 250 is lower than the second differential input voltage by ΔV, the current flowing through the first target MOS transistor is slightly greater than the current flowing through the second target MOS transistor (with a slightly smaller width-to-length ratio). The first target MOS transistor is composed of MA5 and MA4, and the second target MOS transistor is composed of MB5 and MB4. The width-to-length ratios of the above four MOS transistors satisfy the following relationship:

[0088]

[0089] W / L M1 is the width-to-length ratio of the first MOS transistor 211, W / L M2 is the width-to-length ratio of the second MOS transistor 212, W / L M3 is the width-to-length ratio of the third MOS transistor 213, W / L M4 is the width-to-length ratio of the fourth MOS transistor 214) = 1 + δ, where δ is a coefficient slightly greater than 0, ensuring that the active load 210 has a slight asymmetry and constructing a certain equivalent input offset, that is, the forward voltage drop Vos_ea. Therefore, the negative feedback stability condition is met. When the state is stable, the first differential input voltage out is lower than the second differential input voltage source by ΔV. This ΔV is designed as the forward voltage drop Vos_ea, so that the topology circuit can function as an operational amplifier.

[0090] In a specific embodiment, the drain of the fifth MOS transistor 221 is electrically connected to the drain of the sixth MOS transistor 222 and the gate, the source of the fifth MOS transistor 221 is electrically connected to the source of the first MOS transistor 211, the gate of the fifth MOS transistor 221 is electrically connected to the gate of the first MOS transistor 211, the gate of the sixth MOS transistor 222 is electrically connected to the gate of the eighth MOS transistor 232, the source of the sixth MOS transistor 222 is electrically connected to the source of the eighth MOS transistor 232, the drain of the seventh MOS transistor 231 is electrically connected to the drain of the eighth MOS transistor 232, the source of the seventh MOS transistor 231 is electrically connected to the source of the fourth MOS transistor 214, the gate of the seventh MOS transistor 231 is electrically connected to the gate of the fourth MOS transistor 214, the gate of the eighth MOS transistor 232 is electrically connected to the gate of the sixth MOS transistor 222, the drain of the eighth MOS transistor 232 is electrically connected to the gate of the fifteenth MOS transistor 261. The gate of the ninth MOS transistor 241 is electrically connected to the gate of the tenth MOS transistor 242, the drain of the tenth MOS transistor 242 and the first bias current source 245, the source of the ninth MOS transistor 241 is electrically connected to the source of the tenth MOS transistor 242, the gate of the eleventh MOS transistor 243 is electrically connected to the gate of the twelfth MOS transistor 244, the drain of the eleventh MOS transistor 243 and the first bias current source 245, the source of the eleventh MOS transistor 243 is electrically connected to the source of the twelfth MOS transistor 244, the drain of the ninth MOS transistor 241 is electrically connected to the drain of the second MOS transistor 212, the drain of the eleventh MOS transistor 243 is electrically connected to the drain of the third MOS transistor 213, the source of the tenth MOS transistor 242 is electrically connected to the source of the thirteenth MOS transistor 251, the source of the twelfth MOS transistor 244 is electrically connected to the source of the fourteenth MOS transistor 252. The drain of the thirteenth MOS transistor 251 is electrically connected to the drain of the fourteenth MOS transistor 252 and the gate of the fourteenth MOS transistor 252, the source of the thirteenth MOS transistor is electrically connected to the source of the tenth MOS transistor 242, the source of the fourteenth MOS transistor 252 is electrically connected to the source of the twelfth MOS transistor 244, the gate of the eleventh MOS transistor 243 is electrically connected to the source of the fifteenth MOS transistor 261. The drain of the fifteenth MOS transistor 261 is electrically connected to the second bias current source 263 and the gate of the sixteenth MOS transistor 262 respectively, the source of the sixteenth MOS transistor 262 is electrically connected to the source of the fifteenth MOS transistor 261, the gate of the fifteenth MOS transistor 261 is electrically connected to the gate of the eighth MOS transistor 232.When the first differential input voltage out of the differential input circuit 250 is lower than the second differential input voltage source by ΔV, the four MOS tubes in the active load 210 are in the first connection mode, the first MOS tube 211 and the second MOS tube 212 are connected in parallel to form a first target MOS tube, the third MOS tube 213 and the fourth MOS tube 214 are connected in parallel to form a second target MOS tube, the gate of the first target MOS tube is electrically connected with the gate of the second target MOS tube and the drain of the first target MOS tube, the gate of the second target MOS tube is electrically connected with the gate of the third MOS tube 213, the source of the first target MOS tube is electrically connected with the source of the first MOS tube 211, the drain of the first target MOS tube is electrically connected with the drain of the seventh MOS tube 231, the source of the second target MOS tube is electrically connected with the source of the third MOS tube 213, and the drain of the second target MOS tube is electrically connected with the drain of the tenth MOS tube 242 and the gate of the third MOS tube 213. The function of the operational amplifier is realized, and when the sixteenth MOS tube flows a large current, the power loss on the path is effectively reduced.

[0091] Further, please refer to Figure 5 , Figure 5 The operational amplifier combined with the comparator provided by the embodiment of the present application is equivalent to the structural diagram of the comparator. As shown in Figure 5 , the gate of the second MOS tube 212 is electrically connected with the gate of the fourth MOS tube 214, the drain of the fourth MOS tube 214 is electrically connected with the gate of the fourth MOS tube 214, and the first MOS tube 211 and the third MOS tube 213 are cut off.

[0092] For example, the first MOS tube 211 and the third MOS tube 213 are cut off, the gate of the second MOS tube 212 is electrically connected with the gate of the fourth MOS tube 214, the drain of the fourth MOS tube 214 is electrically connected with the gate of the fourth MOS tube 214, the source of the second MOS tube 212 is electrically connected with the source of the first MOS tube 211, the drain of the second MOS tube 212 is electrically connected with the drain of the seventh MOS tube 231, the source of the second MOS tube 212 is electrically connected with the source of the third MOS tube 213, and the drain of the second MOS tube 212 is electrically connected with the drain of the tenth MOS tube 242 and the gate of the third MOS tube 213.

[0093] Here, when the first differential input voltage of the differential input circuit 250 is higher than the second differential input voltage by ΔV, the current flowing through the second MOS tube 212 is slightly smaller than the current flowing through the fourth MOS tube 214 (the width-length ratio is slightly larger), and the first MOS tube 211 and the third MOS tube 213 are cut off. The width-length ratios of the above four groups of MOS satisfy the following relationship:

[0094]

[0095] wherein p is a coefficient slightly greater than 0, ensuring that there is a weak asymmetry in the active load 210, and a certain equivalent input offset is constructed, i.e. the reverse off voltage Vos_com, so only when the first differential input voltage side of the differential input circuit 250 is higher than the second differential input voltage side by ΔV, the current flowing through the side of the second MOS tube 212 (with a slightly smaller width-length ratio) is slightly smaller than the current flowing through the side of the fourth MOS tube 214 (with a slightly larger width-length ratio), under this condition, the positive feedback triggering condition can be met, and under this triggering condition, the ΔV is designed as the reverse off voltage Vos_com, so that the topology circuit serves as a comparator.

[0096] For example, the ratio between the width-length ratio of the first MOS tube 211, the width-length ratio of the second MOS tube 212, the width-length ratio of the third MOS tube 213 and the width-length ratio of the fourth MOS tube 214 is 3.5:2.5:2:3.

[0097] When p = δ, the ratio between the width-length ratio of the first MOS tube 211, the width-length ratio of the second MOS tube 212, the width-length ratio of the third MOS tube 213 and the width-length ratio of the fourth MOS tube 214 is 3.5:2.5:2:3, and here the ratio between the width-length ratio of the first MOS tube 211, the width-length ratio of the second MOS tube 212, the width-length ratio of the third MOS tube 213 and the width-length ratio of the fourth MOS tube 214 is not limited to 3.5:2.5:2:3, and the width-length ratio can be set according to actual needs

[0098] In specific embodiments, the drain of the fifth MOS transistor 221 is electrically connected to the drain and the gate of the sixth MOS transistor 222, the source of the fifth MOS transistor 221 is electrically connected to the source of the first MOS transistor 211, the gate of the fifth MOS transistor 221 is electrically connected to the gate of the first MOS transistor 211, the gate of the sixth MOS transistor 222 is electrically connected to the gate of the eighth MOS transistor 232, the source of the sixth MOS transistor 222 is electrically connected to the source of the eighth MOS transistor 232, the drain of the seventh MOS transistor 231 is electrically connected to the drain of the eighth MOS transistor 232, the source of the seventh MOS transistor 231 is electrically connected to the source of the fourth MOS transistor 214, the gate of the seventh MOS transistor 231 is electrically connected to the gate of the fourth MOS transistor 214, the gate of the eighth MOS transistor 232 is electrically connected to the gate of the sixth MOS transistor 222, the drain of the eighth MOS transistor 232 is electrically connected to the gate of the fifteenth MOS transistor 261. The gate of the ninth MOS transistor 241 is electrically connected to the gate, the drain of the tenth MOS transistor 242 and the first bias current source 245, the source of the ninth MOS transistor 241 is electrically connected to the source of the tenth MOS transistor 242, the gate of the eleventh MOS transistor 243 is electrically connected to the gate, the drain of the eleventh MOS transistor 243 and the first bias current source 245, the source of the eleventh MOS transistor 243 is electrically connected to the source of the twelfth MOS transistor 244, the drain of the ninth MOS transistor 241 is electrically connected to the drain of the second MOS transistor 212, the drain of the eleventh MOS transistor 243 is electrically connected to the drain of the third MOS transistor 213, the source of the tenth MOS transistor 242 is electrically connected to the source of the thirteenth MOS transistor 251, the source of the twelfth MOS transistor 244 is electrically connected to the source of the fourteenth MOS transistor 252. The drain of the thirteenth MOS transistor 251 is electrically connected to the drain and the gate of the fourteenth MOS transistor 252, the source of the thirteenth MOS transistor is electrically connected to the source of the tenth MOS transistor 242, the source of the fourteenth MOS transistor 252 is electrically connected to the source of the twelfth MOS transistor 244, the gate of the eleventh MOS transistor 243 is electrically connected to the source of the fifteenth MOS transistor 261. The drain of the fifteenth MOS transistor 261 is electrically connected to the second bias current source 263 and the gate of the sixteenth MOS transistor 262, respectively, the source of the sixteenth MOS transistor 262 is electrically connected to the source of the fifteenth MOS transistor 261, the gate of the fifteenth MOS transistor 261 is electrically connected to the gate of the eighth MOS transistor 232.When the first differential input voltage out of the differential input circuit 250 is higher than the second differential input voltage source by ΔV, the four MOS tubes in the active load 210 are in the second connection mode, the first MOS tube 211 and the third MOS tube 213 are turned off, the gate of the second MOS tube 212 is electrically connected with the gate of the fourth MOS tube 214, the drain of the fourth MOS tube 214 is electrically connected with the gate of the fourth MOS tube 214, the source of the second MOS tube 212 is electrically connected with the source of the first MOS tube 211, the drain of the second MOS tube 212 is electrically connected with the drain of the seventh MOS tube 231, the source of the second MOS tube 212 is electrically connected with the source of the third MOS tube 213, the drain of the second MOS tube 212 is electrically connected with the drain of the tenth MOS tube 242 and the gate of the third MOS tube 213, but if the first differential input voltage out exceeds the second differential input voltage source by the reverse blocking voltage, at this time the gate of the fifteenth MOS tube 261 will be lifted to the maximum value, to charge the gate with the maximum capacity, to close the power sixteenth MOS tube 262.

[0099] Further, please refer to Figure 6 , Figure 6 The comparison chart of the operation amplifier provided by the embodiment of the present application and the independent design of the operation amplifier and the comparator. As shown in Figure 6As shown, in the present scheme, a circuit topology is used, combining the feedback of the operational amplifier and the comparison function of the comparator together. During the forward conduction period, the circuit topology exhibits the negative feedback characteristics of the operational amplifier, and the voltage drop across the feedback depends on the ratio of the number of transistors in the internal active load, and the forward conduction voltage drop value corresponds to Vos_ea. When external factors cause the power NMOS (the sixteenth MOS tube) to be closed, the circuit topology behaves as a comparator, and the comparison trigger level of the comparator also depends on the ratio of the number of transistors in the internal active load, and the reverse off voltage corresponds to Vos_com. Since both are determined by the same active load, the forward voltage drop distribution function Vos_ea(X) and the reverse off distribution function Vos_com(Y) satisfy the function correlation. The forward voltage drop distribution function Vos_ea(X) and the reverse off distribution function Vos_com(Y) satisfy the function correlation, which can be described using the protection gap function G(X-Y). The meaning of this function is to statistically analyze the sample function of the specific Vos_ea-Vos_com of each chip. By comparing the independent design of the operational amplifier and the comparator with the scheme of combining the two in the present scheme, G1(X-Y) and G2(X-Y) under the two designs perform as follows: In order to reduce the forward voltage drop, the left figure will reduce the distribution center μos_ea of the forward conduction voltage drop, and at the same time, considering that the protection gap between the reverse off cannot be too low in distribution (μ-3σ>0) otherwise it will cause oscillation, so the distribution center μos_com of the reverse off voltage must be reduced (even into negative value), so that the center expectation μ of G1(X-Y) is high enough, and the distribution is guaranteed to be mostly positive, but it will cause the distribution of the reverse off voltage to be too low (even mostly negative), and significant reverse current will appear. In the present scheme, as shown in the right figure, the center expectation μ of the protection gap function G2(X-Y) is the same as that of the left figure. Since the amplification and comparison links are related in the circuit topology, the gap difference also depends on the number ratio of the MOS tubes, so theoretically the dispersion is very small, so the forward voltage drop μos_ea is also reduced. Since the distribution of G2(X-Y) is very concentrated, the designer can make the distribution center μos_com of the reverse off voltage close to the forward voltage drop μos_ea, so that the center expectation μ of G2(X-Y) is relatively low, and there is no need to worry about the distribution of G2(X-Y) being less than 0. Because the distribution of the reverse off voltage can be relatively high (even mostly positive), the reverse current is not significant.

[0100] The embodiment of the application provides a kind of topology circuit for operational amplifier and comparator combination, the topology circuit includes active load including four MOS tubes, two single-ended conversion circuits each including 2 MOS tubes, differential current conversion circuit, differential input circuit and driving circuit;Wherein, the first end of the first single-ended conversion circuit is electrically connected with the first end of active load, the second end of the first single-ended conversion circuit is electrically connected with the second end of active load, the third end of the first single-ended conversion circuit is electrically connected with the third end of the second single-ended conversion circuit, the fourth end of the first single-ended conversion circuit is electrically connected with the fourth end of the second single-ended conversion circuit and the second end of driving circuit;The first end of the second single-ended conversion circuit is electrically connected with the third end of active load, the second end of the second single-ended conversion circuit is electrically connected with the fourth end of active load, the five ends of the second single-ended conversion circuit are electrically connected with the first end of driving circuit;The fifth end of active load is electrically connected with the first end of differential current conversion circuit, the sixth end of active load is electrically connected with the second end of differential current conversion circuit, the third end of differential current conversion circuit is electrically connected with the first end of differential input circuit, the fourth end of differential current conversion circuit is electrically connected with the second end of differential input circuit, the third end of differential input circuit is electrically connected with the second end of driving circuit;When the first differential input voltage of the differential input circuit is less than the second differential input voltage, the four MOS tubes of the active load are in the first connection mode to realize the function of operational amplifier;When the first differential input voltage of the differential input circuit is greater than the second differential input voltage, the four MOS tubes of the active load are in the second connection mode to realize the function of comparator.By making operational amplifier and comparator circuit structure share in circuit topology, the positive voltage drop and reverse blocking voltage mechanism become related mechanisms, which realizes the advantages of keeping the positive voltage drop as low as possible and keeping the reverse blocking point from deviating from the origin too much, to reduce reverse current and avoid oscillation during reverse blocking period.The skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the above-described system, device and unit can refer to the corresponding process in the foregoing method embodiments, which will not be described here.

[0101] In several embodiments provided in the application, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division, and there can be another division manner in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some communication interfaces, devices or units, which can be electrical, mechanical or other forms.

[0102] The units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, i.e. may be located in one place, or may be distributed on multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0103] In addition, the functional units in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit.

[0104] If the functions are realized in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer readable storage medium executable by a processor. Based on this understanding, the technical solutions of the present application or the part of the present application that essentially contributes to the prior art or the part of the technical solutions can be embodied in the form of a software product, which is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The foregoing storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, and various program code storage media.

[0105] Finally, it should be noted that: the above-described embodiments are only specific embodiments of the present application, used to illustrate the technical solutions of the present application, and not to limit them, the protection scope of the present application is not limited thereto, although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand: any person skilled in the art within the technical scope disclosed by the present application, they can still modify or easily think of changes to the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part of the technical features; and these modifications, changes or replacements do not make the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and all should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A topology circuit combining an operational amplifier and a comparator, characterized by, The topology circuit comprises an active load comprising four MOS transistors, two single-ended conversion circuits, a differential current conversion circuit, a differential input circuit and a driving circuit; the active load comprises four MOS transistors, each single-ended conversion circuit comprises two MOS transistors; wherein, a first end of the first single-ended conversion circuit is electrically connected to a first end of the active load, a second end of the first single-ended conversion circuit is electrically connected to a second end of the active load, a third end of the first single-ended conversion circuit is electrically connected to a third end of the second single-ended conversion circuit, and a fourth end of the first single-ended conversion circuit is electrically connected to a fourth end of the second single-ended conversion circuit and a second end of the driving circuit; a first end of the second single-ended conversion circuit is electrically connected to a third end of the active load, a second end of the second single-ended conversion circuit is electrically connected to a fourth end of the active load, and a fifth end of the second single-ended conversion circuit is electrically connected to a first end of the driving circuit; a fifth end of the active load is electrically connected to a first end of the differential current conversion circuit, a sixth end of the active load is electrically connected to a second end of the differential current conversion circuit, a third end of the differential current conversion circuit is electrically connected to a first end of the differential input circuit, a fourth end of the differential current conversion circuit is electrically connected to a second end of the differential input circuit, a third end of the differential input circuit is electrically connected to a second end of the driving circuit; and a power supply is electrically connected to a seventh end of the active load; when a first differential input voltage of the differential input circuit is less than a second differential input voltage, the four MOS transistors of the active load are in a first connection mode to realize the function of an operational amplifier; when the first differential input voltage of the differential input circuit is greater than the second differential input voltage, the four MOS transistors of the active load are in a second connection mode to realize the function of a comparator.

2. The topology circuit of claim 1, wherein, The active load comprises a first MOS transistor, a second MOS transistor, a third MOS transistor and a fourth MOS transistor; wherein, a source of the first MOS transistor is electrically connected to a source of the second MOS transistor, a gate of the first MOS transistor is electrically connected to a drain of the second MOS transistor and a drain of the first MOS transistor, wherein the source of the first MOS transistor serves as a first end of the active load, the gate of the first MOS transistor serves as a second end of the active load, and the drain of the first MOS transistor serves as a fifth end of the active load; a source of the third MOS transistor is electrically connected to a source of the fourth MOS transistor, a drain of the third MOS transistor is electrically connected to a drain of the fourth MOS transistor and a gate of the fourth MOS transistor, wherein the source of the fourth MOS transistor serves as a third end of the active load, the gate of the fourth MOS transistor serves as a fourth end of the active load, and the drain of the third MOS transistor serves as a sixth end of the active load; a gate of the second MOS transistor is electrically connected to a drain of the third MOS transistor, and a source of the second MOS transistor is electrically connected to a gate of the third MOS transistor.

3. The topology circuit of claim 2, wherein, The first connection mode is: The first target MOS tube is connected in parallel with the second MOS tube, the second target MOS tube is connected in parallel with the third MOS tube and the fourth MOS tube, the gate of the first target MOS tube is electrically connected with the gate of the second target MOS tube and the drain of the first target MOS tube respectively, and the gate of the second target MOS tube is electrically connected with the gate of the third MOS tube.

4. The topology circuit of claim 2, wherein, The second connection mode is: The gate of the second MOS tube is electrically connected with the gate of the fourth MOS tube, the drain of the fourth MOS tube is electrically connected with the gate of the fourth MOS tube, and the first MOS tube and the third MOS tube are cut off.

5. The topology circuit of claim 1, wherein, The first single-ended conversion circuit includes two MOS tubes; wherein, The drain of the fifth MOS tube is electrically connected with the drain and the gate of the sixth MOS tube, wherein the source of the fifth MOS tube is the first end of the first single-ended conversion circuit, the gate of the fifth MOS tube is the second end of the first single-ended conversion circuit, the gate of the sixth MOS tube is the third end of the first single-ended conversion circuit, and the source of the sixth MOS tube is the fourth end of the first single-ended conversion circuit.

6. The topological circuit of claim 1, wherein, The second single-ended conversion circuit includes two MOS tubes; wherein, The drain of the seventh MOS tube is electrically connected with the drain of the eighth MOS tube, wherein the source of the seventh MOS tube is the first end of the second single-ended conversion circuit, the gate of the seventh MOS tube is the second end of the second single-ended conversion circuit, the gate of the eighth MOS tube is the third end of the second single-ended conversion circuit, the source of the eighth MOS tube is the fourth end of the second single-ended conversion circuit, and the drain of the eighth MOS tube is the fifth end of the second single-ended conversion circuit.

7. The topological circuit of claim 1, wherein, The differential current conversion circuit includes four MOS tubes and a first bias current source; wherein, The gate of the ninth MOS tube is electrically connected with the gate of the tenth MOS tube, the drain of the tenth MOS tube and the first bias current source, the source of the ninth MOS tube is electrically connected with the source of the tenth MOS tube, the gate of the eleventh MOS tube is electrically connected with the gate of the twelfth MOS tube, the drain of the eleventh MOS tube and the first bias current source, and the source of the eleventh MOS tube is electrically connected with the source of the twelfth MOS tube; Wherein, the drain of the tenth MOS tube is the first end of the differential current conversion circuit, the drain of the twelfth MOS tube is the second end of the differential current conversion circuit, the source of the tenth MOS tube is the third end of the differential current conversion circuit, and the source of the twelfth MOS tube is the fourth end of the differential current conversion circuit.

8. The topological circuit of claim 1, wherein, The differential input circuit includes two MOS tubes; wherein, The drain of the thirteenth MOS tube is electrically connected with the drain of the fourteenth MOS tube and the gate of the fourteenth MOS tube, wherein the source of the thirteenth MOS tube is the first end of the differential input circuit, the source of the fourteenth MOS tube is the second end of the differential input circuit, and the gate of the fourteenth MOS tube is the third end of the differential input circuit.

9. The topological circuit of claim 1, wherein, The driving circuit comprises two MOS tubes and a second bias current source; wherein, the drain of the fifteenth MOS tube is electrically connected with the second bias current source and the gate of the sixteenth MOS tube, the source of the sixteenth MOS tube is electrically connected with the source of the fifteenth MOS tube, wherein the gate of the fifteenth MOS tube is the first end of the driving circuit, and the source of the fifteenth MOS tube is the second end of the driving circuit.

10. The topology circuit of claim 2, wherein, The ratio between the width-length ratio of the first MOS tube, the width-length ratio of the second MOS tube, the width-length ratio of the third MOS tube and the width-length ratio of the fourth MOS tube is 3.5:2.5:2:3.

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