An FPGA supporting associated signal for associated wiring

Abstract

The application discloses an FPGA supporting associated signal wiring, and relates to the field of FPGA.The FPGA further comprises an associated wiring module on the basis of an initial architecture, a plurality of communicable paths in an associated path group in the associated wiring module are simultaneously enabled under the action of a same control signal, and a plurality of associated signals contained in a same associated signal group correspond to a plurality of communicable paths in an associated path group connected with the associated wiring module respectively when a wiring operation is performed; a plurality of communicable paths included in the associated path group are simultaneously enabled through a control signal corresponding to the associated path group, and the plurality of associated signals of the same associated signal group are transmitted to corresponding output ends of the associated path group through the plurality of communicable paths. Thus, the linkage wiring of the plurality of associated signals can be realized, and the wiring of each associated signal does not need to be configured respectively, so that the wiring difficulty of the associated signal group is reduced, and the wiring efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of FPGA, and particularly relates to an FPGA supporting associated signal associated wiring. BACKGROUND

[0002] FPGA (Field Programmable Gate Array) is a product further developed on the basis of PAL (Programmable Array Logic), GAL (Generic Array Logic) and other programmable devices, which solves the shortage of custom circuit and overcomes the limitation of the number of gate circuits of the original programmable device.

[0003] The FPGA internally contains a large number of resource modules such as CLB, BRAM, DSP, IOB, each of which corresponds to one or more interconnection modules INT surrounding the outside of the resource module, and the input port and the output port of the resource module can be connected to the input end or the output end of the corresponding interconnection module INT by configuring the function sub-module FUNC inside the resource module. Different interconnection modules INT are connected through wiring resources of different lengths, so that the interconnection between the ports of two resource modules can be realized by using the series connection of one or more interconnection modules INT, so as to realize the signal connection required by the user design netlist.

[0004] An interconnection module INT provides a plurality of input ends and a plurality of output ends, and the interconnection module INT internally contains a plurality of wiring switch boxes, each of which is generally realized by a multiplexer MUX. All the input ends of the interconnection module INT are generally divided into groups connected to the input ends of different wiring switch boxes, and the output ends of the wiring switch boxes are connected to an output end of the interconnection module INT. The selection signals of the wiring switch boxes are controlled by the corresponding number of configuration bits, and the configuration bits of the wiring switch boxes are independent of each other and do not interfere with each other. By changing the content of the configuration bits of the wiring switch boxes through code stream download, the signals of different input ends of the interconnection module INT can be selected to be transmitted to the output end for output.

[0005] For example Figure 1Taking an interconnect module INT containing 16 input terminals I0, I1...I15 and 4 output terminals, and internally containing 4 wiring switch boxes labeled MUX0, MUX1, MUX2, and MUX3, as an example. The 16 input terminals are divided into four groups and connected to the input terminals of the 4 wiring switch boxes. The output terminals of the 4 wiring switch boxes are connected to the 4 output terminals Y0, Y1, Y2, and Y3 of the interconnect module INT, respectively. Thus, the interconnect module INT forms a total of 16 connectable paths. Each of the 4 wiring switch boxes has 2 configuration bits, therefore, an interconnect module INT requires a total of 8 configuration bits {S0, S1, S2, S3, S4, S5, S6, S7}. By downloading and changing the contents of the configuration bits, the on / off state of the 16 connectable paths can be controlled, thereby transmitting the required input signals to the required outputs.

[0006] However, in reality, an INT interconnect module often contains a large number of input and output terminals, unlike... Figure 1 The examples given are only a small number. Furthermore, for the sake of wiring flexibility and routing success rate, it won't be like... Figure 1 For example, instead of a single input terminal connecting to a single wiring switch box, an input terminal might be assigned to different groups, connecting to multiple wiring switch boxes. This maximizes the possibility of each input terminal connecting to every output terminal, ensuring a connectable path between each input-output group. The grouping and allocation of input terminals in the Interconnect Module (INT) are determined by architectural requirements. Generally, software simulation experiments are needed to determine which wiring switch boxes an input terminal can connect to. Therefore, in practical applications, the number of connectable paths formed between different inputs and outputs within the INT is enormous. For example, a typical INT can have up to 4000 connectable paths. The selection of each connectable path is independent and does not interfere with each other. While this provides high wiring flexibility, each connectable path requires independent configuration of its on / off state, increasing the difficulty and complexity of wiring. Summary of the Invention

[0007] To address the aforementioned problems and technical requirements, the inventors have proposed an FPGA that supports associated routing of associated signals. The technical solution of this invention is as follows:

[0008] An FPGA that supports associated routing of associated signals, the FPGA further includes an associated routing module in addition to an initial architecture, the initial architecture including a resource module and an interconnect module;

[0009] The associated wiring module provides multiple input terminals and multiple output terminals to the outside. Internally, the associated wiring module forms multiple connectable paths between different input terminals and output terminals. The associated wiring module selects the internal connectable paths according to the acquired control signals.

[0010] The connectable paths in the associated wiring module form at least one associated path group, and the multiple connectable paths in the same associated path group are simultaneously enabled under the action of the same control signal, and the multiple connectable paths in the same associated path group connect different input terminals and different output terminals.

[0011] In the wiring operation, one associated signal group is connected to the input terminal of the associated wiring module, the multiple associated signals in the same associated signal group correspond to the multiple connectable paths in one associated path group respectively, the associated wiring module is controlled by the control signal corresponding to the associated path group, the multiple connectable paths in the associated path group are simultaneously enabled, and the multiple associated signals in the same associated signal group are transmitted to the corresponding output terminal of the associated path group by the multiple connectable paths.

[0012] The further technical scheme is that the connectable paths in one associated wiring module form multiple different associated path groups, the multiple connectable paths in the same associated path group are simultaneously enabled under the action of the same control signal, and the connectable paths in different associated path groups are enabled under the action of different control signals.

[0013] The further technical scheme is that, in the wiring operation, multiple associated signal groups are connected to the input terminal of the same associated wiring module, the associated signals in each associated signal group correspond to the multiple connectable paths in one associated path group respectively, and the different associated signal groups correspond to different associated path groups in the associated wiring module.

[0014] The associated wiring module transmits the associated signals of different associated signal groups to the output terminal of the associated wiring module through different associated path groups when different control signals are obtained.

[0015] The further technical scheme is that, in the wiring operation, one associated signal group is connected to the input terminal of the same associated wiring module, the associated signals in each associated signal group correspond to multiple associated path groups respectively, one input terminal connected by each associated signal in the associated signal group is connected to the same output terminal through the multiple connectable paths in the multiple associated path groups, and the path delays of the multiple connectable paths in the multiple associated path groups connected between the same group of input terminals and output terminals are different.

[0016] The further technical scheme is that, in the wiring operation, one associated signal group is connected to the input terminal of the same associated wiring module, the associated signals in each associated signal group correspond to multiple associated path groups respectively, and one input terminal connected by at least one associated signal in the associated signal group is connected to multiple different output terminals through the multiple connectable paths in the multiple associated path groups.

[0017] The further technical solution is that the time delay difference of the path time delay of the connectable paths in different associated path groups in the associated wiring module does not exceed a predetermined threshold value, or the time delay difference of the path time delay of at least two connectable paths exceeds the predetermined threshold value.

[0018] The further technical solution is that at least one output end of the associated wiring module is merged with the output end of the interconnection module and connected to the same input port of the corresponding resource module, and the output end of the associated wiring module and the output end of the interconnection module are not simultaneously connected to the input port of the resource module.

[0019] And / or, at least one input end of the associated wiring module is simultaneously connected to the same output port of the corresponding resource module with the input end of the interconnection module.

[0020] The further technical solution is that the associated wiring module is arranged near the resource module transmitting the associated signal group inside the FPGA.

[0021] The further technical solution is that at least one input end of the associated wiring module is connected to the output end of the other associated wiring module, and / or at least one output end of the associated wiring module is connected to the input end of the other associated wiring module.

[0022] The further technical solution is that the length of the connection line between different associated wiring modules is less than the span of the clock domain or exceeds the span of the clock domain.

[0023] The further technical solution is that the connection line between different associated wiring modules is realized through a high-level metal layer.

[0024] The further technical solution is that a group of BUS signals forms an associated signal group, and the time delay difference of the path time delay of the multiple connectable paths in the same associated path group for connecting the group of BUS signals in the associated wiring module at the time of gating does not exceed a predetermined threshold value.

[0025] The further technical solution is that multiple associated wiring modules are arranged inside the FPGA, and the multiple associated wiring modules are arranged in a row and / or column structure.

[0026] The further technical solution is that the associated wiring module internally includes multiple associated switch boxes, the associated switch boxes are simultaneously controlled by the control signal of the associated wiring module, the input end of each associated switch box is connected to the multiple input ends of the associated wiring module, the output end of each associated switch box is respectively connected to an output end of the associated wiring module, and the associated wiring module forms the internal connectable paths through the associated switch boxes.

[0027] The multiple connectable paths in the same associated path group are formed by multiple different associated switch boxes, and the control signals obtained by the associated wiring module are used to control the associated switch boxes, so that the multiple connectable paths in the same associated path group are simultaneously selected.

[0028] The beneficial technical effects of the present application are:

[0029] The application discloses an FPGA supporting associated signal wiring, which is additionally provided with an associated wiring module based on an initial architecture.

[0030] The connection ports and path delays of the associated path groups in the associated wiring module can be configured as required, so that the associated signals can meet the requirements of the path and delay when the associated signals are wired in association, thereby ensuring the wiring quality. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 It is a schematic diagram of the internal structure of the interconnection module INT in the initial architecture of the conventional FPGA.

[0032] Figure 2 It is a schematic diagram of the associated wiring module implemented in an embodiment based on the initial architecture.

[0033] Figure 3 It is a schematic diagram of the associated signal group being switched to the connectable paths with different path delays by using the associated wiring module in an embodiment.

[0034] Figure 4 It is a schematic diagram of the associated signal group being switched to different output ends by using the associated wiring module in an embodiment.

[0035] Figure 5 It is a schematic diagram of the associated path group being switched by using the associated wiring module in an embodiment, so that different associated signal groups are output.

[0036] Figure 6 It is a schematic diagram of the internal structure of the associated wiring module in an embodiment, and a schematic diagram of the parallel use of the associated wiring module and the interconnection module. DETAILED DESCRIPTION

[0037] The specific embodiments of the present application are further described below with reference to the accompanying drawings.

[0038] The application discloses an FPGA supporting associated signal associated wiring, which comprises an associated wiring module on the basis of a conventional initial architecture, that is, the FPGA in the application modifies the internal hardware architecture relative to the conventional FPGA. The conventional initial architecture is the architecture introduced in the background section, which comprises a resource module and an interconnection module. The resource module comprises CLB, BRAM, DSP, IOB, etc. The interconnection module, that is, the INT module, comprises a plurality of wiring switch boxes inside and provides a plurality of input ends and a plurality of output ends outside. A plurality of communicable paths are formed between different input ends and output ends inside the interconnection module INT, and each communicable path inside the interconnection module INT is controlled by a control signal of the interconnection module INT. The control signals of any two communicable paths are different.

[0039] The associated wiring module BINT added by the application relative to the initial architecture is also arranged around the resource module. The associated wiring module BINT and the interconnection module INT in the initial architecture exist in the FPGA at the same time, and are both used for signal interconnection between the resource modules.

[0040] The associated wiring module BINT also provides a plurality of input ends and a plurality of output ends outside, and a plurality of communicable paths are formed between different input ends and output ends inside the associated wiring module BINT. The on-off of each communicable path is controlled by a control signal ctrl obtained by the associated wiring module BINT. However, unlike the conventional interconnection module INT, the communicable paths inside the associated wiring module BINT are not completely independent of each other. The communicable paths inside the associated wiring module BINT form at least one associated path group. The same associated path group comprises a plurality of communicable paths associated with each other. The inputs of the plurality of communicable paths are connected to different input ends of the associated wiring module BINT, and the outputs of the plurality of communicable paths are connected to different output ends of the associated wiring module BINT. The association between the communicable paths in the same associated path group is reflected in that the plurality of communicable paths in the same associated path group are simultaneously enabled under the action of the same control signal ctrl. That is, unlike the interconnection module INT, in which any communicable path inside can be independently turned on and off, the associated wiring module BINT has a plurality of communicable paths whose states are linked, and the communicable paths are simultaneously connected or disconnected.

[0041] For example Figure 2Take a group of associated paths formed inside the associated wiring module BINT as an example. The group of associated paths includes four associated paths line1, line2, line3 and line4, which are connected to four different input terminals I0, I4, I8 and I12 of the associated wiring module BINT respectively. The associated wiring module BINT is connected to four output terminals Y0, Y1, Y2 and Y3 of the associated wiring module BINT respectively. The on-off of the four associated paths is controlled by the control signal ctrl simultaneously. As shown in Figure 2 To show the on-off effect of the associated paths, take the example of the paths with switches. In fact, the switches may not exist actually, Figure 2 which is only for illustration.

[0042] Based on the newly added associated wiring module BINT, when performing the wiring operation on the FPGA, the associated wiring module BINT inside the group of associated paths can be used to simultaneously wire multiple associated signals in the same associated signal group. When performing the wiring operation, the associated wiring module BINT is connected to the input terminal of the associated wiring module BINT. The multiple associated signals in the same associated signal group are connected to the multiple associated paths in the associated path group respectively, that is, connected to the input terminal connected to the multiple associated paths in the associated path group. By controlling the associated wiring module BINT through the corresponding control signal of the associated path group, the multiple associated paths in the associated path group can be selected simultaneously. The multiple selected associated paths can be used to directly transmit the multiple associated signals in the same associated signal group to the corresponding output terminal of the associated path group, without configuring the associated paths of each associated signal respectively.

[0043] For example, in Figure 2 , an associated signal group Sig1[3:0] includes four associated signals Sig1[3], Sig1[2], Sig1[1] and Sig1[0] respectively. As shown in Figure 2 , the four associated signals are connected to I0, I4, I8 and I12 of the associated wiring module BINT respectively, that is, connected to the input terminal connected to the four associated paths line1, line2, line3 and line4. By controlling the control signal ctrl, the four associated paths can be controlled simultaneously. Thus, the associated signal Sig1[3] is output from Y0, the associated signal Sig1[2] is output from Y1, the associated signal Sig1[1] is output from Y2, and the associated signal Sig1[0] is output from Y3.

[0044] The associated signals in the associated signal group in the present application can have functional association or can not have functional association, can be configured by the user, and any multiple signals that need to be linked can form an associated signal group. In an embodiment, a group of BUS signals forms an associated signal group, that is, a group of BUS signals can be linked by using the method of the present application, and in this application scenario, the time delay difference of the path time delay of the multiple connectable paths in the same associated path group in the associated wiring module BINT for connecting a group of BUS signals does not exceed a predetermined threshold when gated. In this embodiment, a control signal can be used to simultaneously gate multiple connectable paths in the associated wiring module BINT with substantially equal path time delays, so as to output a group of input BUS signals through the corresponding output terminals. Not only can a group of BUS signals be linked, but also the transmission time delay requirements of a group of BUS signals can be met. Otherwise, in the conventional initial architecture, when a group of BUS signals is transmitted by using the interconnection module INT, multiple connectable paths with substantially equal path time delays need to be selected from a large number of connectable paths in the interconnection module INT and then configured with gating, which is complicated and difficult to operate.

[0045] As described above, the path time delays of the multiple connectable paths in the same associated path group when gated can be configured by the user, so that the path time delays of the multiple connectable paths have a specific relationship to meet the wiring needs of different use scenarios. For example, the time delay difference does not exceed a predetermined threshold, that is, the path time delays are considered equal within an error range, or the path time delays are sequentially increased, or other path time delay relationships, which are not limited by the present application.

[0046] On this basis, in another embodiment, an associated wiring module BINT contains multiple associated path groups, and the number of connectable paths with association in the multiple associated path groups is equal or unequal. For example, an associated wiring module BINT contains three associated path groups, two of which each contain four connectable paths with association, and the other contains three connectable paths with association. The connectable paths in different associated path groups are different, and the connectable paths in different associated path groups can be connected to the same or different input terminals. The connectable paths in different associated path groups can be connected to the same or different output terminals. Different control signals correspond to different associated path groups, and the connectable paths in different associated path groups are gated under the action of different control signals.

[0047] When the associated wiring module BINT contains multiple associated path groups, the relationship between the path delays of the multiple connectable paths in each associated path group can be as described above. The delay difference between the path delays of the connectable paths in different associated path groups in the associated wiring module does not exceed the predetermined threshold, or there are at least two connectable paths whose path delays exceed the predetermined threshold, that is, the path delays of the connectable paths in different associated path groups can also be configured to form a corresponding relationship according to actual needs. Thus, different delay requirements in the wiring process can be met.

[0048] When the associated wiring module BINT contains multiple associated path groups, in an embodiment, multiple associated path groups can be connected to the same associated signal group, that is, multiple associated signals contained in the same associated signal group correspond to multiple associated path groups respectively. Then, when the associated wiring module BINT obtains different control signals, the same associated signal group can be transmitted to the output end of the associated wiring module BINT through different associated path groups. A more applicable scenario of this embodiment is that one input end connected by each associated signal is connected to the same output end through each connectable path in multiple associated path groups, and the path delays of each connectable path in multiple associated path groups connected between the same group of input ends and output ends are different. Then, by switching different associated path groups through different control signals, the delay of the associated signal between a group of input ends and output ends can be conveniently adjusted. Another more applicable scenario of this embodiment is that there is at least one input end connected by each associated signal connected to multiple different output ends through each connectable path in multiple associated path groups, and each connectable path in each associated path group is connected between different input ends and output ends. Then, by switching different associated path groups through different control signals, the output end for outputting the associated signal can be conveniently adjusted.

[0049] For example, in an instance, based on Figure 2 Please refer to Figure 3 , an associated wiring module BINT contains two associated path groups A and B, the associated path group A contains four connectable paths written as lineA1, lineA2, lineA3, lineA4, and the path delays of the four connectable paths are all delay1, as indicated by the solid line in Figure 3 . The associated path group B contains four connectable paths written as lineB1, lineB2, lineB3, lineB4, and the path delays of the four connectable paths are all delay2, as indicated by the dotted line in Figure 3 . The delay difference between the path delay delay1 and the path delay delay2 exceeds the predetermined threshold. It should be noted that Figure 3The lengths and routes of the four connectable paths in the associated path group A are only schematic and do not represent the actual situation. The four connectable paths in the associated path group A are connected to the four input terminals I0, I4, I8, I12 and the four output terminals Y0, Y1, Y2, Y3 of the associated wiring module BINT respectively, and the four connectable paths in the associated path group B are also connected to the four input terminals I0, I4, I8, I12 and the four output terminals Y0, Y1, Y2, Y3 of the associated wiring module BINT respectively. The four associated signals Sig1[3], Sig1[2], Sig1[1] and Sig1[0] in the associated signal group Sig1[3:0] are connected to the four input terminals I0, I4, I8, I12 of the associated wiring module BINT respectively, so that when the associated wiring module BINT receives the control signal ctrlA, the four connectable paths in the associated path group A are simultaneously enabled, so that Sig1[3], Sig1[2], Sig1[1] and Sig1[0] are sequentially output from Y0, Y1, Y2 and Y3 through lineA1, lineA2, lineA3, lineA4 with a path delay of delay1. When the associated wiring module BINT receives the control signal ctrlB, the four connectable paths in the associated path group B are simultaneously enabled, so that Sig1[3], Sig1[2], Sig1[1] and Sig1[0] are sequentially output from Y0, Y1, Y2 and Y3 through lineB1, lineB2, lineB3, lineB4 with a path delay of delay2. Thus, synchronous linkage switching of the paths of the multiple associated signals can be realized, so that the time delays of the multiple associated signals can be conveniently and synchronously adjusted, and the time delays of the multiple associated signals before switching and after switching can be guaranteed to be equal, without the need for independent configuration each time.

[0050] For example, in one instance, based on Figure 2 For example, in one instance, based on Figure 4 For example, in one instance, based on Figure 4The middle solid line represents. The associated path group C contains four connectable paths written as lineC1, lineC2, lineC3, lineC4, and the four connectable paths in the associated path group C are also connected to the four input terminals I0, I4, I8, I12 of the associated wiring module BINT, but the four connectable paths are connected to the four output terminals Y1, Y0, Y2, Y3 in turn. The four associated signals Sig1[3], Sig1[2], Sig1[1] and Sig1[0] in an associated signal group Sig1[3:0] are connected to the four input terminals I0, I4, I8, I12 of the associated wiring module BINT respectively, so that when the associated wiring module BINT receives the control signal ctrlA, the four connectable paths in the associated path group A are simultaneously gated, so that Sig1[3], Sig1[2], Sig1[1] and Sig1[0] are output from Y0, Y1, Y2 and Y3 in turn through lineA1, lineA2, lineA3, lineA4. When the associated wiring module BINT receives the control signal ctrlC, the four connectable paths in the associated path group C are simultaneously gated, so that Sig1[3], Sig1[2], Sig1[1] and Sig1[0] are output from Y1, Y0, Y2 and Y3 in turn through lineC1, lineC2, lineC3, lineC4. Thus, the synchronous linkage switching of the paths of multiple associated signals can be realized to facilitate the synchronous adjustment of the output ports of the multiple associated signals.

[0051] Alternatively, in another embodiment, there can be multiple associated path groups connecting different associated signal groups, that is, there are multiple associated signal groups accessing the input terminals of the same associated wiring module BINT, and each associated signal group corresponds to an associated path group, that is, the associated signals contained in each associated signal group correspond to the multiple connectable paths in an associated path group, and different associated signal groups correspond to different associated path groups inside the associated wiring module BINT. In this scenario, the path delay relationship between different associated path groups is configured according to actual conditions. Then in this embodiment, when the associated wiring module BINT obtains different control signals, the associated signals of different associated signal groups can be transmitted to the corresponding output terminals of the associated wiring module BINT through different associated path groups.

[0052] For example, in an example, please refer to Figure 5The four connectable paths lineD1, lineD2, lineD3 and lineD4 in the associated path group D are connected to the four input terminals I0, I4, I8, I12 and the four output terminals Y0, Y1, Y2, Y3 of the associated wiring module BINT respectively. The four connectable paths lineE1, lineE2, lineE3 and lineE4 in the associated path group E are connected to the four input terminals I2, I6, I10, I14 and the four output terminals Y0, Y1, Y2, Y3 of the associated wiring module BINT respectively. The four associated signals in the associated signal group Sig1[3:0] are connected to the four input terminals I0, I4, I8, I12 of the associated wiring module BINT respectively, and the four associated signals in the associated signal group Sig2[3:0] are connected to the four input terminals I2, I6, I10, I14 of the associated wiring module BINT respectively. When the associated wiring module BINT receives the control signal ctrlD, the four connectable paths in the associated path group C are selected simultaneously, and the associated signal group Sig1[3:0] is transmitted to the output terminals of the associated wiring module BINT by the four connectable paths in the associated path group C. When the associated wiring module BINT receives the control signal ctrlE, the four connectable paths in the associated path group D are selected simultaneously, and the associated signal group Sig2[3:0] is transmitted to the output terminals of the associated wiring module BINT by the four connectable paths in the associated path group D. Thus, the different associated signal groups can be switched and output conveniently.

[0053] In either of the above cases, when the total wiring resource demand of the computing architecture is calculated, the original total number of resources of the interconnection module INT in the initial architecture remains unchanged, and the associated wiring module BINT is considered as an additional increase. At this time, the connection of the associated wiring module BINT does not affect the wiring capability of the initial architecture.

[0054] The associated wiring module BINT can be connected with the resource module in the FPGA. The associated wiring module BINT has at least one output end which is merged with the output end of the interconnection module INT and connected to the same input port of the corresponding resource module. The output end of the associated wiring module BINT and the output end of the interconnection module INT are not simultaneously connected to the input port of the resource module. One implementation is that the output of the associated wiring module BINT and the output of the interconnection module INT are connected to the same input port of the resource module through a two-way multiplexer, thereby realizing the above function. And / or, the associated wiring module BINT has at least one input end which is simultaneously connected to the same output port of the corresponding resource module through the input end of the interconnection module INT, that is, the input of the associated wiring module BINT is added to the fan-out of the resource module in the original architecture. In this way, the parallel use of the associated wiring module BINT and the interconnection module INT can be realized without affecting the integrity of the original architecture.

[0055] Please refer to Figure 6 The output end OUT0 of the resource module 1 is simultaneously connected to the input end of the interconnection module INT and the associated wiring module BINT, and OUT1, OUT2 and OUT3 are the same. The four output ends Y0, Y1, Y2 and Y3 of the associated wiring module BINT are respectively connected to the input ends IN0, IN1, IN2 and IN3 of the resource module 2 through a two-way multiplexer.

[0056] When the associated wiring module BINT can be connected with the resource module in the FPGA, the associated wiring module BINT is arranged near the resource module which transmits the associated signal group in the FPGA. That is, in the FPGA, some specific resource modules are usually used to transmit the associated signal group, and the associated wiring module BINT is built near these resource modules to reduce the transmission distance between the associated wiring module BINT and the resource module. For example, when the associated signal group is a group of BUS signals, the common resource modules for generating BUS signals include DSP, BRAM and GTH, etc. The associated wiring module BINT is arranged near these resource modules.

[0057] On the basis of the method provided in the application, a plurality of associated wiring modules BINT are arranged inside the FPGA, and the plurality of associated wiring modules are arranged in a row and / or column structure. In general, in actual applications, the associated wiring modules BINT are arranged in a column, and one or more columns of associated wiring modules BINT are arranged inside the FPGA. Each column of associated wiring modules BINT can be arranged near the resource modules that transmit the associated signal groups as described above. These resource modules are often arranged in a column structure, and the arrangement forms match. Alternatively, each column of associated wiring modules BINT can be arranged at the boundary of the FPGA, thereby being close to the IOB modules and the CMT modules. The actual arrangement position is determined as required, and the application does not limit this.

[0058] When a plurality of associated wiring modules BINT are arranged inside the FPGA, the associated wiring modules BINT can be connected to other associated wiring modules BINT in addition to being connected to the resource modules inside the FPGA. That is, the associated wiring modules have at least one input end connected to the output end of another associated wiring module, and / or the associated wiring modules have at least one output end connected to the input end of another associated wiring module.

[0059] In this embodiment, the connections between different associated wiring modules BINT have a plurality of lengths, which are less than the span of the clock domain or exceed the span of the clock domain. That is, long-distance wiring can be added between different associated wiring modules BINT, thereby simplifying the switching through the interconnection module INT when long-distance wiring is required, and reducing the time delay. The manner in which different lengths of connections are supported between different associated wiring modules BINT can be similar to the wire twisting manner of the conventional interconnection module INT. In another embodiment, the connections between different associated wiring modules BINT are implemented through high-level metal layers, thereby further reducing the time delay.

[0060] Based on the functions of the associated wiring modules BINT, this embodiment provides an implementation manner of the internal structure of the associated wiring modules BINT, which is similar to the implementation manner of the conventional interconnection module INT. The associated wiring module BINT internally includes a plurality of associated switch boxes, which can also be implemented by a plurality of selectors. The associated switch boxes are all controlled by the control signals of the associated wiring module. The input end of each associated switch box is connected to a plurality of input ends of the associated wiring module, and the output end of each associated switch box is connected to an output end of the associated wiring module. The associated wiring module BINT forms an internally connectable path through the associated switch boxes. The plurality of connectable paths in the same associated path group are formed by a plurality of different associated switch boxes, and the control signals obtained by the associated wiring module control the associated switch boxes to simultaneously select the plurality of connectable paths in the same associated path group.

[0061] For example, refer to Figure 6 One of the cases shown corresponds to Figure 1 The structure inside the interconnection module INT shown is similar to Figure 1 The embodiment shown is similar to the case shown in the figure. In this embodiment, four parallel switch boxes are used to form four associated path groups. Each associated path contains four connectable paths, which are realized by the four parallel switch boxes. The four parallel switch boxes are controlled by two configuration bits S0 and S1. When a group of configuration bits is received, the four parallel switch boxes are all actuated to realize the linkage control of an associated path group.

Claims

1. An FPGA supporting associated signals for associated routing, characterized by, The FPGA further comprises an associated wiring module on the basis of an initial architecture, the initial architecture comprising a resource module and an interconnection module; The associated wiring module provides a plurality of input terminals and a plurality of output terminals externally, a plurality of connectable paths are formed between different input terminals and output terminals internally, and the associated wiring module selects the connectable paths internally according to the control signals acquired; The connectable paths in the associated wiring module form at least one associated path group, and the plurality of connectable paths in the same associated path group are selected simultaneously under the action of the same control signal, and the plurality of connectable paths in the same associated path group connect different input terminals and different output terminals. In the wiring operation, one associated signal group is connected to the input terminals of the associated wiring module, the plurality of associated signals in the same associated signal group correspond to the plurality of connectable paths in one associated path group respectively, one control signal corresponding to the associated path group is used to control the associated wiring module and simultaneously select the plurality of connectable paths in the associated path group, and the plurality of associated signals in the same associated signal group are transmitted to the corresponding output terminals of the associated path group through the plurality of connectable paths.

2. The FPGA of claim 1, wherein, The connectable paths in one associated wiring module form a plurality of different associated path groups, and the plurality of connectable paths in the same associated path group are selected simultaneously under the action of the same control signal, and the connectable paths in different associated path groups are selected under the action of different control signals.

3. The FPGA of claim 2, wherein, In the wiring operation, a plurality of associated signal groups are connected to the input terminals of the same associated wiring module, and the associated signals in each associated signal group correspond to the plurality of connectable paths in one associated path group respectively, and different associated signal groups correspond to different associated path groups in the associated wiring module internally. The associated wiring module transmits the associated signals of different associated signal groups to the output terminals of the associated wiring module through different associated path groups when different control signals are acquired.

4. The FPGA of claim 2, wherein, In the wiring operation, one associated signal group is connected to the input terminals of the same associated wiring module, and the associated signals in each associated signal group correspond to a plurality of associated path groups respectively, one input terminal connected by each associated signal in the associated signal group is connected to the same output terminal through the plurality of connectable paths in the plurality of associated path groups, and the path delays of the plurality of connectable paths in the plurality of associated path groups connected between the same group of input terminals and output terminals are different.

5. The FPGA of claim 2, wherein, In the wiring operation, one associated signal group is connected to the input terminals of the same associated wiring module, and the associated signals in each associated signal group correspond to a plurality of associated path groups respectively, one input terminal connected by each associated signal in the associated signal group is connected to a plurality of different output terminals through the plurality of connectable paths in the plurality of associated path groups.

6. The FPGA of claim 2, wherein, The delay differences of the path delays of the connectable paths in different associated path groups in the associated wiring module are all not more than a predetermined threshold, or the delay differences of the path delays of at least two connectable paths exceed the predetermined threshold.

7. The FPGA of claim 1, wherein, at least one output of the associated routing module is merged with an output of the interconnect module and connected to a same input port of a corresponding resource module, and the output of the associated routing module and the output of the interconnect module are not simultaneously connected to the input port of the resource module; and / or, at least one input of the associated routing module is simultaneously connected to a same output port of a corresponding resource module with an input of the interconnect module.

8. The FPGA of claim 7, wherein, The associated routing module is disposed near the resource module transmitting the associated signal group inside the FPGA.

9. The FPGA of claim 1, wherein, At least one input of the associated routing module is connected to an output of another associated routing module, and / or at least one output of the associated routing module is connected to an input of another associated routing module.

10. The FPGA of claim 9, wherein, The length of the connection between different associated routing modules is less than the span of the clock domain, or exceeds the span of the clock domain.

11. The FPGA of claim 9, wherein, The connection between different associated routing modules is implemented by a high-level metal layer.

12. The FPGA of claim 1, wherein, A group of BUS signals forms an associated signal group, and the time delay difference of the path time delay of the multiple connectable paths in a same associated path group used for connecting the group of BUS signals inside the associated routing module does not exceed a predetermined threshold value in the gating time.

13. The FPGA of claim 1, wherein, A plurality of associated routing modules are disposed inside the FPGA, and the plurality of associated routing modules are arranged in a row and / or column structure.

14. The FPGA of claim 1, wherein, The associated routing module includes a plurality of associated switch boxes inside, the associated switch boxes are simultaneously controlled by the control signal of the associated routing module, the input end of each associated switch box is connected to a plurality of input ends of the associated routing module, the output end of each associated switch box is respectively connected to an output end of the associated routing module, and the associated routing module forms the internal connectable paths through the associated switch boxes; The multiple connectable paths in a same associated path group are respectively formed by multiple different associated switch boxes in the gating, the control signal obtained by the associated routing module is linked to control each associated switch box, and the multiple connectable paths in a same associated path group are simultaneously gated.

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