Phase adjustment circuit of frequency-divided clock

Abstract

The present invention provides a phase adjustment circuit for a divided-frequency clock, comprising: a phase control word generation circuit for generating a set of control words based on a reference clock and a divided-frequency clock to be adjusted; and a clock adjustment circuit, connected to the phase control word generation circuit, for adjusting the phase of the divided-frequency clock based on the control words to obtain a divided-frequency synchronous clock synchronized with the reference clock. The present invention can rapidly adjust the clock phase in real time, using half-cycles of the system clock as steps, without losing the clock sampling edge, and is applicable to integrated circuits requiring high sampling accuracy.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a phase adjustment circuit for a frequency-divided clock. Background Art

[0002] Multi-chip synchronization technology is widely used in systems such as communications, radar, and distributed data acquisition that require a certain time relationship. It is used for time coordination between multiple chips or subsystems. In the process of synchronizing the local clock signal to the system reference signal, due to the skew and jitter of the reference signal, the phase of the local clock needs to be adjusted according to the phase of the reference signal. This ensures that a certain phase relationship is maintained between the Betty clock and the reference signal, thus achieving synchronization between the clock and the reference signal.

[0003] In existing technologies, the method of synchronizing the local clock to the reference signal sysref is mainly to use the reference signal sysref to force the clock signal phase to be cleared to zero. The advantage of this method is that the circuit is simple to implement, and it can be implemented by simply designing a phase clearing circuit in the analog circuit. The disadvantage is that this solution has high requirements for the reference signal sysref, and the skew and jitter of sysref will cause the loss of the clock sampling edge. Summary of the Invention

[0004] The present invention provides a phase adjustment circuit for a frequency-divided clock, so as to solve the problem that the sampling edge of the clock is lost during the existing clock synchronization.

[0005] Based on the above-mentioned purpose, an embodiment of the present invention provides a phase adjustment circuit for a divided clock, including: a phase control word generation circuit, which is used to generate a set of control words based on a reference clock and a divided clock that needs to be adjusted; a clock adjustment circuit, which is connected to the phase control word generation circuit, and is used to adjust the phase of the divided clock according to the control word to obtain a divided synchronous clock synchronized with the reference clock.

[0006] Optionally, the phase control word generating circuit determines the phase offset value that needs to be adjusted based on the input divided clock and the reference clock, and generates a control word based on the phase offset value; the clock adjustment circuit adjusts the phase of the divided clock based on the control word to obtain the divided synchronization clock corresponding to the divided clock.

[0007] Optionally, the divided clock is 2 n The divided clock, the number of control words is 2 n+1 where n is an integer greater than or equal to 0.

[0008] Optionally, the clock adjustment circuit includes a baseband adjustment circuit, and the baseband adjustment circuit includes: a first data selector and a first branch adjustment circuit and a second branch adjustment circuit connected to the first data selector, the input ends of the first branch adjustment circuit and the second branch adjustment circuit are used to receive the input of the control word, the output end of the first branch adjustment circuit is connected to the first input end of the first data selector, and the output end of the second branch adjustment circuit is connected to the second input end of the first data selector.

[0009] Optionally, the first branch adjustment circuit delays the input divided clock by an even number of half cycles with a half cycle of the system clock as a step, and generates a first adjustment clock signal that is in phase with the divided clock according to the control word; the second branch adjustment circuit delays the divided clock by an odd number of half cycles with a half cycle of the system clock as a step, and generates a second adjustment clock signal that is in phase with the divided clock according to the control word, and the first data selector selects one of the first adjustment clock signal or the second adjustment clock signal for output.

[0010] Optionally, the first branch adjustment circuit includes: a first NAND gate, a second NAND gate, a third NAND gate and a first delay; the output end of the first NAND gate is connected to the first input end of the first data selector, one input end of the first NAND gate is connected to the output end of the first delay device, and the other input end of the first NAND gate is connected to the system clock; the first input end of the second NAND gate is used as the input end or is left floating, and the second input end is connected to the first enable signal, the first input end of the third NAND gate is connected to the output end of the second NAND gate, the second input end is connected to the first control word or the second enable signal, and the output end of the third NAND gate is connected to the input end of the first delay device.

[0011] Optionally, the second branch adjustment circuit includes: a fourth NAND gate, a fifth NAND gate, a sixth NAND gate and a second delay; the output end of the fourth NAND gate is connected to the second input end of the first data selector, the first input end of the fourth NAND gate is connected to the output end of the second delay device, and the second input end of the fourth NAND gate is connected to the system clock; the first input end of the fifth NAND gate is used as an input end or is left floating, the second input end is connected to the third enable signal, the first input end of the sixth NAND gate is connected to the output end of the fifth NAND gate, the second input end is connected to the second control word or the fourth enable signal, and the output end of the sixth NAND gate is connected to the input end of the second delay device.

[0012] Optionally, if the divided clock is a divided-by-1 clock, the first input terminal of the second NAND gate and the first input terminal of the fifth NAND gate are left floating, the second input terminal of the third NAND gate is connected to the first control word, and the second input terminal of the sixth NAND gate is connected to the second control word;

[0013] If the divided clock is an n-divided clock whose frequency is greater than 1, the first input end of the second NAND gate and the first input end of the fifth NAND gate serve as input ends, the second input end of the third NAND gate is connected to the second enable signal, and the second input end of the sixth NAND gate is connected to the third enable signal.

[0014] Optionally, if the divided clock n is greater than or equal to 1, n The frequency-divided clock, the clock adjustment circuit also includes a plurality of delay control units, the plurality of delay control units are arranged in series in n stages, the i-th stage includes 2 i+1 The delay control units, i=1, 2, ..., n.

[0015] Optionally, the delay control unit includes: a third delay device, a fourth delay device and a second data selector, the input end of the third delay device and the input end of the fourth delay device are connected to the control word or the output end of the second data selector of the next stage, the output end of the third delay device is connected to the first input end of the second data selector of the current stage, the output end of the fourth delay device is connected to the second input end of the second data selector of the current stage, the output end of the second data selector of the current stage is connected to the baseband adjustment circuit, or is connected to the third delay device or the fourth delay device of the previous stage.

[0016] The beneficial effects of the present invention are as follows: As can be seen from the above description, an embodiment of the present invention provides a phase adjustment circuit for a divided clock, comprising: a phase control word generating circuit, for generating a set of control words based on a reference clock and a divided clock that needs to be adjusted; a clock adjustment circuit, connected to the phase control word generating circuit, for adjusting the phase of the divided clock according to the control word, obtaining a divided synchronous clock synchronized with the reference clock, capable of adjusting the clock phase in real time and quickly in steps of half a system clock cycle, realizing switching between any two phases without losing the sampling edge of the clock, and capable of being applied to integrated circuits with high sampling accuracy requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 Schematic diagram of the structure of the phase adjustment circuit of the frequency-divided clock in an embodiment of the present invention;

[0019] Figure 2 Schematic diagram of the structure of the baseband adjustment circuit in an embodiment of the present invention;

[0020] Figure 3 Schematic diagram of the phase adjustment relationship of the baseband adjustment circuit in an embodiment of the present invention;

[0021] Figure 4 Schematic diagram of the structure of the phase adjustment circuit of the divided-by-two clock in an embodiment of the present invention;

[0022] Figure 5 Schematic diagram of the phase adjustment relationship of the phase adjustment circuit of the divided-by-two clock in an embodiment of the present invention;

[0023] Figure 6 Schematic diagram of the structure of the phase adjustment circuit of the 4-frequency divided clock in an embodiment of the present invention;

[0024] Figure 7 Schematic diagram of the phase adjustment relationship of the phase adjustment circuit of the 4-frequency divided clock in an embodiment of the present invention. DETAILED DESCRIPTION

[0025] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0026] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present invention should have the usual meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the embodiments of the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0027] The embodiment of the present invention provides a phase adjustment circuit for a frequency-divided clock. Figure 1As shown, the phase adjustment circuit of the divided clock includes: a phase control word generating circuit 1, which is used to generate a set of control words CTRL according to the reference clock sysref and the divided clock to be adjusted; a clock adjustment circuit 2, which is connected to the phase control word generating circuit 1, and is used to adjust the phase of the divided clock according to the control word CTRL to obtain a divided synchronous clock synchronized with the reference clock sysref. Figure 1 In the figure, clk_div1 is a divided-by-1 clock, that is, the system clock of the embodiment of the present invention, clk_div2 is a divided-by-2 clock, clk_div3 is a divided-by-3 clock, clk_div4 is a divided-by-4 clock, clk_div1_adjusted is a divided-by-1 synchronous clock, clk_div2_adjusted is a divided-by-2 synchronous clock, clk_div3_adjusted is a divided-by-3 synchronous clock, and clk_div4_adjusted is a divided-by-4 synchronous clock.

[0028] In this embodiment of the present invention, phase control word generation circuit 1 determines a phase offset value to be adjusted based on the input divided clock and reference clock sysref, and generates a control word CTRL based on the phase offset value. Clock adjustment circuit 2 adjusts the phase of the divided clock based on the control word CTRL, causing a phase offset in the divided clock to generate a divided synchronization clock corresponding to the divided clock, thereby achieving synchronization between the divided clock and reference signal sysref. This embodiment of the present invention rapidly and in real time adjusts the clock phase based on the phase relationship between the reference signal sysref and the divided clock, without losing the clock sampling edge during the adjustment process. This makes it suitable for integrated circuits requiring high sampling accuracy.

[0029] In the embodiment of the present invention, the divided clock is 2 n The divided clock, the number of control words CTRL is 2 n+1 where n is an integer greater than or equal to 0.

[0030] like Figure 2As shown, the clock adjustment circuit 2 includes a baseband adjustment circuit 21, which includes: a first data selector MUX1 and a first branch adjustment circuit 211 and a second branch adjustment circuit 212 connected to the first data selector MUX1, the input ends of the first branch adjustment circuit 211 and the second branch adjustment circuit 212 are used to receive the input of the control word CTRL, the output end of the first branch adjustment circuit 211 is connected to the first input end of the first data selector MUX1, and the output end of the second branch adjustment circuit 212 is connected to the second input end of the first data selector MUX1. The first branch adjustment circuit 211 delays the input divided clock by an even number of half cycles with a half cycle of the system clock clk_div1 as a step, and generates a first adjustment clock signal that is in phase with the divided clock according to the control word CTRL; the second branch adjustment circuit 212 delays the input divided clock by an odd number of half cycles with a half cycle of the system clock clk_div1 as a step, and generates a second adjustment clock signal that is in phase with the divided clock according to the control word CTRL. The first data selector MUX1 selects one of the first adjustment clock signal or the second adjustment clock signal for output.

[0031] Continue to see Figure 2 The first branch adjustment circuit 211 includes: a first NAND gate 2110, a second NAND gate 2111, a third NAND gate 2112 and a first delay 2113; the output end of the first NAND gate 2110 is connected to the first input end of the first data selector MUX1, one input end of the first NAND gate 2110 is connected to the output end of the first delay 2113, and the other input end of the first NAND gate 2110 is connected to the system clock clk_div1; the first input end of the second NAND gate 2111 is used as an input end or is left floating, and the second input end is connected to the first enable signal; the first input end of the third NAND gate 2112 is connected to the output end of the second NAND gate 2111, the second input end is connected to the first control word or the second enable signal, and the output end of the third NAND gate 2112 is connected to the input end of the first delay 2113.

[0032] The second branch adjustment circuit 212 includes: a fourth NAND gate 2120, a fifth NAND gate 2121, a sixth NAND gate 2122 and a second delay 2123; the output end of the fourth NAND gate 2120 is connected to the second input end of the first data selector MUX1, the first input end of the fourth NAND gate 2120 is connected to the output end of the second delay 2123, and the second input end of the fourth NAND gate 2120 is connected to the system clock clk_div1, specifically to the inverted system clock clk_div1; the first input end of the fifth NAND gate 2121 is used as an input end or is left floating, and the second input end is connected to the third enable signal; the first input end of the sixth NAND gate 2122 is connected to the output end of the fifth NAND gate 2121, the second input end is connected to the second control word or the fourth enable signal, and the output end of the sixth NAND gate 2122 is connected to the input end of the second delay 2123.

[0033] In the embodiment of the present invention, the first delay 2113 is used to generate an odd-numbered half-cycle delay of the system clock clk_div1. The second delay 2123 is used to generate an even-numbered half-cycle delay of the system clock clk_div1. If the divided clock is a 1-divided clock, Figure 2 CTRL0 and CTRL2 are enable signals, and CTRL1 and CTRL3 are control words. If the divided clock is n-divided clock, and n is greater than or equal to 2, Figure 2 CTRL0, CTRL1, CTRL2 and CTRL3 are all enable signals. Specifically, if the divided clock is a 1-divided clock, the first input terminal of the second NAND gate 2111 and the first input terminal of the fifth NAND gate 2121 are left floating, the second input terminal of the second NAND gate 2111 is connected to the first enable signal CTRL0, the second input terminal of the fifth NAND gate 2121 is connected to the third enable signal CTRL2, the second input terminal of the third NAND gate 2112 is connected to the first control word CTRL1, and the second input terminal of the sixth NAND gate 2122 is connected to the second control word CTRL3. The floating default value is 1, and the first input terminal of the second NAND gate 2111 and the first input terminal of the fifth NAND gate 2121 can also be directly connected to a high level 1. The 1-divided clock clk_div1 and its phase relationship are as follows: Figure 3 As shown, clk_div1 phase 0 represents the first adjusted clock signal with the same phase as the divided-by-1 clock clk_div1, and clk_div1 phase 1 represents the second adjusted clock signal obtained by shifting the phase of the divided-by-1 clock clk_div1 by half the system clock, that is, the clock signal with the opposite phase to the divided-by-1 clock clk_div1.

[0034] See also Figure 4 and Figure 6If the divided clock is an n-divided clock whose frequency is greater than 1, the first input end of the second NAND gate 2111 and the first input end of the fifth NAND gate 2121 serve as input ends, the second input end of the third NAND gate 2112 is connected to the second enable signal CTRL1, and the second input end of the sixth NAND gate 2122 is connected to the fourth enable signal CTRL3.

[0035] Continue to see Figure 4 and Figure 6 , if the divided clock n is greater than or equal to 12 n The clock adjustment circuit 2 further comprises a plurality of delay control units 22, wherein the plurality of delay control units 22 are arranged in series in n stages, and the i-th stage comprises 2 i+1 The delay control units, i = 1, 2, ..., n. 2 in the i-th level i+1 The delay control units 22 are arranged in parallel. The output of the first-stage delay control unit 22 is connected to the baseband adjustment circuit 21. The outputs of the delay control units 22 of the other stages are connected to the inputs of the previous stage delay control unit 22. The input of the last stage delay control unit 22 is connected to the control word CTRL.

[0036] The delay control unit 22 includes a third delay unit 221, a fourth delay unit 222, and a second data selector MUX2. The inputs of the third delay unit 221 and the fourth delay unit 222 are connected to the control word or the output of the second data selector MUX2 of the subsequent stage. The output of the third delay unit 221 is connected to the first input of the second data selector MUX2 of the current stage, the output of the fourth delay unit 222 is connected to the second input of the second data selector MUX2 of the current stage, and the output of the second data selector MUX2 of the current stage is connected to the baseband adjustment circuit 21, or to the third delay unit 221 or the fourth delay unit 222 of the previous stage. The third delay unit 221 is configured to generate a delay that is an odd multiple of a half-cycle of the system clock clk_div1, and the fourth delay unit 222 is configured to generate a delay that is an even multiple of a half-cycle of the system clock clk_div1.

[0037] Specifically, the first stage includes two delay control units 22. The output of the second data selector MUX2 in the first delay control unit 22 is connected to the input of the first branch adjustment circuit 211 in the baseband adjustment circuit 21, specifically to the first input of the second NAND gate 2111. The output of the second data selector MUX2 in the second delay control unit 22 is connected to the input of the second branch adjustment circuit 212 in the baseband adjustment circuit 21, specifically to the first input of the fifth NAND gate 2121. The inputs of the third delay unit 221 and the fourth delay unit 222 in each delay control unit 22 of the last stage are connected to different control words CTRL, respectively. The output of the second data selector MUX2 in each delay control unit 22 of the last stage is connected to the input of the third delay unit 221 or the input of the fourth delay unit 222 of the previous stage. The input ends of the third delay device 221 and the fourth delay device 222 of each delay control unit 22 of the intermediate stage are respectively connected to the output end of the second data selector MUX2 in the delay control unit 22 of the subsequent stage. The output end of the second data selector MUX2 in each delay control unit 22 of the intermediate stage is connected to the input end of the third delay device 221 or the input end of the fourth delay device 222 of the previous stage.

[0038] Figure 4 The diagram below shows the structure of the phase adjustment circuit for a divided-by-two clock. The phase adjustment circuit for the divided-by-two clock includes a baseband adjustment circuit 21 and two delay control units 22 connected in parallel. The first-stage delay formed by the two delay control units 22 is connected in series with the baseband adjustment circuit 21 to output the divided-by-two synchronous clock clk_div2_adjusted. CTRL0-CTRL3 are enable signals, and CTRL4-CTRL7 are control words. The phase adjustment relationship of the phase adjustment circuit for the divided-by-two clock is shown in Figure 1. Figure 5 As shown in the figure, clk_div2 phase 0, clk_div2 phase 1, clk_div2 phase 2, and clk_div2 phase 3 represent the four possible phase delays of the output divided-by-two synchronous clock clk_div2_adjusted, each differing by half a system clock cycle. Specifically, using half a system clock cycle as a step, path A2 generates a delay of N times (N is an integer) the divided-by-two clock, path B2 generates a delay of N+1 / 4 times the divided-by-two clock, path C2 generates a delay of N+1 / 2 times the divided-by-two clock, and path D2 generates a delay of N+3 / 4 times the divided-by-two clock. Control word generation circuit 1 generates control words CTRL4-CTRL7, and clock adjustment circuit 2 generates four clock phases: 0, 1, 2, and 3. Selecting a clock output from A2, B2, C2, or D2 achieves phase adjustment of the divided-by-two clock, allowing switching between any two phases without missing a clock sampling edge.

[0039] Figure 6 The diagram is a structural diagram of the phase adjustment circuit of a 4-frequency clock, which includes a base frequency adjustment circuit 21 and a plurality of delay control units 22. The multiple delay control units 22 constitute a two-stage delay, wherein the first stage includes two delay control units 22 connected in parallel, and the second stage includes four delay control units 22 connected in parallel. The input ends of the four delay control units 22 of the second stage are connected to the control word, and the output ends are connected to the input ends of the two delay control units 22 of the first stage. The output ends of the two delay control units 22 of the first stage are connected to the input ends of the base frequency adjustment circuit 21, and the 4-frequency synchronous clock clk_div4_adjusted is output from the output end of the base frequency adjustment circuit 21. Among them, CTRL0-CTRL3 are enable signals, and CTRL4-CTRL11 are control words. The phase adjustment relationship of the phase adjustment circuit of the 4-frequency clock is as follows: Figure 7 As shown, clk_div4 phase 0, clk_div4 phase 1, clk_div4 phase 2, clk_div4 phase 3, clk_div4 phase 4, clk_div4 phase 5, clk_div4 phase 6, and clk_div4 phase 7 are 8 phase delays generated by the phase adjustment circuit of the 4-frequency clock, and their phase differences are half a period of the system clock. Specifically, taking half a period of the system clock as a step, A4 generates N times (N is an integer) delay of the 4-frequency clock, B4 generates N+1 / 8 times delay of the 4-frequency clock, C4 generates N+1 / 4 times delay of the 4-frequency clock, D4 generates N+3 / 8 times delay of the 4-frequency clock, E4 generates N+1 / 2 times delay of the 4-frequency clock, F4 generates N+5 / delay of the 4-frequency clock, and G4 generates N+3 / 4 delay of the 4-frequency clock. H4 generates an N+7 / 8 delay of the divided-by-4 clock. Control word generation circuit 1 generates control words CTRL4-CTRL11. Clock adjustment circuit 2 obtains a total of 8 phases of 0, 1, 2, 3, 4, 5, 6, and 7. Selecting one clock output from A4, B4, C4, D4, E4, F4, G4, and H4 can achieve phase adjustment of the divided-by-4 clock and switch between any two phases without losing the clock sampling edge.

[0040] Taking the 1, 2, and 4 frequency division clock phase adjustment circuits as reference, the phase adjustment circuit of the embodiment of the present invention can perform 2 n (n is an integer) Phase adjustment of the divided clock, based on 2 n Frequency division clock generation 2 (n+1) Phase delay, with half cycle of system clock as step, can produce 2 n N times delay of the divided clock, 2 n N+1 / 2 frequency division (n+1) times the phase delay, 2 nFrequency division N+2 / 2 (n+1) times the phase delay, ..., N+(2 n+1 -1) / 2 (n+1) times the phase delay. Control word generation circuit 1 generates 2 n+1 A control word is obtained by clock adjustment circuit 2, 0 to 2 (n+1) -1 of 2 (n+1) Phases, from 2 (n+1) Select one phase output from the two phases to achieve 2 n The phase of the divided clock can be adjusted and switched between any two phases without losing the sampling edge of the clock.

[0041] The phase adjustment circuit of the frequency-divided clock of the embodiment of the present invention comprises: a phase control word generating circuit for generating a set of control words according to a reference clock and the frequency-divided clock to be adjusted, and a clock adjustment circuit connected to the phase control word generating circuit, the clock adjustment circuit is used to adjust the phase of the frequency-divided clock according to the control word, obtain the frequency-divided synchronous clock synchronized with the reference clock, and can adjust the clock phase quickly and in real time with half a cycle of the system clock as a step, and can adjust the clock phase for 1, 2, 4, 2 n The phase of the divided clock is adjusted and can be switched between any two phases without losing the sampling edge of the clock. It can be applied to integrated circuits with high sampling accuracy requirements.

[0042] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application is limited to these examples. Within the scope of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the present application as described above, which are not provided in detail for the sake of simplicity.

[0043] This application is intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the embodiments of the present invention. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present invention should be included in the scope of protection of this application.

Claims

1. A phase adjustment circuit for a frequency-divided clock, characterized in that: The phase adjustment circuit comprises: A phase control word generating circuit is used to generate a set of control words according to a reference clock and a frequency-divided clock that needs to be adjusted; A clock adjustment circuit, connected to the phase control word generation circuit, for adjusting the phase of the frequency-divided clock according to the control word to obtain a frequency-divided synchronous clock synchronized with the reference clock; The clock adjustment circuit includes a baseband adjustment circuit, which includes: a first data selector, and a first branch adjustment circuit and a second branch adjustment circuit connected to the first data selector, wherein the input ends of the first branch adjustment circuit and the second branch adjustment circuit are used to receive the input of the control word, the output end of the first branch adjustment circuit is connected to the first input end of the first data selector, and the output end of the second branch adjustment circuit is connected to the second input end of the first data selector; The first branch adjustment circuit delays the input divided clock by an even number of half cycles in steps of half cycles of the system clock, and generates a first adjustment clock signal that is in phase with the divided clock according to the control word; the second branch adjustment circuit delays the divided clock by an odd number of half cycles in steps of half cycles of the system clock, and generates a second adjustment clock signal that is in phase with the divided clock according to the control word, and the first data selector selects one of the first adjustment clock signal or the second adjustment clock signal for output.

2. The phase adjustment circuit according to claim 1, wherein: The phase control word generating circuit determines the phase offset value that needs to be adjusted based on the input divided clock and the reference clock, and generates a control word based on the phase offset value; the clock adjustment circuit adjusts the phase of the divided clock based on the control word to obtain the divided synchronization clock corresponding to the divided clock.

3. The phase adjustment circuit according to claim 1, wherein: The divided clock is 2 n The divided clock, the number of control words is 2 n+1 where n is an integer greater than or equal to 0.

4. The phase adjustment circuit according to claim 1, wherein: The first branch adjustment circuit includes: a first NAND gate, a second NAND gate, a third NAND gate and a first delay; the output end of the first NAND gate is connected to the first input end of the first data selector, one input end of the first NAND gate is connected to the output end of the first delay device, and the other input end of the first NAND gate is connected to the system clock; the first input end of the second NAND gate is used as an input end or is left floating, and the second input end is connected to a first enable signal, the first input end of the third NAND gate is connected to the output end of the second NAND gate, the second input end is connected to the first control word or the second enable signal, and the output end of the third NAND gate is connected to the input end of the first delay device.

5. The phase adjustment circuit according to claim 4, wherein: The second branch adjustment circuit includes: a fourth NAND gate, a fifth NAND gate, a sixth NAND gate and a second delay; the output end of the fourth NAND gate is connected to the second input end of the first data selector, the first input end of the fourth NAND gate is connected to the output end of the second delay device, and the second input end of the fourth NAND gate is connected to the system clock; the first input end of the fifth NAND gate is used as an input end or is left floating, and the second input end is connected to the third enable signal; the first input end of the sixth NAND gate is connected to the output end of the fifth NAND gate, the second input end is connected to the second control word or the fourth enable signal, and the output end of the sixth NAND gate is connected to the input end of the second delay device.

6. The phase adjustment circuit according to claim 5, wherein: If the divided-frequency clock is a divided-by-1 clock, the first input terminal of the second NAND gate and the first input terminal of the fifth NAND gate are left floating, the second input terminal of the third NAND gate is connected to the first control word, and the second input terminal of the sixth NAND gate is connected to the second control word; If the divided clock is an n-divided clock whose frequency is greater than 1, the first input end of the second NAND gate and the first input end of the fifth NAND gate serve as input ends, the second input end of the third NAND gate is connected to the second enable signal, and the second input end of the sixth NAND gate is connected to the third enable signal.

7. The phase adjustment circuit according to claim 1, wherein: If the divided clock is n greater than or equal to 1, n The frequency-divided clock, the clock adjustment circuit also includes a plurality of delay control units, the plurality of delay control units are arranged in series in n stages, the i-th stage includes 2 i+1 The delay control units, i=1, 2, ..., n.

8. The phase adjustment circuit according to claim 7, wherein: The delay control unit includes: a third delay device, a fourth delay device and a second data selector. The input end of the third delay device and the input end of the fourth delay device are connected to the control word or the output end of the second data selector of the next stage. The output end of the third delay device is connected to the first input end of the second data selector of the current stage. The output end of the fourth delay device is connected to the second input end of the second data selector of the current stage. The output end of the second data selector of the current stage is connected to the baseband adjustment circuit, or is connected to the third delay device or the fourth delay device of the previous stage.

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