A timing signal generating device and generating method

Abstract

The present invention provides a timing signal generating device and method. The timing signal generating device includes: a high-level and low-level duration register, which stores the duration of the high level and low level of each pulse cycle in the timing signal; a level flip threshold providing unit, which obtains the threshold of the high-level and low-level flip time of the timing signal based on the duration of the high level and low level of each pulse cycle in the timing signal; a timing signal level duration counting unit, which receives a trigger signal and counts after receiving the trigger signal; a trigger unit; and an output timing controller, which flips the level signal output by the output timing controller when the count value of the timing signal level duration counting unit reaches the threshold of the high-level and low-level flip time of the timing signal. The timing signal generating device provided by the present invention can flexibly control the timing signal.

Description

Technical Field

[0001] The present invention belongs to the technical field of sequential circuit structures, and in particular relates to a sequential signal generating device and a generating method. Background Art

[0002] A timing signal is a flag used to determine which micro-operations are performed during a certain period of time. Image sensors are equipped with multiple timing signals. These include those used to set a photodiode, initiate photoelectric conversion, stop photoelectric conversion, and perform analog-to-digital conversion.

[0003] In the timing signals of image sensors, when the chip requires more and more complex timings, the required number of register resources and electronic units will be very large and the configuration will be very difficult. Therefore, the existing technology cannot meet the requirements of universal timing signal generation. Summary of the Invention

[0004] The object of the present invention is to provide a timing signal generating device and a generating method, which can realize the independent control of multiple timing signals and flexibly adjust the composition of the timing signal generating device according to the number of registers and counters.

[0005] To achieve the above object, the present invention provides a timing signal generating device, comprising at least:

[0006] A high and low level duration register, storing the duration of the high level and the low level of each pulse cycle in the timing signal;

[0007] a level flip threshold providing unit, electrically connected to the high and low level duration register, wherein the level flip threshold providing unit obtains a threshold value of the flip time of the high and low levels of the timing signal according to the duration of the high level and the low level of each pulse cycle in the timing signal;

[0008] A timing signal level duration counting unit receives a trigger signal and counts after receiving the trigger signal;

[0009] a trigger unit electrically connected to the timing signal level duration counting unit and the level flip threshold providing unit; and

[0010] The output timing controller is electrically connected to the trigger unit, and when the count value of the timing signal level duration counting unit reaches the threshold of the switching time of the high and low levels of the timing signal, the level signal output by the output timing controller is switched.

[0011] In one embodiment of the present invention, the level flip threshold providing unit includes:

[0012] an adder, an input end of which is electrically connected to the high and low level duration registers; and

[0013] The selector has an input end electrically connected to the high and low level time length registers and the adder, and an output end of the selector is electrically connected to the trigger unit.

[0014] In one embodiment of the present invention, the output terminal of the output timing controller is electrically connected to the selector to adjust the output value of the selector.

[0015] In one embodiment of the present invention, the timing signal generating device further includes a pulse number counting unit, which is electrically connected to the trigger unit to record the number of pulse cycles or pulse levels of the timing signal.

[0016] In one embodiment of the present invention, the level flip threshold providing unit includes:

[0017] a selector, wherein an input end of the selector is electrically connected to the high and low level duration register, and an output end of the selector is electrically connected to the trigger unit; and

[0018] An adder, wherein an input end is electrically connected to the high and low level time length register and the selector, and an output end of the adder is electrically connected to the trigger unit.

[0019] In one embodiment of the present invention, the trigger unit includes:

[0020] a first comparator, whose input end is electrically connected to the selector and the timing signal level duration counting unit; and

[0021] The second comparator has an input end electrically connected to the adder and the timing signal level duration counting unit.

[0022] In one embodiment of the present invention, the level inversion threshold providing unit includes a timing pulse quantity counter, and the timing pulse quantity counter is electrically connected to the second comparator.

[0023] In one embodiment of the present invention, the timing signal generating device also includes a timing pulse quantity comparator, the input end of the timing pulse quantity comparator is electrically connected to the timing pulse quantity counter and the high and low level time length register, and the output end is electrically connected to the output timing controller, the level flip threshold providing unit and the timing pulse quantity counter.

[0024] In one embodiment of the present invention, the level flip threshold providing unit includes a selector, an input end of which is electrically connected to the high and low level duration register, and an output end of the selector is electrically connected to the trigger unit.

[0025] The present invention provides a method for generating a timing signal, comprising at least the following steps:

[0026] Setting the duration of the high level and the low level of each pulse cycle in the timing signal;

[0027] Obtaining a threshold value of a flip time between a high level and a low level of the timing signal according to a duration of a high level and a low level of each pulse period in the timing signal;

[0028] When receiving a trigger signal, using the timing signal level duration counting unit to count; and

[0029] When the count value of the timing signal level duration counting unit reaches the threshold of the switching time between the high and low levels of the timing signal, the level signal output by the output timing controller switches.

[0030] In summary, the present invention provides a timing signal generating device and method. For different types of timing signals, the optimal circuit implementation method can be selected to achieve optimal resource utilization, achieving the best resource utilization effect. Timing signals are implemented with minimal resources, and the timing is arbitrarily configurable. There are no restrictions on application scenarios or timing signal types, and the device is compatible with both internal and external triggering modes. At the same time, the present invention has good compatibility and practicality. The present invention provides a timing signal generating device that can achieve flexible regulation of timing signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0032] Figure 1 It is a control circuit of an image sensor in the present invention.

[0033] Figure 2 This is a schematic diagram of an image sensor control signal in the present invention.

[0034] Figure 3 It is a schematic diagram of various timing signals in the present invention.

[0035] Figure 4 It is a structural schematic diagram of a timing signal generating device in the present invention.

[0036] Figure 5 In the present invention Figure 3 Schematic diagram of the structure of the device for generating the first type of timing signal.

[0037] Figure 6 In the present invention Figure 3 Schematic diagram of the structure of the device for generating the second type of timing signal.

[0038] Figure 7 In the present invention Figure 3 Schematic diagram of the structure of the device for generating the third type of timing signal.

[0039] Figure 8 In the present invention Figure 5 Flowchart of the timing generation method corresponding to the timing signal generating device.

[0040] Figure 9 In the present invention Figure 6 Flowchart of the timing generation method corresponding to the timing signal generating device.

[0041] Figure 10 In the present invention Figure 7 Flowchart of the timing generation method corresponding to the timing signal generating device. DETAILED DESCRIPTION

[0042] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The accompanying drawings illustrate preferred embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the disclosure of the present application.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0044] In the description of the present invention, it should be understood that the terms "center," "upper," "lower," "front," "back," "left," and "right" and the like, indicating positions or relationships, are based on the positions or relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0045] See also Figures 1 to 2As shown in FIG, a photosensitive area and a logic control area are provided in the image sensor. The photosensitive area is provided with a photodiode, which can convert the light signal into an electrical signal and store it. The logic control area includes a plurality of logic control devices, such as a transmission tube M1, a reset tube M2, a source follower M3 and a row select tube M4. The connection relationship between the transmission tube M1, the reset tube M2, the source follower M3 and the row select tube M4 is as follows: Figure 1 As shown. The transmission tube M1 can effectively reduce the thermal noise and dark current of the pixel, and the source follower M3 can play the role of buffer amplification, so that the column bus with large parasitic capacitance and the subsequent readout circuit are isolated from each sensitive node of the pixel. When performing photoelectric conversion, the timing of each logic control device is as follows Figure 2 As shown in the figure. When the image sensor is operating, the enable signal row_sel first controls the switching of the row select transistor M4, and the enable signal row_sel serves as the counting signal of the counter. When the level of the enable signal row_sel changes, the counter begins counting. When the timer matches the value of the corresponding register in the circuit, the reset signal rst is pulled up. The image sensor turns on the reset signal rst to reset, and then quantizes the reset information through the analog-to-digital conversion signal ADC. After quantization is completed, the integrated signal of the photodiode in the image sensor is read by turning on the read signal tx transistor. Finally, the integrated signal is quantized by the analog-to-digital converter and the reset signal rst is subtracted to complete the signal reading.

[0046] Please combine Figure 2 and Figure 3 As shown, in one embodiment of the present invention, the timing signal can be divided into three categories according to the number of pulse cycles of the timing signal and the duration of the high level and low level in each pulse cycle. The first type of timing signal is a single pulse signal S1, for example Figure 2 The enable signal row_sel, reset signal rst or read signal tx in the second type of timing signal is a repetitive multi-pulse signal S2. The third type of timing signal is a non-repetitive multi-pulse signal S3, for example Figure 2 Analog-to-digital conversion signal ADC. Different timing circuit configurations can be selected for different types of timing signals.

[0047] See also Figure 4As shown, in one embodiment of the present invention, a timing signal generating device is provided, which can generate different types of timing signals. In this embodiment, the timing signal generating device includes a high and low level duration register 101, a level flip threshold providing unit 12, a timing signal level duration counting unit 13, a trigger unit 14 and an output timing controller 105. Among them, the high and low level duration register 101 stores the duration of the high level and the low level of each pulse cycle in the timing signal. The level flip threshold providing unit 12 is electrically connected to the high and low level duration register 101, and can obtain the threshold of the flip time of the high and low levels of the timing signal based on the duration of the high level and the low level of each pulse cycle in the timing signal. The timing signal level duration counting unit 13 starts counting after receiving the trigger signal. The trigger unit 14 is electrically connected to the level flip threshold providing unit 12 and the timing signal level duration counting unit 13. When the count value of the timing signal level duration counting unit 13 reaches the flip time threshold provided by the level flip threshold providing unit 12, the output timing controller 105 can be triggered to flip the signal output by the output timing controller 105.

[0048] See also Figure 5 As shown, in one embodiment of the present invention, a timing signal generating device is provided, which can generate Figure 3 The first type of timing signal shown in FIG is a single pulse signal S1. The single pulse signal S1 has only one pulse cycle after receiving the trigger signal.

[0049] See also Figure 3 and Figure 5 As shown, in one embodiment of the present invention, the high and low level duration registers 101 store the durations of the high and low levels in a single pulse cycle of the single pulse signal S1. In this embodiment, the high and low level duration registers 101 store a first duration P1 from the receipt of the trigger signal to the rising edge (or falling edge) of the single pulse signal S1, and a second duration P2 during which the single pulse signal S1 maintains a high level (or low level). Therefore, for example, two high and low level duration registers 101 can be provided, and the first duration P1 and the second duration P2 can be configured in the two high and low level duration registers 101, respectively.

[0050] See also Figure 4 and Figure 5As shown, in one embodiment of the present invention, the level flip threshold providing unit 12 includes an adder 1021 and a selector 1022. The input end of the adder 1021 is electrically connected to the high and low level duration register 101, and the input end of the selector 1022 is electrically connected to the adder 1021 and the high and low level duration register 101. The adder 1021 can add the first duration P1 and the second duration P2 of the input single pulse signal S1 to obtain the pulse period of the single pulse signal S1. The input end of the selector 1022 inputs the first duration P1 and the pulse period of the single pulse signal S1, that is, the first duration P1 + the second duration P2. The input of the selector 1022 is also electrically connected to the output of the output timing controller 105. The output of the output timing controller 105 outputs a single pulse signal S1. The selector 1022 can select whether to provide the first duration P1 or the pulse period of the single pulse signal (first duration P1 + second duration P2) to the input of the comparator 104 based on the level of the output single pulse signal S1. In this embodiment, when the level of the single pulse signal S1 is low, the selector 1022 outputs the first duration P1. When the level of the single pulse signal S1 is high, the selector 1022 outputs the pulse period of the single pulse signal.

[0051] See also Figure 4 and Figure 5 As shown, in one embodiment of the present invention, the timing signal level duration counting unit 13 is, for example, a first counter 103, and the trigger unit 14 is, for example, a comparator 104. The input end of the first counter 103 is connected to the input clock signal, and the output end is electrically connected to the input end of the comparator 104. The output end of the selector 1022 is also electrically connected to the input end of the comparator 104. The output end of the comparator 104 is electrically connected to the input end of the output timing controller 105, and the input end of the output timing controller 105 is also connected to the input clock signal.

[0052] For details, please refer to Figure 5 and Figure 8As shown, in one embodiment of the present invention, the timing signal generation method of the present invention includes steps S101 to S112. When the first counter 103 does not receive a trigger signal, the output timing controller 105 outputs an initial level, which can be a high level 1 or a low level 0. In this embodiment, when the first counter 103 does not receive a trigger signal, the output timing controller 105 outputs a low level. The trigger signal can be an internal trigger signal or an external reset signal. Upon receiving the trigger signal, the first counter 103 begins counting. When the count value of the first counter 103 reaches the first time duration P1, that is, CNT1 = P1, the comparator 104 triggers the output timing controller 105, causing the level of the output timing controller 105 to flip and output a high level. At this point, the first counter 103 continues counting. When the count value of the first counter 103 reaches the pulse period of the single pulse signal, that is, CNT1 = P1 + P2, the comparator 104 triggers the output timing controller 105 again, causing the level of the output timing controller 105 to flip and output a low level. After that, the first counter 103 continues to count until the first counter 103 receives an internal trigger signal (to a preset cycle value) or an external reset signal (external trigger signal) again, the first counter 103 is cleared and then counts again, thereby cyclically generating a single pulse signal S1.

[0053] See also Figure 4 、 Figure 6 and Figure 7 As shown, in other embodiments of the present invention, the timing signal generating device further includes a pulse number counting unit 16. The pulse number counting unit 16 is electrically connected to the output end of the trigger unit 14. When the trigger unit 14 outputs a trigger signal, the pulse number counting unit 16 counts to record the number of pulse cycles or pulse levels of the timing signal. The output end of the pulse number counting unit 16 is also electrically connected to the timing signal level duration counting unit 13 and the trigger unit 14. When the number of pulse cycles or pulse levels recorded by the pulse number counting unit 16 reaches the number of pulse cycles or pulse levels of the timing signal, the signal level duration counting unit 13 and the trigger unit 14 are reset.

[0054] See also Figure 4 and Figure 6 As shown, in one embodiment of the present invention, the timing signal generating device can generate the following Figure 3 The second type of timing signal shown in is the repetitive multi-pulse signal S2. Figure 6 As shown, in one embodiment of the present invention, the pulse number counting unit 16 includes a newly added sequential pulse number counter, namely, a second counter 206. A third comparator 2043 electrically connected to the second counter 206 is also provided.

[0055] See also Figure 3 、 Figure 4 and Figure 6 As shown, in one embodiment of the present invention, the high and low level duration register 201 stores the duration of the high and low levels of the repetitive multi-pulse signal S2, as well as the number of pulse cycles of the repetitive multi-pulse signal S2. In this embodiment, the high and low level duration register 201 stores the first duration P1 from the receipt of the trigger signal to the rising edge (or falling edge) of the repetitive multi-pulse signal S2, the second duration P2 for the high level (or low level) of the repetitive multi-pulse signal S2, the third duration P3 for the low level (or high level) of the repetitive multi-pulse signal S2, and the number PN of pulse cycles of the repetitive multi-pulse signal S2. Therefore, for example, four high and low level duration registers 101 can be set, and the first duration P1, the second duration P2, the third duration P3 and the number PN of pulse cycles can be configured in the four high and low level duration registers 101 respectively.

[0056] See also Figure 4 and Figure 6 As shown, in one embodiment of the present invention, the level flip threshold providing unit 12 includes an adder 2021 and a selector 2022, the timing signal level duration counting unit 13 includes a first counter 203, the triggering unit 14 includes a first comparator 2041, a second comparator 2042, and a third comparator 2043, and the pulse number counting unit 16 includes a second counter 206. The second counter 206 records the number of pulse cycles of the repetitive multi-pulse signal S2, and the number of pulse cycles includes the number of first pulse cycles and the number of cyclic pulse cycles. The third comparator 2043 is a timing pulse number comparator.

[0057] See also Figure 4 and Figure 6 As shown, in one embodiment of the present invention, the input end of the selector 2022 is electrically connected to the high and low level duration register 201 and the output end of the second counter 206, and the output end of the selector 2022 is electrically connected to the input end of the adder 2021 and the input end of the first comparator 2041. The high and low level duration register 201 inputs the first duration P1 and the third duration P3 into the selector 2022. The selector 2022 selects whether the first duration P1 or the third duration P3 is input to the adder 2021 or the first comparator 2041 based on whether the output value of the second counter 206 is zero. In this embodiment, when the output value of the second counter 206 is zero, the selector 2022 outputs the first duration P1. When the output value of the second counter 206 is not zero, the selector 2022 outputs the third duration P3.

[0058] See also Figure 4 and Figure 6As shown, in one embodiment of the present invention, the input terminal of the first counter 203 is connected to the input clock signal, the input terminal of the first comparator 2041 is electrically connected to the output terminal of the first counter 203 and the output terminal of the selector 2022, and the input terminal of the output timing controller 205 is electrically connected to the output terminal of the first comparator 2041. When the count value of the first counter 203 is equal to the value of the output terminal of the selector 2022, the first comparator 2041 triggers the output timing controller 205 to flip the level.

[0059] See also Figure 4 and Figure 6 As shown, in one embodiment of the present invention, the input end of the adder 2021 is electrically connected to the output end of the selector 2022 and the high and low level duration register 201. The adder 2021 adds the second duration P2 output by the high and low level duration register 201 and the first duration P1 or the third duration P3 output by the selector 2022, and outputs the sum at the output end. The first duration P1 and the second duration P2 are added together to form the first pulse period of the repetitive multi-pulse signal S2, and the second duration P2 and the third duration P3 are added together to form the cyclic pulse period of the repetitive multi-pulse signal S2. The second comparator 2042 is electrically connected to the output end of the first counter 203 and the output end of the adder 2021, and the input end of the output timing controller 205 is electrically connected to the output end of the second comparator 2042. When the count value of the first counter 203 equals the first pulse period (P1+P2) or the cycle pulse period (P3+P2), the second comparator 2042 triggers the output timing controller 205 to flip the level. The output of the second comparator 2042 is also electrically connected to the first counter 203. When the second comparator 2042 has an output, the first counter 203 is reset.

[0060] See also Figure 4 and Figure 6 As shown, in one embodiment of the present invention, the input end of the second counter 206 is electrically connected to the output end of the second comparator 2042. When the output end of the second comparator 2042 has an output, the second counter 206 increases by 1 to record the number of pulse periods of the repetitive multi-pulse signal S2. The input end of the third comparator 2043 is electrically connected to the output end of the second counter 206 and the output end of the high and low level duration register 201. The output end of the third comparator 2043 is electrically connected to the first counter 203, the second counter 206, and the output timing controller 205. When the count value of the second counter 206 is equal to the number PN of pulse periods of the repetitive multi-pulse signal S2, the third comparator 2043 is triggered, causing the first counter 203 and the second counter 206 to reset, and the output timing controller 205 to return to its initial state.

[0061] For details, please refer to Figure 6 and Figure 9As shown, in one embodiment of the present invention, the timing signal generation method of the present invention includes steps S201 to S215. When the first counter 203 does not receive a trigger signal, the output timing controller 205 outputs an initial level, which can be a high level 1 or a low level 0. In this embodiment, when the first counter 203 does not receive a trigger signal, the output timing controller 205 outputs a low level. When a trigger signal is received, the first counter 203 begins counting, and the value of the second counter 206 is 0. At this time, the selector 2022 outputs P=P1. When the count value of the first counter 203 reaches P1, that is, CNT1=P1, the first comparator 2041 triggers the output timing controller 205, and the level of the output timing controller 205 flips, outputting a high level. The first counter 203 continues counting. When the first counter 203 reaches P1+P2, that is, CNT1=P1+P2, the second comparator 2042 triggers the output timing controller 205, and the level of the output timing controller 205 flips again, outputting a low level. At the same time, the second counter 206 begins counting, and the first counter 203 is cleared. Since the output value of the second counter 206 is non-zero, the selector 2022 outputs the pulse edge position of the cycle, i.e., P = P3. The first counter 203 restarts counting. When the value of the first counter 203 reaches P3, i.e., CNT1 = P3, the first comparator 2041 triggers the output timing controller 205, causing the output timing controller 205 to flip its level and output a high level. The first counter 203 continues counting. When the value of the first counter 203 reaches P3 + P2, i.e., CNT1 = P3 + P2, the second comparator 2042 triggers the output timing controller 205, causing the output timing controller 205 to flip its level again and output a low level. At the same time, the second counter 206 begins counting, and the first counter 203 is cleared. The above steps are repeated until the count value of the second counter 206 reaches the number of pulse cycles, PN, of the repetitive multi-pulse signal S2, i.e., CNT2 = PN, at which point the cycle ends. When the second counter 206 reaches the preset pulse cycle number PN (internally triggered) or the external reset signal (externally triggered) arrives again, the first counter 203 and the second counter 206 are reset to zero and then restart counting to cyclically generate a repetitive multi-pulse signal S2.

[0062] See also Figure 4 and Figure 7 As shown, in one embodiment of the present invention, the timing signal generating device can generate the following Figure 3 The third type of timing signal shown in is the non-repetitive multi-pulse signal S3. Figure 7As shown, in one embodiment of the present invention, the pulse number counting unit 16 includes a newly added timing pulse number counter, namely the second counter 306. A second comparator 3042 electrically connected to the second counter 306 is also provided, wherein the second comparator 3042 is a timing pulse number comparator.

[0063] See also Figure 3 、 Figure 4 and Figure 7 As shown, in one embodiment of the present invention, the high and low level duration register 301 stores the duration of the high and low levels of the timing signal. In this embodiment, the high and low level duration register 301 stores the first duration P1 from the receipt of the trigger signal to the rising edge (or falling edge) of the non-repetitive multi-pulse signal S3, the second duration P2 for the high level (or low level) of the non-repetitive multi-pulse signal S3, the third duration P3 for the low level (or high level) of the non-repetitive multi-pulse signal S3, and the number of pulse levels PM of the non-repetitive multi-pulse signal S3. In this case, the pulse is a non-repetitive pulse, and the number of pulse levels PM needs to be recorded to record the number of pulses. In this embodiment, the second duration P2 in each pulse cycle is not equal, and the third duration P3 in each pulse cycle is also not equal. The second duration P2 specifically includes a second duration P21, P22, P23, P24, P25, or P26, and the third duration P3 specifically includes a third duration P31, P32, P33, P34, P35, or P36. The high and low level duration registers 101 are set according to the number of durations to be stored.

[0064] See also Figure 4 and Figure 7 As shown, in one embodiment of the present invention, the level flip threshold providing unit 12 includes a selector 302, the timing signal level duration counting unit 13 includes a first counter 303, the pulse number counting unit 16 includes a second counter 306, and the triggering unit 14 includes a first comparator 3041 and a second comparator 3042. The second counter 306 records the pulse level number PM of the non-repetitive multi-pulse signal S3.

[0065] See also Figure 7As shown, in one embodiment of the present invention, the input end of the selector 302 is electrically connected to the high and low level duration register 301 and the output end of the second counter 306, and the output end of the selector 302 is electrically connected to the input end of the first comparator 3041. The high and low level duration register 301 inputs the first duration P1, the second duration P2, and the third duration P3 into the selector 302. The selector 302 selects the first duration P1, the second duration P2, and the third duration P3 according to the change of the output value of the second counter 306 and outputs them to the first comparator 3041. In this embodiment, the selector 302 outputs the non-repetitive multi-pulse signal S3 in a high and low level order. For example, when the selector 302 first outputs the first duration P1, the non-repetitive multi-pulse signal S3 changes its level, the selector 302 outputs the second duration P21. After the non-repetitive multi-pulse signal S3 changes its level again, the selector 302 outputs the third duration P31, and so on.

[0066] See also Figure 7 As shown, in one embodiment of the present invention, the input terminal of the first counter 303 is connected to the input clock signal, the input terminal of the first comparator 3041 is electrically connected to the output terminal of the first counter 303 and the output terminal of the selector 302, and the input terminal of the output timing controller 305 is electrically connected to the output terminal of the first comparator 3041. When the count value of the first counter 303 is equal to the value of the output terminal of the selector 302, the first comparator 3041 triggers the output timing controller 305 to flip the level.

[0067] See also Figure 7 As shown, in one embodiment of the present invention, the input terminal of the second counter 306 is electrically connected to the output terminal of the first comparator 3041. When the output terminal of the first comparator 3041 outputs an output, the second counter 306 increases by 1 to record the number of pulse levels PM of the non-repetitive multi-pulse signal S3. The input terminal of the second comparator 3042 is electrically connected to the output terminal of the first counter 303 and the output terminal of the high and low level duration register 301. The output terminal of the second comparator 3042 is electrically connected to the first counter 303, the second counter 306, and the output timing controller 305. When the count value of the second counter 306 is equal to the number of pulse levels PM of the non-repetitive multi-pulse signal S3, the second comparator 3042 is triggered, causing the first counter 303 and the second counter 306 to reset, and the output timing controller 305 to return to its initial state.

[0068] For details, please refer to Figure 7 and Figure 10As shown, in one embodiment of the present invention, the timing signal generation method described in the present invention includes steps S301 to S312. When the first counter 303 does not input a trigger signal, the output timing controller 305 outputs an initial level, which can be a high level 1 or a low level 0. In this embodiment, when the first counter 303 does not input a trigger signal, the output timing controller 305 outputs a low level. When a trigger signal is received, the first counter 303 starts counting, and the value of the second counter 306 is 0. At this time, the selector 302 outputs P=P1. When the count value of the first counter reaches P1, that is, CNT1=P1, the first comparator 3041 triggers the output timing controller 305, and the level of the output timing controller 305 is flipped, outputting a high level. At the same time, the second counter 306 continues counting, and the first counter 303 is cleared. The selector outputs P = P21. When the count value of the first counter 303 reaches P21 again, that is, CNT1 = P21, the first comparator 3041 triggers the output timing controller 305, and the output timing controller 305 flips its level, outputting a low level. At the same time, the second counter 306 begins counting, and the first counter 303 is cleared. The selector outputs P = P31. When the count value of the first counter 303 reaches P31 again, that is, CNT1 = P31, the first comparator 3041 triggers the output timing controller 305, and the output timing controller 305 flips its level, outputting a high level. The above steps are repeated until the count value of the second counter 306 reaches the number of pulse levels PM, that is, CNT2 = PM, at which point the loop ends. When the second counter 206 reaches the preset pulse level number PM (when internally triggered) or the external reset signal arrives again (when externally triggered), the first counter 303 and the second counter 306 are reset to zero and then restart counting, cyclically generating the non-repetitive multi-pulse signal S3. In this case, no matter how many edges the non-repetitive multi-pulse signal S3 has, only two comparators are required, regardless of the number of edge changes, which greatly saves circuit resources.

[0069] It is worth noting that the present invention can decompose a repetitive or non-repetitive multi-pulse signal into multiple single pulse signals and realize a multi-pulse timing signal by superposition. For example, the repetitive multi-pulse signal S2 or the non-repetitive multi-pulse signal S3 can be decomposed into multiple single pulse signals S1 and superposed. According to the method of obtaining the single pulse signal S1, the repetitive multi-pulse signal S2 or the non-repetitive multi-pulse signal S3 can be obtained by superposition. However, this solution obviously requires more circuit resources than this solution. It is also possible to decompose the repetitive multi-pulse signal S2 or the non-repetitive multi-pulse signal S3 into multiple single pulse signals S1 and superpose them according to the method of obtaining the single pulse signal S1. Figure 5 The input of the selector of the timing signal generating device is modified to Figure 6The output of the high and low level duration register can obtain the repetitive multi-pulse signal S2. These solutions are also technical solutions that can be obtained by those skilled in the art without creative work by making modifications based on the concept of the present invention, and should also be regarded as the intended protection points of the present invention.

[0070] In the present application, the registers, counters, adders, selectors, comparators and output timing controllers in the timing signal generating devices corresponding to the first type of timing signals, the second type of timing signals and the third type of timing signals can be universal. In actual applications, the required electrical components can be selected according to the type of timing signal to be generated.

[0071] To sum up, the timing signal generating device and generating method provided by the present invention use high and low level duration registers to set the duration of the high level and low level of each pulse cycle in the timing signal, and use the level flip threshold providing unit to obtain the threshold of the flip time of the high and low levels of the timing signal according to the duration of the high level and low level of each pulse cycle in the timing signal. After receiving the trigger signal, the timing signal level duration counting unit uses the timing signal level duration counting unit to count. When the count value of the timing signal level duration counting unit reaches the threshold of the flip time of the high and low levels of the timing signal, the trigger unit triggers the level signal output by the output timing controller to flip to form a timing signal.

[0072] The embodiments of the present invention disclosed above are intended only to illustrate the present invention. They do not describe all details in detail, nor do they limit the present invention to the specific embodiments described. Obviously, many modifications and variations are possible based on the content of this specification. These embodiments are selected and described in detail in this specification to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to better understand and utilize the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A timing signal generating device, characterized in that: include: A high and low level duration register stores the duration of the high level and the low level of each pulse period in the timing signal, and the high level duration register stores a first duration from receiving the trigger signal to the rising edge or falling edge of the repetitive multi-pulse signal, a second duration for maintaining the high level or low level of the repetitive multi-pulse signal, and a third duration for maintaining the low level or high level of the repetitive multi-pulse signal; a level flip threshold providing unit, electrically connected to the high and low level duration register, wherein the level flip threshold providing unit obtains a threshold value of the flip time of the high and low levels of the timing signal according to the duration of the high level and the low level of each pulse cycle in the timing signal; A timing signal level duration counting unit receives a trigger signal and counts after receiving the trigger signal; a trigger unit electrically connected to the timing signal level duration counting unit and the level flip threshold providing unit; as well as an output timing controller electrically connected to the trigger unit, and when the count value of the timing signal level duration counting unit reaches the threshold of the switching time of the high and low levels of the timing signal, the level signal output by the output timing controller is reversed; a pulse number counting unit, the pulse number counting unit being electrically connected to the trigger unit to record the number of pulse cycles or pulse levels of the timing signal; Wherein, the level flip threshold providing unit includes: a selector, wherein an input end is electrically connected to the high and low level duration register, and an output end of the selector is electrically connected to the trigger unit, and when the output value of the pulse number counting unit is zero, the selector outputs the first duration, and when the output value of the pulse number counting unit is not zero, the selector outputs the third duration; and an adder, the input end of which is electrically connected to the high and low level duration register and the selector, and the second duration output by the high and low level duration register and the first and third duration output by the selector are input to the adder, and the output end of the adder is electrically connected to the trigger unit; The trigger unit includes a first comparator, a second comparator and a third comparator, wherein, when the count value of the timing signal level duration counting unit is equal to the count value of the selector, the first comparator triggers the output timing controller to cause a level flip; when the count value of the timing signal level duration counting unit is equal to the first pulse period or the cycle pulse period, the second comparator triggers the output timing controller to cause a level flip; when the count value of the pulse number counting unit is equal to the number of pulse periods of the repetitive multi-pulse signal, the third comparator is triggered, so that the timing signal level duration counting unit and the pulse number counting unit are reset, and the output timing controller returns to an initial state.

2. The timing signal generating device according to claim 1, wherein: The level flip threshold providing unit includes: an adder, an input end of which is electrically connected to the high and low level duration registers; and The selector has an input end electrically connected to the high and low level time length registers and the adder, and an output end of the selector is electrically connected to the trigger unit.

3. The timing signal generating device according to claim 2, wherein: The output terminal of the output timing controller is electrically connected to the selector to adjust the output value of the selector.

4. The timing signal generating device according to claim 1, wherein: The trigger unit includes: a first comparator, whose input end is electrically connected to the selector and the timing signal level duration counting unit; and The second comparator has an input end electrically connected to the adder and the timing signal level duration counting unit.

5. The timing signal generating device according to claim 4, wherein: The level inversion threshold providing unit includes a timing pulse quantity counter, and the timing pulse quantity counter is electrically connected to the second comparator.

6. The timing signal generating device according to claim 5, characterized in that: The timing signal generating device also includes a timing pulse quantity comparator, the input end of the timing pulse quantity comparator is electrically connected to the timing pulse quantity counter and the high and low level duration registers, and the output end is electrically connected to the output timing controller, the level flip threshold providing unit and the timing pulse quantity counter.

7. The timing signal generating device according to claim 1, wherein: The level flip threshold providing unit includes a selector, an input end of which is electrically connected to the high and low level duration register, and an output end of the selector is electrically connected to the trigger unit.

8. A timing signal generation method, characterized in that: At least the following steps are included: Setting a high and low level duration register to store the duration of the high level and the low level of each pulse period in the timing signal, and the high and low level duration register stores a first duration from receiving the trigger signal to the rising edge or falling edge of the repetitive multi-pulse signal, a second duration for maintaining the high level or low level of the repetitive multi-pulse signal, and a third duration for maintaining the low level or high level of the repetitive multi-pulse signal; Setting a level flip threshold providing unit, wherein the level flip threshold providing unit obtains a threshold of a flip time of a high level and a low level of the timing signal according to a duration of a high level and a low level of each pulse cycle in the timing signal; When receiving a trigger signal, the timing signal level duration counting unit is used to count; Setting a trigger unit, the trigger unit being electrically connected to the timing signal level duration counting unit and the level flip threshold providing unit; as well as An output timing controller is set, and when the count value of the timing signal level duration counting unit reaches the threshold value of the switching time of the high and low levels of the timing signal, the trigger unit triggers the switching of the level signal output by the output timing controller; Setting a pulse number counting unit to record the number of pulse cycles or pulse levels of the timing signal; Wherein, the level flip threshold providing unit includes: a selector, wherein an input end is electrically connected to the high and low level duration register, and an output end of the selector is electrically connected to the trigger unit, and when the output value of the pulse number counting unit is zero, the selector outputs the first duration, and when the output value of the pulse number counting unit is not zero, the selector outputs the third duration; and an adder, the input end of which is electrically connected to the high and low level duration register and the selector, and the second duration output by the high and low level duration register and the first and third duration output by the selector are input to the adder, and the output end of the adder is electrically connected to the trigger unit; The trigger unit includes a first comparator, a second comparator and a third comparator, wherein, when the count value of the timing signal level duration counting unit is equal to the count value of the selector, the first comparator triggers the output timing controller to cause a level flip; when the count value of the timing signal level duration counting unit is equal to the first pulse period or the cycle pulse period, the second comparator triggers the output timing controller to cause a level flip; when the count value of the pulse number counting unit is equal to the number of pulse periods of the repetitive multi-pulse signal, the third comparator is triggered, so that the timing signal level duration counting unit and the pulse number counting unit are reset, and the output timing controller returns to an initial state.

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