Refresh management for DRAM

Abstract

A memory controller interfaces with a dynamic random access memory (DRAM). The memory controller selectively places memory commands in a memory interface queue and transmits the commands from the memory interface queue to a memory channel connected to at least one dynamic random access memory (DRAM). The transmitted commands are stored in a replay queue. The number of activate commands to a memory region of the DRAM is counted. Based on the count, a refresh control circuit signals that an emergency refresh command should be sent to the memory region. In response to detecting a specified type of error, a recovery sequence is initiated to retransmit memory commands from the replay queue. The specified error condition can cause the recovery sequence to restart. If an emergency refresh command is pending at the time such a restart occurs, the recovery sequence is interrupted to allow the emergency refresh command to be sent.

Description

Background Technology

[0001] Computer systems typically use inexpensive and high-density Dynamic Random Access Memory (DRAM) chips as main memory. When a specific row in a DRAM chip is activated for reading or writing, the word line associated with that row is activated, and the contents of the memory cells along that row are read into the page buffer. Subsequent read and write accesses to the memory cells in that row can be performed entirely within the page buffer without accessing the row again. When the data processor later accesses another row in the same memory bank, the memory cells along that row are restored in a precharge operation before the other row becomes available.

[0002] Modern DRAM chips typically use deep submicron technology to store one to eight gigabits (Gb) of data. Due to the high density and small feature size, memory rows are physically very close to each other, such that activation of a particular row can disturb data stored in adjacent rows by changing the charge on the memory cell capacitors. In the past, these disturbances were usually harmless because the memory cells were refreshed periodically. However, some memory access patterns occasionally cause certain rows to be activated and precharged many times before the next refresh cycle, resulting in memory cells in adjacent rows being corrupted and their logic state reversed. After corruption, the original data is lost and cannot be recovered in subsequent refresh cycles. As feature sizes become smaller, this problem (known as "row hammer") becomes more difficult to mitigate because fewer row activations are required to cause it.

[0003] One known technique for addressing data scrambling is called Target Row Refresh (TRR). To ensure that DRAM rows are not activated too many times during a refresh cycle, the memory controller puts the DRAM into TRR mode by setting certain mode register bits. The controller then issues successive activation and precharge commands to the target row and two physically adjacent rows. Once TRR mode is enabled, no other mode register commands are allowed until TRR mode is complete. TRR mode is self-clearing, and the mode register bits are set after TRR mode is complete. While TRR allows the memory controller to avoid over-activation of specific rows within a specific time period, it is implemented by setting the mode registers, which takes a significant amount of time because all memory banks must be idle before the controller can issue mode register set commands. Attached Figure Description

[0004] Figure 1 The accelerated processing unit (APU) and memory system known in the prior art are shown in block diagram form;

[0005] Figure 2 The diagram illustrates, in block form, the suitability for some implementation schemes in similar situations. Figure 1 The memory controller used in the APU;

[0006] Figure 3 It is a flowchart of the process for handling refresh management based on some implementation schemes;

[0007] Figure 4 It is a flowchart of a process for replaying commands according to some implementation schemes; and

[0008] Figures 5-7 It is a series of illustrations of portions of the recovery sequence based on some implementation schemes.

[0009] In the following description, the same reference numerals are used in different figures to indicate similar or identical items. Unless otherwise stated, the word “coupled” and its associated verb form include both direct connection and indirect electrical connection by means known in the art, and unless otherwise stated, any description of direct connection also implies alternative embodiments using suitable forms of indirect electrical connection. Detailed Implementation

[0010] The memory controller includes a memory interface queue, an arbitrator, at least one replay queue, refresh control circuitry, and replay control circuitry. The memory interface queue includes an output for connecting to a memory channel adapted to connect to at least one dynamic random access memory (DRAM). The arbitrator is connected to the memory interface queue and selects incoming memory commands and places them in the memory interface queue, thereby causing the memory commands to be transmitted through the memory channel. The replay queue stores memory access commands placed in the memory interface queue. The refresh control circuitry is connected to the arbitrator and is operable to monitor an activation counter that counts the number of activation commands sent to a memory region via the memory channel, and in response to the activation counter exceeding a specified threshold, signals to the arbitrator that an emergency refresh command should be sent. The replay control circuitry detects that an error of a specified type has occurred and, in response to the error, initiates a recovery sequence, including retransmitting the selected memory command from the at least one replay queue.

[0011] A method includes selectively placing memory commands in a memory interface queue, transferring the memory commands from the memory interface queue to a memory channel connected to at least one dynamic random access memory (DRAM), and storing a copy of the transferred memory commands in a replay queue. The method counts the number of active commands sent to a memory region of the DRAM via the memory channel. In response to the number of active commands exceeding a specified threshold, the method signals an arbitrator that an urgent refresh command should be sent to that memory region. In response to detecting an error of a specified type, the method initiates a recovery sequence, including retransmitting the selected memory commands from the replay queue. In response to a specified error condition in the recovery sequence, the method checks if there is an urgent refresh command pending at the arbitrator, and if so, interrupts the recovery sequence and allows the sending of the urgent refresh command.

[0012] A data processing system includes: a data processor; a data texture connected to the data processor; and a memory controller connected to the data texture for fulfilling memory requests from the data processor. The memory controller includes a memory interface queue, an arbitrator, at least one replay queue, refresh control circuitry, and replay control circuitry. The memory interface queue includes an output for connecting to a memory channel adapted to connect to at least one dynamic random access memory (DRAM). The arbitrator is connected to the memory interface queue for selecting incoming memory commands and placing the memory commands in the memory interface queue, thereby causing the memory commands to be transmitted through the memory channel. The replay queue stores memory access commands placed in the memory interface queue. The refresh control circuitry is connected to the arbitrator and operable to monitor an activation counter that counts the number of activation commands sent to a memory region via the memory channel, and in response to the activation counter exceeding a specified threshold, signals to the arbitrator that an emergency refresh command should be sent. The replay control circuitry detects that an error of a specified type has occurred and, in response to the error, initiates a recovery sequence, including retransmitting the selected memory command from the at least one replay queue.

[0013] Figure 1A block diagram illustrates an Accelerated Processing Unit (APU) 100 and a memory system 130 known in the prior art. The APU 100 is an integrated circuit suitable for use as a processor in a host data processing system and typically includes a Central Processing Unit (CPU) core complex 110, a graphics core 120, a set of display engines 122, a memory management center 140, a data texture 125, a set of peripheral controllers 160, a set of peripheral bus controllers 170, and a System Management Unit (SMU) 180. As those skilled in the art will appreciate, the APU 100 may not have all of these elements present in each embodiment and may also have additional elements included therein. Furthermore, the APU 100 may include, for example, one or more integrated circuits in a system.

[0014] CPU core complex 110 includes CPU core 112 and CPU core 114. In this example, CPU core complex 110 includes two CPU cores, but in other embodiments, CPU core complex 110 may include any number of CPU cores. Each of CPU cores 112 and 114 is bidirectionally connected to a system management network (SMN) and a data texture 125 forming a control texture, and is able to provide memory access requests to the data texture 125. Each of CPU cores 112 and 114 may be a monolithic core, or may further be a core complex of two or more monolithic cores having caches sharing certain resources.

[0015] The graphics core 120 is a high-performance graphics processing unit (GPU) capable of performing graphics operations such as vertex processing, fragment processing, shading, and texture blending in a highly integrated and parallel manner. The graphics core 120 is bidirectionally connected to the SMN and data texture 125 and can provide memory access requests to the data texture 125. In this regard, the APU 100 can support a unified memory architecture in which the CPU core complex 110 and the graphics core 120 share the same memory space, or a memory architecture in which the CPU core complex 110 and the graphics core 120 share a portion of the memory space, while the graphics core 120 also uses a private graphics memory that the CPU core complex 110 cannot access.

[0016] Display engine 122 renders and rasterizes objects generated by graphics core 120 for display on the monitor. Graphics core 120 and display engine 122 are bidirectionally connected to a common memory management hub 140 for unified translation into appropriate addresses in memory system 130, and memory management hub 140 is bidirectionally connected to data texture 125 for generating such memory accesses and receiving read data returned from memory system.

[0017] Data texture 125 includes a lever switch for routing memory access requests and memory responses between any memory access agent and memory management hub 140. The data texture also includes a system memory map defined by the Basic Input / Output System (BIOS) for determining the destination of memory accesses based on system configuration, and buffers for each virtual connection.

[0018] Peripheral controller 160 includes a Universal Serial Bus (USB) controller 162 and a Serial Advanced Technology Attachment (SATA) interface controller 164, each of which is bidirectionally connected to the system hub 166 and the SMN bus. These two controllers are merely examples of peripheral controllers that can be used with the APU 100.

[0019] The peripheral bus controller 170 includes a system controller or "southbridge" (SB) 172 and a peripheral component interconnect (PCIe) controller 174, each of which is bidirectionally connected to an input / output (I / O) hub 176 and the SMN bus. The I / O hub 176 is also bidirectionally connected to a system hub 166 and a data texture 125. Thus, for example, the CPU core can program registers in the USB controller 162, SATA interface controller 164, SB 172, or PCIe controller 174 via access routed through the I / O hub 176 to the data texture 125. The APU 100's software and firmware are stored in a system data drive or system BIOS memory (not shown), which can be any of a variety of non-volatile memory types, such as read-only memory (ROM), electrically erasable programmable flash ROM (EEPROM), etc. Typically, the BIOS memory is accessed via the PCIe bus, and the system data drive via the SATA interface.

[0020] The SMU 180 is a local controller that controls the operation of resources on the APU 100 and synchronizes communication between these resources. The SMU 180 manages the power-on sequence of the various processors on the APU 100 and controls multiple off-chip devices via reset, enable, and other signals. The SMU 180 includes one or more clock sources (not shown), such as phase-locked loops (PLLs), to provide clock signals to each component of the APU 100. The SMU 180 also manages the power of various processors and other functional blocks and can receive measured power consumption values ​​from CPU cores 112 and 114 and graphics core 120 to determine appropriate power states.

[0021] In this implementation, the memory management hub 140 and its associated physical interfaces (PHYs) 151 and 152 are integrated with the APU 100. The memory management hub 140 includes memory channels 141 and 142 and a power engine 149. Memory channel 141 includes a host interface 145, a memory channel controller 143, and a physical interface 147. The host interface 145 bidirectionally connects the memory channel controller 143 to the data texture 125 via a Serial Presence Detection Link (SDP). The physical interface 147 bidirectionally connects the memory channel controller 143 to the PHY 151 and conforms to the DDR PHY Interface (DFI) specification. Memory channel 142 includes a host interface 146, a memory channel controller 144, and a physical interface 148. The host interface 146 bidirectionally connects the memory channel controller 144 to the data texture 125 via another SDP. The physical interface 148 bidirectionally connects the memory channel controller 144 to the PHY 152 and conforms to the DFI specification. Power engine 149 is bidirectionally connected to SMU 180 via SMN bus, to PHYs 151 and 152 via APB, and also bidirectionally connected to storage channel controllers 143 and 144. PHY 151 has a bidirectional connection to storage channel 131. PHY 152 has a bidirectional connection to storage channel 133.

[0022] Memory management hub 140 is an instantiation of a memory controller with two memory channel controllers, and uses a shared power engine 149 to control the operation of both memory channel controllers 143 and 144 in a manner described further below. Each of the memory channels 141 and 142 can be connected to existing DDR memories (such as DDR version 4, low-power DDR4 (LPDDR 4), graphics DDR version 5 (gPDDR 5)) and high-bandwidth memory (HBM), and is adaptable to future memory technologies. These memories provide high bus bandwidth and high-speed operation. Simultaneously, they also provide low-power modes to save power in battery-powered applications such as laptops, and provide built-in thermal monitoring.

[0023] Memory system 130 includes memory channels 131 and 133. Memory channel 131 includes a set of dual in-line memory modules (DIMMs) connected to a DDRx bus 132, including representative DIMMs 134, 136, and 138, which in this example correspond to individual memory columns. Similarly, memory channel 133 includes a set of DIMMs connected to a DDRx bus 129, including representative DIMMs 135, 137, and 139.

[0024] The APU 100 operates as the central processing unit (CPU) of the host data processing system and provides a variety of buses and interfaces available in modern computer systems. These interfaces include two dual data rate (DDRx) memory channels, a PCIe root complex for connecting to a PCIe link, a USB controller for connecting to a USB network, and an interface to SATA mass storage devices.

[0025] The APU 100 also implements various system monitoring and power-saving functions. Specifically, one system monitoring function is thermal monitoring. For example, if the APU 100 gets hot, the SMU 180 can reduce the frequency and voltage of CPU cores 112 and 114 and / or graphics core 120. If the APU 100 becomes overheated, it can be completely shut down. The SMU 180 can also receive thermal events from external sensors via the SMN bus, and in response, the SMU 180 can reduce the clock frequency and / or supply voltage.

[0026] Figure 2 The diagram illustrates a suitable approach for applications similar to... Figure 1 The memory controller 200 used in the APU. The memory controller 200 typically includes a memory channel controller 210 and a power controller 250. The memory channel controller 210 typically includes an interface 212, a memory interface queue 214, a command queue 220, an address generator 222, a content-addressable memory (CAM) 224, replay control logic 231 including a replay queue 230, a refresh logic block 232, a timing block 234, a page table 236, an arbitrator 238, an error correction code (ECC) checking circuit 242, an ECC generation block 244, and a data buffer 246.

[0027] Interface 212 has a first bidirectional connection to data texture 125 via an external bus and has an output. In memory controller 200, this external bus is compatible with Advanced Extensible Interface Version 4 (referred to as AXI4) as specified by ARM Holdings, PLC of Cambridge, England, but may be other types of interfaces in other embodiments. Interface 212 translates memory access requests from a first clock domain called the FCLK (or MEMCLK) domain to a second clock domain called the UCLK domain within memory controller 200. Similarly, memory interface queue 214 provides memory access from the UCLK domain to the DFICLK domain associated with the DFI interface.

[0028] Address generator 222 decodes the addresses of memory access requests received from data texture 125 via the AXI4 bus. The memory access request includes an access address in a normalized format within the physical address space. Address generator 222 converts the normalized address into a format that can be used to address the actual memory devices in memory system 130 and to efficiently schedule related accesses. This format includes a region identifier that associates the memory access request with a specific memory column, row address, column address, bank address, and bank group. At startup, the system BIOS queries the memory devices in memory system 130 to determine their size and configuration and programs a set of configuration registers associated with address generator 222. Address generator 222 uses the configuration stored in the configuration registers to convert the normalized address into an appropriate format. Command queue 220 is a queue of memory access requests received from memory access agents in APU 100, such as CPU cores 112 and 114 and graphics core 120. Command queue 220 stores the address field decoded by address generator 222, as well as other address information that allows arbitrator 238 to efficiently select memory accesses, including access type and quality of service (QoS) identifiers. CAM 224 includes information on implementing ordering rules such as write-after-write (WAW) and read-after-write (RAW) ordering rules.

[0029] Error Correction Code (ECC) generation block 244 determines the ECC of the write data to be sent to the memory. ECC checking circuit 242 checks the received ECC against the incoming ECC.

[0030] Replay queue 230 is a temporary queue for storing selected memory accesses chosen by arbitrator 238, which are awaiting responses such as address and command parity responses. Replay control logic 231 accesses ECC checking circuit 242 to determine whether the returned ECC is correct or indicates an error. Replay control logic 231 initiates and controls a recovery sequence in which accesses are replayed in the event of a parity or ECC error in one of these cycles. The replayed commands are placed in memory interface queue 214.

[0031] Refresh control logic 232 includes a state machine for various power-down, refresh, and termination resistor (ZQ) calibration cycles, which are generated separately from normal read and write memory access requests received from the memory access agent. For example, if a memory bank is in a pre-charge power-down state, it must be periodically woken up to run a refresh cycle. Refresh control logic 232 periodically and in response to specified conditions generates refresh commands to prevent data errors caused by charge leakage from storage capacitors in memory cells within the DRAM chip. The memory region is a memory bank in some embodiments and a memory sub-bank in others, as discussed further below. Refresh control logic 232 also generates refresh commands, including both refresh (REF) commands and refresh management (RFM) commands, where the RFM command directs the memory to perform refresh functions to mitigate row hammer problems, as described further below. Furthermore, refresh control logic 232 periodically calibrates ZQ to prevent mismatch of on-chip termination resistors due to thermal variations in the system.

[0032] Arbitrator 238 is bidirectionally connected to command queue 220 and is the core of memory channel controller 210. Arbitrator 238 improves efficiency by intelligently scheduling accesses to increase memory bus utilization. Arbitrator 238 uses timing block 234 to implement correct timing relationships by determining whether certain accesses in command queue 220 are eligible to be issued based on DRAM timing parameters. For example, each DRAM has a minimum specified time between activation commands, called "t". RC The timing block 234 maintains a set of counters that determine eligibility based on the timing parameters and other timing parameters specified in the JEDEC specification, and is bidirectionally connected to the replay queue 230. The page table 236 maintains status information about active pages in each bank and column of the storage channel of the arbitrator 238, and is bidirectionally connected to the replay queue 230. The arbitrator 238 includes an activation counter 248, which in this embodiment includes a counter for each storage region that counts the number of activation commands sent to the storage region via the storage channel. The arbitrator 238 is bidirectionally connected to the refresh control logic 232 to monitor refresh commands and guide refresh activity.

[0033] In response to receiving a write memory access request from interface 212, ECC generation block 244 calculates the ECC based on the write data. Data buffer 246 stores the write data and ECC of the received memory access request. When arbitrator 238 selects a corresponding write access for dispatch to the memory channel, the data buffer outputs the combined write data / ECC to memory interface queue 214.

[0034] The power controller 250 typically includes an interface 252 to an Advanced Scalable Interface Version 1 (AXI), an Advanced Peripheral Bus (APB) interface 254, and a power engine 260. Interface 252 has a first bidirectional connection to the SMN, which includes a function for receiving... Figure 2 The inputs and outputs of the event signal labeled “EVENT_n” are shown separately. APB interface 254 has inputs connected to the outputs of interface 252, and outputs for connecting to the PHY via APB. Power engine 260 has inputs connected to the outputs of interface 252, and outputs connected to the inputs of memory interface queue 214. Power engine 260 includes a set of configuration registers 262, a microcontroller (μC) 264, a self-refresh controller (SLFREF / PE) 266, and a reliable read / write timing engine (RRW / TE) 268. Configuration registers 262 are programmed via the AXI bus and store configuration information to control the operation of various blocks in memory controller 200. Therefore, configuration registers 262 have outputs connected to these blocks, which... Figure 2 Not shown in detail. The self-refresh controller 266 is an engine that allows manual refresh generation in addition to automatic refresh generation by the refresh control logic 232. The reliable read / write timing engine 268 provides a continuous stream of memory accesses to the memory or I / O device for purposes such as DDR interface maximum read latency (MRL) training and loopback testing.

[0035] The memory channel controller 210 includes circuitry that allows an arbiter to select memory accesses for assignment to an associated memory channel. To make the desired arbitration decision, address generator 222 decodes address information into pre-decoded information, including the memory column, row, column, bank, and bank groups in the memory system, and command queue 220 stores the pre-decoded information. Configuration register 262 stores configuration information to determine how address generator 222 decodes the received address information. Arbitrator 238 uses the decoded address information, timing eligibility information indicated by timing block 234, and active page information indicated by page table 236 to efficiently schedule memory accesses while adhering to other criteria such as Quality of Service (QoS) requirements. For example, arbitrator 238 prioritizes access to open pages to avoid the overhead of precharge and activation commands required to change memory pages, and hides overhead access to a bank by interleaving overhead access to one bank with read and write access to another bank. Especially during normal operation, the arbitrator 238 typically keeps pages open in different storage banks until these pages need to be precharged, and then selects a different page. In some implementations, the arbitrator 238 determines the eligibility of a command selection based at least on the corresponding value of the activation counter 248 of the target storage region for the corresponding command.

[0036] Figure 3 This is a flowchart of process 300 for handling refresh management according to some implementation schemes. In some implementation schemes, process 300 is controlled by refresh control logic 232 (…). Figure 2 The refresh control logic 232 is executed, or in other embodiments, by the memory controller digital logic or a controller with similar functionality. In this embodiment, refresh control logic 232 is connected to arbitrator 238 and operable to monitor activation counter 248, which counts the number of activation commands sent to the memory region via the memory channel, as shown at block 302. The memory region is a memory bank in some embodiments, but in other embodiments it is a memory sub-bank, as discussed further below. Process 300 is repeated for each memory region. At block 304, if a refresh (REF) command is issued to the corresponding monitored region, process 300 manages the counter by decrementing the counter by a first specified amount. Block 304 considers "per-bank" REF commands pointing to a specific memory bank, and "all-bank" REF commands pointing to all banks within a specific memory bank. For example, in one embodiment, in response to a REF command being issued to a memory bank, whether it is a per-bank REF or an all-bank REF, the activation counter of the memory bank is decremented by 50. Therefore, for all affected memory banks, all memory bank REF commands cause multiple activation counters to decrement. As shown in box 306, when an RFM command is issued to a memory region, process 300 also considers the issuance of the refresh management (RFM) command by decrementing the counters by a second specified amount. For example, in one embodiment, in response to an RFM command being issued to a memory bank, the activation counter of the memory bank is decremented by 100. As will be understood, the amount decremented (or incremented) is exemplary and other values ​​may be used. Furthermore, the first amount, the amount per region or per memory bank as described with reference to the exemplary embodiment, and / or the second amount (all memory bank amounts in the exemplary embodiment) may be dynamically changed to reflect various characteristics of the memory device—e.g., aging, voltage, temperature, etc.—that may affect the frequency at which the memory needs to be refreshed.

[0037] When activation counter 248 is updated via boxes 302, 304, and 306, process 300 monitors the value, as shown in boxes 308-320, and in addition to the normal REF commands issued to the storage area, these boxes also take various refresh management actions. Typically, process 300 is used to provide some type of refresh command (REF or RFM), preferably controlled by refresh control logic 232 (…). Figure 2The REF command is created by the periodic refresh function of the storage region. This priority is achieved by determining whether a pending refresh (REF) command for the storage region is currently held at the refresh control circuitry in response to an activation counter that is above an intermediate management threshold but below a maximum management threshold. If not, a refresh management (RFM) command is sent to the storage region. If so, a pending REF command is allowed to be issued without an RFM command. In response to an activation counter equal to or above the maximum management threshold, the process causes an RFM command to be scheduled for the storage region and prevents any new activation commands from being scheduled to the storage region until either an RFM command or a pending REF command is scheduled. Different implementations use different logical procedures to achieve this.

[0038] In the depicted process 300, box 308 monitors the value of activation counter 248. If, at box 310, the value is equal to or higher than the maximum management threshold, process 300 proceeds to box 316, where the process checks if any REF commands for the storage region are pending at arbitrator 238. Box 316 checks both "per-bank" and "all-bank" REF commands applicable to the considered bank. If any type of REF command covers one of the considered banks pending, the process proceeds to box 318, where it signals the arbitrator to prioritize the pending REF command in order to request its scheduling and release. If no pending REF command exists at box 316, process 300 proceeds to box 320, where the process creates a new RFM command to be scheduled by the arbitrator. Following either block 318 or 320, process 300 proceeds to block 322, where the process prevents any activation command from being scheduled at arbitrator 238 until a newly created RFM command is scheduled or a pending REF is scheduled. In some alternative embodiments, the refresh control circuitry is further operable to double the refresh rate of the memory region in response to a specified condition, such as exceeding a maximum threshold, activating counter 248 at block 310 until the specified condition is remedied. This rate increase can be performed in addition to or instead of creating an RFM command at block 320. In some embodiments, the refresh control logic can be configured to include the rate increase.

[0039] If the activation counter 248 at box 310 is not higher than the maximum management threshold, then box 314 checks whether the activation counter 248 is equal to or higher than the intermediate management threshold. If not, then box 315 simply returns to box 308 to continue monitoring the activation counter. If yes, then process 300 proceeds to box 324, where the process checks whether REF commands for the storage region are pending at arbitrator 238. Box 316 checks the “per-bank” and “all-bank” REF commands applied to the considered bank. If any type of REF command covers one of the considered banks pending, then the process proceeds to box 326, where the process signals the arbitrator to prioritize the pending REF command to request its scheduling and release. If not, then process 300 proceeds to box 328, where the process creates a new RFM command to be scheduled by the arbitrator.

[0040] Although the depicted process blocks are shown in sequence, this sequence is not limiting, and the depicted logical functions or their logical equivalents are typically implemented by various digital logic circuits operating in parallel. In various embodiments, the digital logic circuits perform activation counter monitoring in various ways, such as by responding to changes in the activation counter or by repeatedly comparing the activation counter value with one or both of an intermediate threshold and a maximum threshold. Monitoring continues at block 308 after each depicted branch of the logical function has completed.

[0041] The intermediate management threshold and the maximum management threshold are preferably adjustable to allow the memory controller to work well with different DRAM modules from various manufacturers, for which REF commands and RFM commands typically vary in their implementation. In some implementations, it is permissible to set the intermediate management threshold and the maximum management threshold to the same value to implement a simplified version of the monitoring process. Setting these two threshold values ​​to be equal preferably disables the maximum management threshold logic (block 310) and allows the logic implementing the intermediate management threshold comparison (blocks 314, 315, 324, 326, and 328) to handle cases where the counter exceeds the equality threshold value. Thus, such implementations are used to prioritize pending REF commands when they exist, rather than creating a new RFM command. This prioritization generally improves efficiency because REF commands are typically faster than RFM commands in various DRAM module implementations.

[0042] In various implementations, the storage region for which the activation counters are monitored is a memory bank or a sub-memory. When the storage region is a sub-memory of a memory bank, the refresh control circuitry is operable to monitor multiple activation counters of the corresponding multiple sub-memories of the memory bank and apply REF and RFM commands at the bank level. Such commands cause all sub-memory activation counters of the sub-memories within the memory bank to be updated. Similarly, all bank REF commands cause all sub-memory activation counters of the sub-memories within the corresponding memory column to be updated. Thus, process 300 is operable to monitor activation counters at the granularity level of multiple sub-memories and allows or causes REF and RFM commands to be issued at the granularity level of the selected memory bank. The refresh control circuitry may be configured to provide activation counters for either memory banks or sub-memories, and the refresh management process may be adjusted to take into account either memory banks or sub-memories.

[0043] Figure 4 This is a flowchart 400 of a process for replaying commands according to some implementation schemes. In the illustrated implementation scheme, the depicted process is controlled by replay control logic 231 ( Figure 2 This is managed by [the system], but in other implementations, it can be managed by another suitable digital logic circuit implementing the described function. The process begins at block 402, where a copy of the outgoing command is placed in the replay queue (230, ...). Figure 2 The command is kept in the replay queue until it is executed without errors. At box 404, when a command is executed without errors, it is removed from the replay queue. This sequence of placing commands in the replay queue until they are executed continues until an error requiring sequence recovery is detected, as shown in box 406.

[0044] The process at block 406 detects whether an error requiring sequence recovery exists at one of the DRAM modules (e.g., DIMMs) or on the memory channel. When such an error is detected, the process proceeds from block 406 to block 408, where the error at the DRAM module is cleared. Block 408 includes: if a parity error is detected, clearing the parity error at each DRAM module on the memory channel; if a write or read ECC error is detected at block 406, clearing the write or read ECC state at block 408. In some embodiments, if the process cannot determine the error type, errors of both types are cleared to ensure complete clearing of the error state.

[0045] At box 410, the memory controller resets the PHY's First-In-First-Out (FIFO) buffer. If the Multipurpose Register (MPR) mode is currently active, it is disabled before the reset. Box 410 may also include a request to write credits, if necessary. If the MPR mode was active before the recovery sequence, it is then re-enabled to place the DIMM under the same conditions it was in when the error occurred to replay the necessary commands. At this point, the recovery sequence has been reset and the channels and portions of the DIMM have been cleared. However, before sending commands to implement the recovery sequence (which occupies the command bus for a period of time), the process handles refresh commands to avoid violating the maximum time limit between REF commands, and activates command processing based on count, handling RFM commands that may have been generated for a specific region.

[0046] To handle such commands, the procedure at box 412 checks for any pending urgent or deferred refresh commands before retransmitting the commands in the recovery sequence. In this implementation, urgent refresh commands are... Figure 3 Any of the REF or RFM commands generated or prioritized in the refresh management process (such as at boxes 312, 320, and 328). Other implementations use... Figure 3 Different processes are used to provide emergency refresh commands. For example, in some implementations, the emergency refresh command is a REF or RFM command generated in response to an unexpected value for a memory region (such as a memory bank, sub-memory bank, or line) at an activation counter. Other implementations may not use an activation counter to generate the emergency refresh command, but instead monitor refresh conditions created by the underlying periodic refresh cycle and insert the emergency refresh command when needed. The refresh control circuitry includes outputs, or flags or similar indicators, which send signals to the arbitrator 238 (…). Figure 2 The replay control circuit 231 signals that a particular refresh command is urgent. Typically, this signal indicates that the command must be sent before any further activation commands are sent to the affected memory area. Deferred refresh commands are pending REF commands, which are postponed such that if the recovery cycle continues for too long, the maximum REF-to-REF interval for the memory area may be violated. For example, some DDR standards specify a maximum interval between refreshes of 5 times the defined time interval tREF1.

[0047] If an urgent refresh command or a deferred refresh command exists at box 412, the process interrupts the recovery sequence at box 414 and allows the arbitrator to transmit the urgent refresh command and / or the deferred refresh command. Multiple refresh commands can be transmitted at this box for different storage regions. If no urgent refresh command is pending at box 412, the process proceeds directly to box 416 to continue the recovery sequence.

[0048] Next, at box 418, the process replays commands from the replay queue, starting with the selected commands. Typically, commands are replayed in the exact order they were originally transmitted. The replayed commands are placed in the memory interface queue for transmission to the DRAM. In some implementations, the selected commands include any read, write, and MPR-related commands. As the recovery sequence replays commands, at box 420, the process monitors for errors. If an error message is received during the recovery sequence, the process at box 420 determines whether the error is of a specified type that would require restarting the recovery sequence. For example, in this implementation, a command parity error would require restarting the recovery sequence. Other types of errors may also satisfy specified conditions. If the error condition is not satisfied, the process at box 420 returns to box 418 and continues retransmitting commands in the recovery sequence.

[0049] If the specified error state exists at box 420, it represents a second or additional error in addition to the original error detected at box 406. This additional error causes a “recursive” recovery sequence, in which the recovery sequence restarts. In some cases, such a restart can delay the refresh management process from providing the appropriate refresh command. In some cases, if an error occurs before all commands in the replay queue have been transmitted, the recovery sequence may have to restart more than once. The depicted process checks for urgent refresh commands and deferred refresh commands whenever the recovery sequence is restarted (box 412). When the transmission of all commands in the replay queue has been completed and the commands have been executed, the recovery sequence is considered complete, and the memory controller ends the recovery sequence and returns to its normal operating state, where the arbitrator selects the command to be transmitted.

[0050] Figures 5-7 It is a series of illustrations illustrating parts of the recovery sequence based on some implementation schemes. Figure 5 This is illustration 500, illustrating an example scenario prior to the start of the recovery sequence. Arbitrators such as arbitrator 238 ( Figure 2 The command selected from the command queue is used to place the command in the memory interface queue. Figure 5 The operation is depicted by arrow 501, which shows commands placed in the queue in the order selected by the arbitrator. Arrow 502 depicts a copy of the command being placed in the replay queue. Arrow 503 depicts commands being transferred from the queue to the DRAM module via the PHY layer and memory channels.

[0051] Figure 6 It is shown Figure 5The scenario continues in Figure 600 with arrow 504, which indicates an error message indicating a problem such as a command parity error or an ECC or CRC check error, suggesting an uncorrectable error has occurred on the channel. This allows the recovery sequence to begin as described above. Commands from the replay queue are then replayed in the order depicted by arrow 505, showing the commands added to the queue from the replay queue. These commands are then transmitted through the channel, as shown by arrow 506.

[0052] Figure 7 This is illustration 700 showing a later scenario where a specified error condition has occurred during the recovery sequence, necessitating a restart of the recovery sequence. Upon restart, an emergency refresh command is to be transmitted, as indicated by arrow 507. The emergency refresh command is placed in a queue for transmission before any commands in the restarted recovery sequence are transmitted, as indicated by arrow 508. Commands in the replay queue are then added to the queue for transmission, as indicated by arrow 509.

[0053] Although in this implementation, the emergency refresh command can be transmitted when an error condition requires the sequence to restart, in other implementations, the emergency refresh command is checked (box 412). Figure 4 The check can be performed at additional points in the process or at other points in the process. For example, the check can occur at the beginning of the recovery sequence, or if the replay queue is large enough to guarantee further checks, a periodic check for an urgent refresh can occur during the recovery sequence without error conditions, such as the error conditions in box 420.

[0054] Figure 2 The memory controller 200 or any part thereof (such as arbitrator 238 and refresh control circuitry 232) may be described or represented by a computer-accessible data structure in the form of a database or other data structure that can be read by a program and is used directly or indirectly for manufacturing integrated circuits. For example, the data structure may be a behavioral-level description or register-transfer-level (RTL) description of hardware functionality in a high-level design language (HDL) such as Verilog or VHDL. The description may be read by a synthesis tool, which may synthesize the description to produce a netlist including a list of gates from the synthesis library. The netlist includes gate sets, which also represent the functionality of the hardware comprising the integrated circuit. The netlist may then be placed and routed to produce a dataset describing the geometry to be applied to a mask. The mask may then be used in various semiconductor manufacturing steps to produce the integrated circuit. Alternatively, the database on the computer-accessible storage medium may be a netlist (with or without a synthesis library), a dataset (as needed), or Graphical Data System (GDS) II data.

[0055] While specific embodiments have been described, various modifications to these embodiments will be apparent to those skilled in the art. For example, the internal architecture of the memory channel controller 210 and / or power engine 250 may vary in different embodiments. The memory controller 200 may interface with other types of memory besides DDRx, such as high-bandwidth memory (HBM), RAMbus DRAM (RDRAM), etc. While the illustrated embodiments show each memory storage column corresponding to a single DIMM or SIMM, in other embodiments, each module may support multiple storage columns. Still other embodiments may include other types of DRAM modules or DRAM not included in a particular module, such as DRAM mounted to a host motherboard. Therefore, the appended claims are intended to cover all modifications of the disclosed embodiments that fall within the scope of the disclosed embodiments.

Claims

1. A memory controller, comprising: an arbiter to select memory commands and cause the selected memory commands to be transmitted over a memory channel; and at least one replay queue to store memory access commands transmitted over the memory channel; and a refresh control circuit coupled to the arbiter and operable to monitor an activation counter that counts a number of activation commands sent to a memory region over the memory channel and, in response to the activation counter being above a specified threshold, signal the arbiter that an emergency refresh command should be sent; and a replay control circuit to detect that a specified type of error has occurred and, in response to the error, initiate a recovery sequence that includes retransmission of selected memory commands from the at least one replay queue, wherein the replay control circuit is further operable to, in response to a specified error condition in the recovery sequence, interrupt the recovery sequence and allow the emergency refresh command to be sent based on whether the emergency refresh command is pending at the arbiter.

2. The memory controller of claim 1, wherein the replay control circuit is further operable to cause the refresh control circuit to increment the activation counter in response to an error in transmitting a refresh command.

3. The memory controller of claim 1, wherein the specified error condition comprises a command parity error during the recovery sequence.

4. The memory controller of claim 1, wherein the specified error condition comprises a restart of the recovery sequence.

5. The memory controller of claim 1, wherein the specified error condition comprises at least partial repetition of the recovery sequence.

6. The memory controller of claim 1, wherein the emergency refresh command is one of a refresh (REF) for at least a portion of the memory region, or a refresh management command (RFM) for the memory region.

7. The memory controller of claim 1, wherein the memory region is one of a memory bank and a sub-bank.

8. The memory controller of claim 7, wherein when the memory region is a sub-bank of a memory bank, the refresh control circuit is operable to monitor a plurality of activation counters for a respective plurality of sub-banks of the memory bank.

9. The memory controller of claim 8, wherein the replay control circuit is operable to replace a REF command for a specified sub-bank with a REF command for the memory bank that contains the specified sub-bank.

10. The memory controller of claim 1, wherein the refresh control circuit is further operable to decrement the activation counter by a first specified amount in the event a REF command is issued to the memory region.

11. A method, comprising: selectively transmitting memory commands to a memory channel coupled to at least one dynamic random access memory (DRAM), and storing copies of the transmitted memory commands in a replay queue; counting a number of activate commands sent through the memory channel to a memory region of the DRAM; signaling to an arbiter that an emergency refresh command should be sent to the memory region in response to the number of activate commands being above a specified threshold; detecting that a specified type of error has occurred, and in response to the error, initiating a recovery sequence that includes retransmitting selected memory commands from the replay queue; and in response to a specified error condition in the recovery sequence, checking whether an emergency refresh command is pending at the arbiter, and if so, interrupting the recovery sequence and allowing the emergency refresh command to be sent.

12. The method of claim 11, further comprising incrementing the count of activate commands in response to an error in transmitting a refresh command.

13. The method of claim 11, wherein the specified error condition comprises a command parity error during the recovery sequence.

14. The method of claim 11, wherein the specified error condition comprises a restart of the recovery sequence.

15. A data processing system comprising: a data processor; a memory controller to fulfill memory requests from the data processor, the memory controller comprising: an arbiter coupled to a memory interface queue to select memory commands and cause the selected memory commands to be transmitted through a memory channel; and at least one replay queue to store memory commands placed in the memory interface queue; and a refresh control circuit coupled to the arbiter and operable to monitor an activate counter that counts a number of activate commands sent through the memory channel to a memory region, and in response to the activate counter being above a specified threshold, signal to the arbiter that an emergency refresh command should be sent; and a replay control circuit to detect that a specified type of error has occurred, and in response to the error, initiate a recovery sequence that includes retransmitting selected memory commands from the at least one replay queue, wherein the replay control circuit is further operable to, in response to a specified error condition in the recovery sequence, interrupt the recovery sequence and allow the emergency refresh command to be sent based on whether an emergency refresh command is pending at the arbiter.

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