A disturbance-free redundant control system for servo units

Abstract

The present invention discloses a servo unit non-disturbance redundant control system. The disclosed system includes a control circuit CPUA, a control circuit CPUB, a machine cut arbitration circuit, an output enable circuit A and an output enable circuit B circuit; the control circuit CPUA and the control circuit CPUB output the unit control signal to the output enable circuit A and the output enable circuit B respectively according to the working condition of the unit; the machine cut arbitration circuit determines which control signal is on duty according to the self-checking signal of the control circuit CPUA and the control circuit CPUB, and outputs the judgment result to the output enable circuit A or the output enable circuit B; the output enable circuit A or the output enable circuit B enables the driving unit to work. The present invention solves the position disturbance problem in the switching process between the main control channel and the redundant channel in the redundant circuit through the dedicated servo controller hardware circuit and control strategy design, realizes the smooth adjustment of the engine thrust, and greatly improves the reliability of the engine operation.

Description

Technical Field

[0001] The invention relates to a servo unit control technology, and in particular to a servo unit non-disturbance redundant control system.

[0002] Background

[0003] The thrust regulation servo control system of a high-thrust liquid rocket engine includes a servo controller and a servo unit. The servo controller is composed of a control circuit and a drive circuit; the servo unit is composed of a dual-winding permanent magnet synchronous motor, a dual-way motor rotary transformer, a dual-way unit rotary transformer, a power-off brake and a reducer. The servo controller controls the position loop of the servo unit, thereby adjusting the opening of the flow regulator to achieve thrust regulation of the high-thrust liquid rocket engine.

[0004] The control accuracy of the servo control system over the servo unit has become the key guarantee for the thrust control of the liquid rocket engine. At the same time, the elimination of the servo unit position disturbance during the redundant switching process is an important manifestation of improving the control reliability and smooth thrust regulation of the liquid rocket engine.

[0005] At present, the thrust regulation servo controller usually adopts a dual-redundancy design. When the main control channel and the redundant channel are hot-switched, the servo unit will still have certain disturbances in position control, especially during load testing. As the load torque increases, the position disturbance becomes more obvious. Large position disturbances will cause thrust fluctuations during the engine ignition process, seriously affecting the success of the engine's ignition (hot) test or launch. Summary of the invention

[0006] In view of the defects or shortcomings of the prior art, the present invention provides a disturbance-free redundant control system for a servo unit, wherein the motor in the servo unit outputs two motor resolver signals, namely, motor resolver signal A and motor resolver signal B; the servo unit outputs two unit resolver signals, namely, unit resolver signal A and unit resolver signal B.

[0007] The servo unit disturbance-free redundant control system provided by the present invention comprises a control circuit CPUA, a control circuit CPUB, a machine cutting arbitration circuit, an output enabling circuit A and an output enabling circuit B;

[0008] The control circuit CPUA receives in real time the motor position signal A and the motor speed signal A obtained by decoding the motor resolver signal A, and the motor position signal B and the motor speed signal B obtained by decoding the motor resolver signal B, and simultaneously receives the unit position signal A obtained by decoding the unit resolver signal A and the unit position signal B obtained by decoding the unit resolver signal B; the control circuit CPUA calculates the received motor position signal A, motor speed signal A, motor position signal B, motor speed signal B, unit position signal A and unit position signal B in real time to obtain motor control data, and outputs the control data to the output enabling circuit A in real time;

[0009] The control circuit CPUA performs self-check on its own status in real time, and outputs a signal bundle CPUA_STATUS to the machine switching arbitration circuit in real time according to the self-check status, wherein the signal bundle CPUA_STATUS includes a software self-check signal BIT, a hardware reset signal RESET, a watchdog signal WDO and a power monitoring signal PFO;

[0010] The control circuit CPUA receives the position limit signal of the servo unit. When the servo unit reaches the limit, the control circuit CPUA outputs a signal to control the servo motor to stop working and inputs it to the output enabling circuit A;

[0011] The control circuit CPUB receives in real time the motor position signal B and the motor speed signal B decoded from the motor resolver signal B and the motor position signal A and the motor speed signal A decoded from the motor resolver signal A, and simultaneously receives the unit position signal B decoded from the unit resolver signal B and the unit position signal A decoded from the unit resolver signal A; the control circuit CPUB calculates the received motor position signal A, motor speed signal A, motor position signal B, motor speed signal B, unit position signal A and unit position signal B in real time to obtain motor control data; and outputs the control data to the output enabling circuit B in real time;

[0012] The control circuit CPUB performs self-check on its own status in real time, and outputs a signal bundle CPUB_STATUS to the machine switching arbitration circuit in real time according to the self-check status, wherein the signal bundle CPUB_STATUS includes a software self-check signal BIT, a hardware reset signal RESET and a watchdog signal WDO;

[0013] The control circuit CPUB receives the position limit signal of the servo unit. When the servo unit reaches the limit, the control circuit CPUB outputs a signal to control the servo motor to stop working and inputs it to the output enable circuit B;

[0014] The control circuit CPUA and the control circuit CPUB interact with each other in real time through the dual-port RAM to control data;

[0015] The machine switching arbitration circuit determines whether the control circuit CPUA is on duty or the control circuit CPUB is on duty according to the signal beam CPUA_STATUS and the signal beam CPUB_STATUS, and outputs the determination result to the output enabling circuit A or the output enabling circuit B;

[0016] The output enabling circuit A is used to enable the output of the control signal of the control circuit CPUA: when the control circuit CPUA is on duty, the control circuit CPUA outputs control data to control the operation of the servo unit; when the control circuit CPUA is not on duty, the control circuit CPUA does not output;

[0017] The output enable circuit B is used to enable the control signal output of the control circuit CPUB: when the control circuit CPUB is on duty, the control circuit CPUB outputs control data to control the operation of the servo unit; when the control circuit CPUB is not on duty, the control circuit CPUB does not output.

[0018] Further, the system of the present invention also includes a motor resolver decoding circuit A, a unit resolver decoding circuit A, a motor resolver decoding circuit B, and a unit resolver decoding circuit B;

[0019] The motor resolver decoding circuit A is used to decode the motor resolver signal A into a motor position signal A and a motor speed signal A, and transmit the signals to the control circuit CPUA and the control circuit CPUB;

[0020] The unit resolver decoding circuit A is used to decode the unit resolver signal A into a unit position signal A, and transmit it to the control circuit CPUA and the control circuit CPUB;

[0021] The motor resolver decoding circuit B is used to decode the motor resolver signal B into a motor position signal B and a motor speed signal B, and transmit the signals to the control circuit CPUA and the control circuit CPUB;

[0022] The unit resolver decoding circuit B is used to decode the unit resolver signal B into a unit position signal B, and transmit it to the control circuit CPUA and the control circuit CPUB.

[0023] Further, the system of the present invention also includes a motor drive circuit A, a brake control circuit, a Hall signal detection circuit and a motor drive circuit B;

[0024] The brake control circuit is used to receive the brake control signal sent by the output enable circuit A or the output enable circuit B, and control the brake to unlock, thereby ensuring the normal operation of the output shaft of the servo unit;

[0025] The Hall signal detection circuit is used to detect the limit signal of the servo unit and transmit the signal to the control circuit CPUA and the control circuit CPUB;

[0026] The motor driving circuit A is used to receive the motor driving signal sent by the control circuit CPUA and the control circuit CPUB to drive the servo unit.

[0027] The motor driving circuit B is used to receive the motor driving signal sent by the control circuit CPUA and the control circuit CPUB to drive the servo unit.

[0028] Further, the machine switching arbitration circuit includes a first NAND logic circuit, a first pull-up circuit, a second NAND logic circuit and a second pull-up circuit;

[0029] The first NAND logic circuit is used to judge whether the control circuit CPUA is on duty according to the signal beam CPUA_STATUS, and output the judgment result to the first pull-up circuit, and the first pull-up circuit outputs a signal indicating that the control circuit CPUA is on duty or the control circuit CPUA is not on duty to the output enable circuit A and the second NAND logic circuit according to the judgment result;

[0030] The second NAND logic circuit determines whether the control circuit CPUB is on duty based on the output signal of the first pull-up circuit and the signal beam CPUB_STATUS, and outputs the determination result to the second pull-up circuit. The second pull-up circuit outputs a signal indicating that the control circuit CPUB is on duty or not to the output enable circuit B based on the determination result.

[0031] Optionally, the output enable circuit A and the output enable circuit B independently use level conversion chips.

[0032] The present invention solves the problem of position disturbance in the switching process between the main control channel and the redundant channel in the redundant circuit through a dedicated servo controller hardware circuit and control strategy design, realizes the smooth regulation of the engine thrust, and greatly improves the reliability of the engine operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 Schematic diagram of the structure and working principle of the control system in an embodiment of the present invention. In the figure, the A / B drive analog quantity acquisition signal includes the three-phase current of the A / B winding, which are the U-phase current, the V-phase current, and the W-phase current. After the three-phase current is collected, it is input into the control circuit CPUA and the control circuit CPUB for the control closed loop of the A / B winding.

[0034] Figure 2 Schematic diagram of the structure principle of the machine switching arbitration circuit in an embodiment of the present invention.

[0035] Figure 3 To adopt Figure 1 and Figure 2The control system shown is a diagram showing the effect of controlling the thrust regulation servo unit of a large thrust liquid rocket engine. In the figure, the horizontal axis is time, in units of S; the vertical axis on the right is the speed, in units of rpm; and the vertical axis on the left is current, in units of A. DETAILED DESCRIPTION

[0036] Unless otherwise specified, the scientific and technical terms used herein are understood according to the knowledge of ordinary technicians in the relevant fields.

[0037] Figure 1 A specific control system of the present invention is shown, which includes a control circuit CPUA, a control circuit CPUB, a machine cutting arbitration circuit, an output enabling circuit A, an output enabling circuit B, a motor resolver decoding circuit A, a unit resolver decoding circuit A, a motor resolver decoding circuit B, a unit resolver decoding circuit B, a motor drive circuit A, a brake control circuit, a Hall signal detection circuit and a motor drive circuit B; wherein:

[0038] The control circuit CPUA receives the motor position and speed signals calculated by the motor resolver decoding circuit A through the SPI interface, and receives the motor position and speed signals calculated by the motor resolver decoding circuit B through the QEP interface; the control circuit CPUA receives the unit position signal calculated by the unit resolver decoding circuit A through the SPI interface, and receives the unit position signal calculated by the unit resolver decoding circuit B through the QEP interface; by calculating the positions of the resolver signals of the two motor channels and the two unit channels, the control circuit CPUA ensures the closed-loop control of the motor speed and the unit position under different conditions;

[0039] The control circuit CPUA receives the upper and lower limit signals of the servo unit detected by the Hall detection circuit;

[0040] The control circuit CPUA outputs a signal bundle CPUA_STATUS to the machine switching arbitration circuit in real time according to its own self-check status; in the specific scheme, the signal bundle CPUA_STATUS includes a software self-check signal BIT, a hardware reset signal RESET, a watchdog signal WDO and a power monitoring signal PFO; wherein, the software self-check BIT is the result of the software function self-check, and the output state is 1 when the software self-check is normal, and the output state is 0 when it is abnormal; the hardware reset signal RESET is the hardware reset state result, and the output state is 1 when the hardware is in reset, and the non-reset state is 0; the watchdog signal WDO is the state result of preventing the software from running away, and the output state is 1 when the software is running normally, and the output state is 0 when the software is abnormal; the power monitoring signal PFO is the state result of detecting whether the amplitude of the processor power supply voltage is normal, and the output state is 1 when the power supply amplitude is normal, and the output state is 0 when it is abnormal;

[0041] The control circuit CPUB receives the motor position and speed signals calculated by the motor resolver decoding circuit B through the SPI interface, and receives the motor position and speed signals calculated by the motor resolver decoding circuit A through the QEP interface; the control circuit CPUB receives the unit position signal calculated by the unit resolver decoding circuit B through the SPI interface, and receives the unit position signal calculated by the unit resolver decoding circuit A through the QEP interface; by calculating the positions of the resolver signals of the two motor channels and the two unit channels, the control circuit CPUB ensures the closed-loop control of the motor speed and the unit position under different conditions;

[0042] The control circuit CPUB receives the position limit signal detected by the Hall detection circuit;

[0043] The control circuit CPUB outputs a signal bundle CPUB_STATUS to the machine switching arbitration circuit in real time according to its own self-checking status; in the specific scheme, the signal bundle CPUB_STATUS includes a software self-checking signal BIT, a hardware reset signal RESET and a watchdog signal WDO; wherein, the software self-checking BIT is the result of the software function self-checking, and the output state is 1 when the software self-checking is normal, and the output state is 0 when it is abnormal; the hardware reset signal RESET is the hardware reset state result, and the output state is 1 when the hardware is reset, and the non-reset state is 0; the watchdog signal WDO is the state result output to prevent the software from running away, and the output state is 1 when the software is running normally, and the output state is 0 when the software is abnormal;

[0044] The control circuit CPUA and the control circuit CPUB exchange data through the dual-port RAM; in the specific scheme, the control circuit CPUA periodically outputs its own real-time closed-loop state to the dual-port RAM data interaction circuit through the signal beam CPUA_DRAM_BUS, and also periodically receives real-time closed-loop data from the control circuit CPUB through the signal beam CPUA_DRAM_BUS.

[0045] In the specific scheme, the dual-port RAM processor can use a data interaction RAM chip with dual parallel port communication (such as Shenzhen Guowei's shelf product SM7C027), the control circuit CPUA and the dual-port RAM processor realize data interaction through one parallel communication, and the control circuit CPUB and the dual-port RAM processor realize data interaction through another parallel communication. The data interaction content includes the closed-loop parameters of the real-time current loop, speed loop, and position loop, including real-time PID output parameters and closed-loop feedback parameters, to ensure that the backup processor can immediately take over the closed-loop control during the machine cutting process, eliminate the closed-loop establishment time of the backup processor, and realize true hot backup without control delay;

[0046] The machine switching arbitration circuit performs logic arbitration on the CPUA_STATUS status signal output by the control circuit CPUA and the CPUA_STATUS status signal output by the control circuit CPUB to determine which control circuit is fault-free and is on duty to perform the current control task:

[0047] If the control circuit CPUA is on duty at this time, the output signal activates the output enable circuit A, so that the control circuit CPUA drives the motor drive circuit A and the drive motor drive circuit B to control the action of the servo unit; the output enable circuit A enables the brake drive circuit to unlock the brake; at the same time, the detection status result signal of the other party is fed back to the control circuit CPUA to determine that CPUB is not on duty.

[0048] If the control circuit CPUB is on duty at this time, the corresponding signal is output to activate the output enable circuit B, so that the control circuit CPUB drives the motor drive circuit A and the drive motor drive circuit B to control the action of the servo unit; the output enable circuit B enables the brake drive circuit to unlock the brake; at the same time, the detection status result signal of the other party is fed back to the control circuit CPUB; to determine that CPUA is not on duty.

[0049] In the specific scheme, the working principle of the machine cutting arbitration circuit can be selected as follows: at the initial moment of power-on, the control circuit CPUA is first judged. If the control circuit CPUA is normal, the state detection signal CPUA_OK is set to 0, and CPUB_OK is set to 1, then the control circuit CPUA performs the work on duty; if the control circuit CPUA is abnormal, it jumps to the control circuit CPUB for judgment. If the control circuit CPUB is normal, the state detection signal CPUA_OK is set to 1, and CPUB_OK is set to 0, then the control circuit CPUB performs the work on duty; if the control circuit CPUB is abnormal, the logic judgment is stopped;

[0050] For the specific structure of the corresponding machine cutting arbitration circuit, see Figure 2 As shown, it includes a first NAND logic circuit, a first pull-up circuit, a second NAND logic circuit and a second pull-up circuit; the first NAND logic circuit is used to judge whether the control circuit CPUA is on duty according to the signal beam CPUA_STATUS, and output the judgment result to the first pull-up circuit, and the first pull-up circuit outputs a signal that the control circuit CPUA is on duty or the control circuit CPUA is not on duty to the output enable circuit A and the second NAND logic circuit according to the judgment result; the second NAND logic circuit judges whether the control circuit CPUB is on duty according to the output signal of the first pull-up circuit and the signal beam CPUB_STATUS, and outputs the judgment result to the second pull-up circuit, and the second pull-up circuit outputs a signal that the control circuit CPUB is on duty or the control circuit CPUB is not on duty to the output enable circuit B according to the judgment result;

[0051] When the four monitoring states of the control circuit A are all normal, that is, all outputs are 1, after the judgment of the NAND logic circuit, the final output result is 0. After the pull-up circuit, the final state of CPUA_OK is 0, indicating that the processor CPUA is working normally. At this time, the processor CPUA is on duty. Otherwise, if there is an abnormal output in the above four states (that is, the output is 0), the final state of CPUA_OK is 1, and the control circuit CPUA is transferred to the non-duty channel;

[0052] The three inspection status results of the control circuit CPUB and the CPUA_OK signal enter the NAND logic circuit for judgment at the same time. When the three CPUB_STATUS states are normal, the output is 1. At this time, when the CPUA_OK signal is 1 (indicating that the control circuit CPUA is abnormal and not on duty), the four monitoring states are judged by the NAND logic circuit, and the final output result is 0. After passing through the pull-up circuit, the final state of CPUB_OK is 0, indicating that the processor CPUB is working normally. At this time, the processor CPUB is working on duty. Otherwise, if there is an abnormal output in the above four states (that is, the output is 0), the final state of CPUB_OK is 1, and the control circuit CPUB is transferred to the off-duty channel;

[0053] The output enable circuit A is mainly used to realize the control signal output enable. The motor control data signal bundle CPUA_CONTROL output by the control circuit CPUA is output to the motor drive circuit A, the motor drive circuit B and the brake control circuit; specifically, when the control circuit CPUA is on duty (CPUA_OK is set to a low level), the level conversion function is activated to output the signal bundle CPUA_CONTROL to CPUA_DRIVE, and output each signal to the motor drive circuit A, the motor drive circuit B and the brake control circuit; when the control circuit CPUA is not on duty (CPUA_OK is set to a high level), the level conversion function is turned off to stop the output of the signal bundle CPUA_CONTROL.

[0054] In the specific scheme, the signal bundle CPUA_CONTROL includes the motor drive A-channel PWM signal (used to drive the A winding motor to operate), the motor drive B-channel PWM signal (used to drive the B winding motor to operate), the brake control signal (used to output the brake signal and unlock the brake), the motor drive A-channel IPM enable signal (used to enable the A-channel IPM to receive the A-channel PWM signal), and the motor drive B-channel IPM enable signal (used to enable the B-channel IPM to receive the B-channel PWM signal); accordingly, the CPUA_DRIVE signal bundle includes the A-channel and B-channel PWM signals after level conversion, the brake control signal, and the A-channel and B-channel IPM enable signals;

[0055] The output enable circuit B is mainly used to realize the control signal output enable function. The motor control data signal bundle CPUB_CONTROL output by the control circuit CPUB is output to the motor drive circuit A, the motor drive circuit B and the brake control circuit; specifically, when the control circuit CPUB is on duty (CPUB_OK is set to a low level), the level conversion function is activated, so that the signal bundle CPUB_CONTROL is output to CPUB_DRIVE, and each signal is output to the motor drive circuit A, the motor drive circuit B and the brake control circuit; when the control circuit CPUB is not on duty (CPUB_OK is set to a high level), the level conversion function is turned off, so that the signal bundle CPUB_CONTROL stops outputting;

[0056] In the specific scheme, the signal bundle CPUB_CONTROL includes the motor drive A-channel PWM signal (used to drive the A winding motor to operate), the motor drive B-channel PWM signal (used to drive the B winding motor to operate), the brake control signal (used to output the brake signal and unlock the brake), the motor drive A-channel IPM enable signal (used to enable the A-channel IPM to receive the A-channel PWM signal), and the motor drive B-channel IPM enable signal (used to enable the B-channel IPM to receive the B-channel PWM signal); accordingly, the CPUB_DRIVE signal bundle includes the A-channel and B-channel PWM signals after level conversion, the brake control signal, and the A-channel and B-channel IPM enable signals;

[0057] In some specific solutions, the output enable circuits A and B can use a level conversion chip (such as SN74ALVC164245 from ADI).

[0058] When the control system starts working, the control circuit CPUA and the control circuit CPUB reset the other party's resolver circuit through the interactive data RDC_A and RDC_B reset signals, respectively, to realize the closed loop of the servo unit; the control circuit CPUA and the control circuit CPUB realize the timing synchronization of the control process through the interactive data SYNIN and SYNOUT to ensure the consistency of the control timing.

[0059] In the closed-loop control process of the control system, the working modes include: CPUA working on duty, CPUB working on duty; the driving circuit working modes include: motor driving circuit A closed-loop control, motor driving circuit B closed-loop control, motor driving circuits A and B dual-drive closed-loop control; thus, the two working modes of the processor circuit are combined with the three working modes of the driving circuit to realize the control of the servo motor. A total of 6 logical working combinations are designed: CPUA working on duty + motor driving circuit A drive closed-loop control (mode 1), CPUA working on duty + motor driving circuit B drive closed-loop control (mode 2), CPUA working on duty + motor driving circuit A / B dual-drive closed-loop control (mode 3), CPUB working on duty + motor driving circuit A drive closed-loop control (mode 4), CPUB working on duty + motor driving circuit B drive closed-loop control (mode 5), CPUB working on duty + motor driving circuit A / B dual-drive closed-loop control (mode 6).

[0060] Furthermore, the cutting machine design modes include the following modes: mode 1 switches to mode 4, mode 2 switches to mode 5, and mode 3 switches to mode 6 for processor circuit cutting; mode 1 switches to mode 2, mode 1 switches to mode 3, mode 2 switches to mode 3, mode 4 switches to mode 5, mode 4 switches to mode 6, and mode 5 switches to mode 6 for drive circuit cutting; mode 1 switches to mode 5, mode 1 switches to mode 6, mode 2 switches to mode 6, mode 3 switches to mode 4, and mode 3 switches to mode 5 for simultaneous switching of processor circuits and drive circuits.

[0061] The motor resolver decoding circuit A in the above scheme is used to decode the position signal of the servo unit motor resolver A and convert it into the position and speed signal of the motor shaft. The signal sends the data to the control circuit CPUA through the SPI interface, and the signal sends the output to the control circuit CPUB through the QEP interface. The resolver decoding circuit is implemented by a general resolver chip (such as AD2S1210 of ADI Company).

[0062] The unit resolver decoding circuit A is used to decode the servo unit resolver A signal and convert it into the unit position signal. The signal sends the data to the control circuit CPUA through the SPI interface, and the signal sends the output to the control circuit CPUB through the QEP interface. The resolver decoding circuit is implemented by a general resolver chip (such as AD2S1210 of ADI Company).

[0063] The motor resolver decoding circuit B is used to decode the position signal of the servo unit motor resolver B and convert it into the position and speed signal of the motor shaft. The signal sends the data to the control circuit CPUA through the SPI interface, and the signal sends the output to the control circuit CPUB through the QEP interface. The resolver decoding circuit is implemented by a general resolver chip (such as AD2S1210 of ADI Company).

[0064] The unit resolver decoding circuit B is used to decode the servo unit resolver B signal and convert it into the unit position signal. The signal sends the data to the control circuit CPUA through the SPI interface, and the signal sends the output to the control circuit CPUB through the QEP interface. The resolver decoding circuit is implemented by a general resolver chip (such as AD2S1210 of ADI Company).

[0065] For further solutions, see Figure 1 As shown, the system also includes a motor drive circuit A, a motor drive circuit B, a brake control circuit and a Hall signal detection circuit; wherein the motor drive circuit A is used to receive the motor drive signal (including 6-way PWM signals and IPM enable signal) of the control circuit CPUA or the control circuit CPUB to drive the A winding coil of the servo unit, and the output signal of the circuit is the three-phase drive voltage of the motor (respectively U, V, W three-phase drive);

[0066] The motor drive circuit B is used to receive the motor drive signal (including 6-way PWM signal and IPM enable signal) of the control circuit CPUA or the control circuit CPUB to drive the B winding coil of the servo unit. The output signal of the circuit is the three-phase drive voltage of the motor (U, V, W three-phase drive respectively);

[0067] The brake control circuit is used to receive the brake control signal sent by the output enable circuit A (or the output enable circuit B) to control the brake to unlock, thereby ensuring the normal operation of the output shaft of the servo unit;

[0068] The Hall signal detection circuit is used to detect the upper and lower limit signals of the servo unit and transmit the signals to the control circuit CPUA and the control circuit CPUB to ensure that when the servo unit reaches the limit, the control circuit can stop the motor operation, thereby protecting the servo unit from working normally.

[0069] use Figure 1 and 2 The control system of the present invention controls the thrust regulating servo unit of a large thrust liquid rocket engine, and its effect is shown in FIG. Figure 3 In the figure, the red curve represents the motor speed (the black curve overlapping with the red curve is the speed setting curve), and the corresponding coordinate is the right vertical coordinate; the gray curve represents the bus current output of the control circuit CPUA, and the corresponding coordinate is the left vertical coordinate; the blue curve represents the speed setting of the control circuit CPUB, and the corresponding coordinate is the left vertical coordinate;

[0070] It can be seen from the figure that before the horizontal axis point 1850, the control circuit CPUA is in duty control, so the black curve control circuit CPUA current effective value is greater than 0, and at the cutting point 1850, the control circuit CPUA is switched to the control circuit CPUB. At this time, it can be seen that the bus current output of the black curve control circuit CPUA tends to 0, indicating that the control circuit CPUA exits control; the blue curve control circuit CPUB speed setting effective value is greater than 0, indicating that the control circuit CPUB is in duty control; from the red curve motor output speed, it can be seen that the speed has been maintained at 12000rpm during the above cutting process, and there is no speed fluctuation, indicating that the control system of the present invention is effective.

Claims

1. A servo unit non-disturbance redundant control system, wherein the motor in the servo unit outputs two motor resolver signals, namely, motor resolver signal A and motor resolver signal B; the servo unit outputs two unit resolver signals, namely, unit resolver signal A and unit resolver signal B; characterized in that: The servo unit disturbance-free redundant control system comprises a control circuit CPUA, a control circuit CPUB, a machine cutting arbitration circuit, an output enabling circuit A and an output enabling circuit B; The control circuit CPUA receives in real time the motor position signal A and the motor speed signal A obtained by decoding the motor resolver signal A, and the motor position signal B and the motor speed signal B obtained by decoding the motor resolver signal B, and simultaneously receives the unit position signal A obtained by decoding the unit resolver signal A and the unit position signal B obtained by decoding the unit resolver signal B; the control circuit CPUA calculates the received motor position signal A, motor speed signal A, motor position signal B, motor speed signal B, unit position signal A and unit position signal B in real time to obtain motor control data, and outputs the control data to the output enabling circuit A in real time; The control circuit CPUA performs self-check on its own status in real time, and outputs a signal bundle CPUA_STATUS to the machine switching arbitration circuit in real time according to the self-check status, wherein the signal bundle CPUA_STATUS includes a software self-check signal BIT, a hardware reset signal RESET, a watchdog signal WDO and a power monitoring signal PFO; The control circuit CPUA receives the position limit signal of the servo unit. When the servo unit reaches the limit, the control circuit CPUA outputs a signal to control the servo motor to stop working and inputs it to the output enabling circuit A; The control circuit CPUB receives in real time the motor position signal B and the motor speed signal B decoded from the motor resolver signal B and the motor position signal A and the motor speed signal A decoded from the motor resolver signal A, and simultaneously receives the unit position signal B decoded from the unit resolver signal B and the unit position signal A decoded from the unit resolver signal A; the control circuit CPUB calculates the received motor position signal A, motor speed signal A, motor position signal B, motor speed signal B, unit position signal A and unit position signal B in real time to obtain motor control data; and outputs the control data to the output enabling circuit B in real time; The control circuit CPUB performs self-check on its own status in real time, and outputs a signal bundle CPUB_STATUS to the machine switching arbitration circuit in real time according to the self-check status, wherein the signal bundle CPUB_STATUS includes a software self-check signal BIT, a hardware reset signal RESET and a watchdog signal WDO; The control circuit CPUB receives the position limit signal of the servo unit. When the servo unit reaches the limit, the control circuit CPUB outputs a signal to control the servo motor to stop working and inputs it to the output enable circuit B; The control circuit CPUA and the control circuit CPUB interact with each other in real time through the dual-port RAM to control data; The machine switching arbitration circuit determines whether the control circuit CPUA is on duty or the control circuit CPUB is on duty according to the signal beam CPUA_STATUS and the signal beam CPUB_STATUS, and outputs the determination result to the output enabling circuit A or the output enabling circuit B; The output enabling circuit A is used to enable the control signal output of the control circuit CPUA: when the control circuit CPUA is on duty, the control circuit CPUA outputs control data to control the operation of the servo unit; when the control circuit CPUA is not on duty, the control circuit CPUA does not output; The output enabling circuit B is used to enable the control signal output of the control circuit CPUB: when the control circuit CPUB is on duty, the control circuit CPUB outputs control data to control the operation of the servo unit; when the control circuit CPUB is not on duty, the control circuit CPUB does not output.

2. The servo unit disturbance-free redundant control system according to claim 1, characterized in that: The system also includes a motor resolver decoding circuit A, a unit resolver decoding circuit A, a motor resolver decoding circuit B, and a unit resolver decoding circuit B; The motor resolver decoding circuit A is used to decode the motor resolver signal A into a motor position signal A and a motor speed signal A, and transmit the signals to the control circuit CPUA and the control circuit CPUB; The unit resolver decoding circuit A is used to decode the unit resolver signal A into a unit position signal A, and transmit it to the control circuit CPUA and the control circuit CPUB; The motor resolver decoding circuit B is used to decode the motor resolver signal B into a motor position signal B and a motor speed signal B, and transmit the signals to the control circuit CPUA and the control circuit CPUB; The unit resolver decoding circuit B is used to decode the unit resolver signal B into a unit position signal B, and transmit it to the control circuit CPUA and the control circuit CPUB.

3. The servo unit disturbance-free redundant control system according to claim 1, characterized in that: The system also includes a motor drive circuit A, a brake control circuit, a Hall signal detection circuit and a motor drive circuit B; The brake control circuit is used to receive the brake control signal sent by the output enable circuit A or the output enable circuit B, and control the brake to unlock, thereby ensuring the normal operation of the output shaft of the servo unit; The Hall signal detection circuit is used to detect the limit signal of the servo unit and transmit the signal to the control circuit CPUA and the control circuit CPUB; The motor drive circuit A is used to receive the motor drive signal sent by the control circuit CPUA and the control circuit CPUB to drive the servo unit; The motor driving circuit B is used to receive the motor driving signal sent by the control circuit CPUA and the control circuit CPUB to drive the servo unit.

4. The servo unit disturbance-free redundant control system according to claim 1, 2 or 3, characterized in that: The machine cutting arbitration circuit includes a first NAND logic circuit, a first pull-up circuit, a second NAND logic circuit and a second pull-up circuit; The first NAND logic circuit is used to judge whether the control circuit CPUA is on duty according to the signal beam CPUA_STATUS, and output the judgment result to the first pull-up circuit, and the first pull-up circuit outputs a signal indicating that the control circuit CPUA is on duty or the control circuit CPUA is not on duty to the output enable circuit A and the second NAND logic circuit according to the judgment result; The second NAND logic circuit determines whether the control circuit CPUB is on duty based on the output signal of the first pull-up circuit and the signal beam CPUB_STATUS, and outputs the determination result to the second pull-up circuit. The second pull-up circuit outputs a signal indicating that the control circuit CPUB is on duty or not to the output enable circuit B based on the determination result.

5. The servo unit disturbance-free redundant control system according to claim 1, 2 or 3, characterized in that: The output enabling circuit A and the output enabling circuit B independently use level conversion chips.

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