A clock tick processing and maintenance method for multi-processor cores

Abstract

The present invention provides a clock tick processing and maintenance method for multiple processor cores. The method includes attaching a clock interrupt handler to a clock interrupt during initialization, so that each processor core executes the clock interrupt handler upon receiving a clock interrupt signal; obtaining the last timebase timestamp; sending a clock interrupt signal to each processor core when a clock tick is triggered; each processor core obtaining the current timebase timestamp of its entry into the clock interrupt handler; comparing the last timebase timestamp with the current timebase timestamp to determine whether the current clock tick interrupt has been responded to; if not, processing and maintaining the current clock tick interrupt by the processor core; and exiting the clock interrupt handler upon completion. The method can reduce lost clock ticks, is highly efficient, requires no additional maintenance costs, and improves the execution efficiency of multiple processor cores.

Description

Technical Field

[0001] The present invention relates to the technical field of computer system software, and in particular to a clock tick processing and maintenance method for a multi-processor core. Background Art

[0002] With the continuous development of multi-core hardware processors, many embedded systems have adopted multi-core operating system technologies to improve software efficiency and hardware utilization. Among them, the clock tick is the basis for task scheduling and time maintenance in the operating system, providing timing capabilities for task invocation and execution.

[0003] In a single-core operating system, the entire system maintains a clock tick, while in a multi-core operating system, the response and processing of multiple processor cores to the same hardware clock interrupt will determine whether the time of the entire system is accurate, thereby affecting the accuracy of scheduling and time management.

[0004] Generally, there are two approaches to clock management in multi-core processors: one maintains the system's tick clock on the master core or a designated processor core, and the other maintains its own tick clock on each processor core. If a single core maintains the system clock, as in the first approach, then when that core's interrupts are disabled, ticks are lost. If each core maintains its own tick clock, then as the system runs and each core's interrupts are disabled, the tick clocks on each core become inconsistent. This requires constant tick consistency checks, increasing the complexity and maintenance costs of multi-core operating systems. Summary of the Invention

[0005] The present invention aims to solve the problems of tick loss during clock tick processing in existing multi-core operating systems, as well as the complex and costly maintenance of each processor core. A clock tick processing and maintenance method for multiple processor cores is designed. This method can make the clock tick of the entire multi-core operating system more accurate than maintenance of a specific core, avoid clock tick loss, and make maintenance of each processor core simpler and more feasible.

[0006] The technical solution for achieving the purpose of the invention is as follows: A clock tick processing and maintenance method for a multi-processor core comprises the following steps:

[0007] S1. When the operating system is initialized, the clock interrupt handler is attached to the unified clock interrupt of the operating system. When each processor core of the multi-processor core receives the clock interrupt, the clock interrupt handler is executed.

[0008] S2. Define a global variable to save the timebase timestamp of the last time the clock tick interrupt was processed;

[0009] S3. When the clock tick is triggered, a clock interrupt signal is sent to each processor core;

[0010] S4. When each processor core enters the clock interrupt handler, it obtains the current timebase timestamp;

[0011] S5. Each processor core determines whether the clock tick interrupt has been responded to by other processor cores based on the previous timebase timestamp and the current timebase timestamp of the processor core;

[0012] If it has been responded to, the processor core exits the clock interrupt processing program;

[0013] If it has not been responded to, the current timebase timestamp is used to replace the previous timebase timestamp to update the global variable, and the processing and maintenance operations of this clock tick interrupt are performed;

[0014] S6. After the clock tick interrupt processing is completed, the processor core exits the clock interrupt processing program.

[0015] In one embodiment, the operating system is an embedded operating system running on a multi-processor core, and the operating system performs task scheduling and time maintenance based on a clock tick.

[0016] In one embodiment, when a hardware clock tick interrupt is triggered, a clock interrupt signal is sent to all processor cores connected to the clock interrupt via a bus.

[0017] In one embodiment, in step S5, based on the current timebase timestamp and the previous timebase timestamp, a method for determining whether the current clock tick interrupt has been responded to by other processor cores is as follows: comparing the current timebase timestamp and the previous timebase timestamp; if both are timebase timestamps within the same clock tick, the current clock tick interrupt has been responded to by other processor cores; otherwise, the current clock tick interrupt is responded to for the first time.

[0018] In one embodiment, in step S5, the processing and maintenance operations of this clock tick interrupt include global time tick maintenance, and checking and triggering of a time watchdog.

[0019] In one embodiment, the operating system uses clock ticks to maintain system time. Each time a clock tick interrupt occurs, the clock tick number increases by 1 based on the previous clock tick number.

[0020] In one embodiment, in step S1, when the operating system is initialized, the global variables in step S2 are initialized to 0.

[0021] In an improved embodiment of the above embodiment, in the above step S1, the clock interrupt handler is attached to the system unified clock interrupt, and the processor core that does not turn off the clock interrupt executes steps S3 to S6, and the processor core that turns off the clock interrupt does not execute steps S3 to S6.

[0022] Compared with the prior art, the beneficial effects of the present invention are as follows: the clock tick processing and maintenance method for multiple processor cores designed by the present invention does not fix the processing of the operating system clock tick interrupt by a certain core. Instead, the processor core that first enters the interrupt handling program executes the response to the single clock tick interrupt of the entire operating system and performs processing and maintenance. The execution is efficient, saves a lot of system overhead, improves the execution efficiency of the multiple processor cores, and can avoid the problem of clock tick loss caused by the interrupt disabling process of a fixed processor core performing clock maintenance. Moreover, if each processor core in the multiple processor cores maintains its own clock tick, then the entire operating system needs to design and run a clock tick calibration module to continuously maintain a unified system clock. The calibration module not only increases the difficulty of operating system design, but also causes additional execution time of the processor cores. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are merely for the purpose of more clearly illustrating the embodiments of the present invention or the technical solutions in the prior art. Those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0024] Figure 1 A schematic diagram of the connection between the operating system and the multi-processor core in a specific implementation manner;

[0025] Figure 2 Flowchart of a clock tick processing and maintenance method for a multi-processor core in a specific implementation manner. DETAILED DESCRIPTION

[0026] The present invention will be further described below with reference to specific embodiments, and the advantages and features of the present invention will become clearer as the description proceeds. However, these embodiments are merely exemplary and do not constitute any limitation to the scope of the present invention. It should be understood by those skilled in the art that the details and forms of the technical solutions of the present invention may be modified or replaced without departing from the spirit and scope of the present invention, and such modifications and replacements fall within the scope of protection of the present invention.

[0027] In the description of this embodiment, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the invention.

[0028] Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified with "first," "second," etc., may explicitly or implicitly include one or more of such features. In the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0029] This specific embodiment discloses a clock tick processing and maintenance method for a multi-processor core. The operating system is an embedded operating system running on the multi-processor core, and the operating system uses clock ticks for task scheduling and time maintenance. The multi-processor core responds to, processes, and maintains clock tick interrupts that occur in the operating system.

[0030] In this specific implementation, the operating system maintains the system time based on the clock tick number. Each time a clock tick interrupt occurs, the clock tick number increases by 1 based on the previous clock tick number.

[0031] See also Figure 2 As shown, the clock tick processing and maintenance method of the multi-processor core includes the following steps:

[0032] S1. When the operating system is initialized, the clock interrupt handler is attached to the unified clock interrupt of the operating system. When each processor core of the multi-processor core receives the clock interrupt, the clock interrupt handler is executed.

[0033] In this step, when the operating system is running, it is possible that not all processor cores' clock interrupts are turned on, or that the clock interrupts of some processor cores are turned off. In this case, the processor cores whose clock interrupts are not turned off execute steps S3 to S6, and the processor cores whose clock interrupts are turned off do not execute steps S3 to S6.

[0034] At the same time, in order to avoid the problem of clock tick loss caused by only one processor core processing the clock tick interrupt and its failure or abnormal interruption, the number of processor cores that do not disable the clock interrupt in this step is at least 2.

[0035] For example, see Figure 1 As shown, the multi-processor core includes 4 processor cores, the clock interrupt of each processor core is connected to the clock interrupt handler in the I / O interrupt controller in the operating system, and the clock interrupt of each processor core is not closed.

[0036] S2. Define a global variable to save the timebase timestamp of the last time the clock tick interrupt was processed.

[0037] In this step, the timebase timestamp is used to determine whether the clock count is repeatedly maintained.

[0038] When the operating system is initialized, the global variable is initialized to 0. As the number of clock tick interrupts increases, the value of the global variable continues to increase.

[0039] S3. When the clock tick is triggered, a clock interrupt signal is sent to each processor core.

[0040] In this step, when the clock tick interrupt of the hardware is triggered (ie, the clock tick interrupt occurs), it sends a clock interrupt signal to all processor cores connected to the clock interrupt through the bus.

[0041] S4. Each processor core obtains the current timebase timestamp when entering the clock interrupt handler.

[0042] S5. Each processor core determines whether the current clock tick interrupt has been acknowledged by another processor core based on the previous timebase timestamp and the current timebase timestamp of the processor core. If so, the processor core exits the clock interrupt handler. If not, the current timebase timestamp replaces the previous timebase timestamp, updates the global variables, and performs processing and maintenance operations for the current clock tick interrupt.

[0043] In this step, based on the current timebase timestamp and the previous timebase timestamp, the method for determining whether the clock tick interrupt has been responded to by other processor cores is as follows:

[0044] Compare the current timebase timestamp with the previous timebase timestamp. If both are timebase timestamps within the same clock tick, then this clock tick interrupt has been responded to by other processor cores; otherwise, this clock tick interrupt is responded to for the first time.

[0045] The processing and maintenance operations of this clock tick interrupt include global time tick maintenance, time watchdog check and triggering, and other time-related processing.

[0046] S6: After the clock tick interrupt is processed, the processor core exits the clock interrupt handler.

[0047] When the clock tick interrupt occurs next time, the above steps S2 to S6 are repeated.

[0048] The clock tick processing and maintenance method for multiple processor cores designed in the present invention does not require a fixed core to handle the clock tick interrupt of the operating system. Instead, the processor core that first enters the interrupt handling program executes the response to, processes, and maintains the single clock tick interrupt of the entire operating system. This method is highly efficient, saves a large amount of system overhead, improves the execution efficiency of multiple processor cores, and avoids the problem of clock tick loss caused by the interrupt being disabled by a fixed processor core performing clock maintenance. Moreover, if each processor core in the multi-processor core maintains its own clock tick, the entire operating system needs to design and run a clock tick calibration module to continuously maintain a unified system clock. The calibration module not only increases the difficulty of operating system design, but also causes additional execution time for the processor cores.

[0049] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0050] In addition, although this specification is described according to implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A clock tick processing and maintenance method for a multi-processor core, characterized in that: The following steps are involved: S1. When the operating system is initialized, a clock interrupt handler is attached to a unified clock interrupt of the operating system. Each processor core of the multiple processor cores executes the clock interrupt handler upon receiving a clock interrupt. The number of processor cores that do not disable clock interrupts is at least two. The processor cores that do not disable clock interrupts execute steps S4 to S6, while the processor cores that disable clock interrupts do not execute steps S4 to S6. S2. Define a global variable to save the timebase timestamp of the last time the clock tick interrupt was processed; S3. When the clock tick is triggered, a clock interrupt signal is sent to each processor core; S4. When each processor core enters the clock interrupt handler, it obtains the current timebase timestamp; S5. Each processor core determines whether the current clock tick interrupt has been responded to by another processor core based on the previous timebase timestamp and the current timebase timestamp of the processor core, including: comparing the current timebase timestamp with the previous timebase timestamp. If the two are timebase timestamps within the same clock tick, the current clock tick interrupt has been responded to by another processor core; otherwise, the current clock tick interrupt is responded to for the first time. If it has been responded to, the processor core exits the clock interrupt processing program; If it has not been responded to, the current timebase timestamp is used to replace the previous timebase timestamp to update the global variable, and the processing and maintenance operations of this clock tick interrupt are performed; S6. After the clock tick interrupt processing is completed, the processor core exits the clock interrupt processing program.

2. The clock tick processing and maintenance method for a multi-processor core according to claim 1, wherein: The operating system is an embedded operating system running on multiple processor cores, and the operating system performs task scheduling and time maintenance based on clock ticks.

3. The clock tick processing and maintenance method for a multi-processor core according to claim 1, wherein: When the hardware clock tick interrupt is triggered, a clock interrupt signal is sent through the bus to all processor cores connected to the clock interrupt.

4. The clock tick processing and maintenance method for a multi-processor core according to claim 1, wherein: In step S5, the processing and maintenance operations of this clock tick interrupt include global time tick maintenance, time watchdog check and triggering.

5. The clock tick processing and maintenance method for a multi-processor core according to claim 1, wherein: The operating system uses clock ticks to maintain system time. Each time a clock tick interrupt occurs, the clock tick number increases by 1 based on the previous clock tick number.

6. The clock tick processing and maintenance method for a multi-processor core according to claim 1, wherein: In step S1, when the operating system is initialized, the global variables in step S2 are initialized to 0.

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