Parallel-to-serial conversion control system and chip for parallel data

Abstract

This application discloses a parallel-to-serial conversion control system and chip for parallel data. The parallel-to-serial conversion control system is connected to an external circuit so that the parallel port of the external circuit used for outputting parallel data is not exposed externally. The external circuit is used to transmit parallel data to the parallel-to-serial conversion control system. The external circuit is a circuit located outside the parallel-to-serial conversion control system and has a parallel port. The external circuit supports the conversion of input signals into the parallel data. The parallel-to-serial conversion control system exposes a conversion result port for outputting serial data, so that the external system can detect the conversion result of the parallel data in the parallel-to-serial conversion control system through the conversion result port. The bit width of the conversion result is less than the bit width of the parallel data.

Description

Technical Field

[0001] This application belongs to the field of parallel-to-serial logic control technology, and particularly relates to parallel-to-serial control systems and chips for parallel data. Background Technology

[0002] When performing performance analysis on the parallel output data after ADC analog-to-digital conversion or in related FPGA (Field Programmable Gate Array) designs, the small storage space (typically a few KB) in small-scale MCUs (microcontrollers) is insufficient to store the large number of conversion results after parallel output into SRAM or other memory blocks. Therefore, the output data can only be output through chip pins, and then the output data of SAR_ADC can be captured by signal detection devices such as logic analyzers or oscilloscopes. The captured output data is then transferred to Matlab software for parallel data performance analysis.

[0003] During signal testing in the design of successive approximation analog-to-digital converters (ADCs) or related digital conversion systems, it was found that, for example, a 12-bit (resolution) SAR_ADC outputs a 12-bit binary number. This 12-bit binary number represents the encoding of the analog signal input to the SAR_ADC. Adding other clock signals, ADC start sampling flag (SOC), and ADC end conversion flag (EOC), at least 16 binary signals need to be pulled down before the converted data can be obtained through the chip pins or circuit device ports. This leads to the following problem: when the SAR_ADC's operating clock frequency is high, the conversion output data flips very quickly. Furthermore, insufficient layout considerations result in very small spacing between the SAR_ADC chip pin locations and the signal traces designed for the SAR_ADC driver circuit. This easily generates crosstalk in high-frequency clock systems, affecting the final output data performance of the SAR_ADC. Additionally, with too many parallel pins exposed, the need for control signals to manage numerous clock and data signals increases the design complexity of pin multiplexing and the cost of chip packaging. Summary of the Invention

[0004] This application discloses a parallel-to-serial conversion control system for parallel data, and the specific technical solution is as follows:

[0005] A parallel-to-serial conversion control system for parallel data is provided. The system is connected to an external circuit, ensuring that the parallel port used for outputting parallel data in the external circuit is not exposed externally. The external circuit is used to transmit parallel data to the parallel-to-serial conversion control system. This external circuit is located outside the parallel-to-serial conversion control system and has a parallel port. The external circuit supports the conversion of input signals into the parallel data. The parallel-to-serial conversion control system exposes a conversion result port for outputting serial data, allowing the external system to detect the conversion result of the parallel data within the parallel-to-serial conversion control system through this port. The bit width of the conversion result is less than the bit width of the parallel data.

[0006] Furthermore, the parallel-to-serial conversion control system includes a bit indexing unit, a clock synchronization unit, a parallel transmission unit, a parallel-to-serial conversion start / stop control unit, and a parallel-to-serial conversion execution unit. The clock synchronization unit, triggered by the system clock signal, synchronizes the conversion end signal to the clock domain of the system clock signal, generates an edge alignment flag signal, and then controls the edge alignment flag signal to follow the clock beat of the system clock signal to delay the output of the parallel-to-serial conversion start flag signal. The clock synchronization unit is also used to transmit the edge alignment flag signal to the bit indexing unit and the parallel-to-serial conversion start flag signal to the parallel transmission unit and the parallel-to-serial conversion start / stop control unit, respectively. The bit indexing unit, triggered by the system clock signal, controls the built-in counter to start counting and transmits the real-time count value to the parallel-to-serial conversion start / stop control unit, and transmits the real-time... The obtained count value is converted into a bit index value, and then the bit index value is transmitted to the parallel-to-serial conversion execution unit; the parallel transmission unit is used to sample the parallel data in parallel based on the start function of the parallel-to-serial conversion start flag signal when triggered by the system clock signal; the parallel-to-serial conversion start / stop control unit is used to adjust the conversion status flag signal based on the parallel-to-serial conversion start flag signal and the count value transmitted by the bit index unit when triggered by the system clock signal, and transmit the conversion status flag signal to the parallel-to-serial conversion execution unit; the parallel-to-serial conversion execution unit is used to index the corresponding bit data from the parallel data based on the conversion status flag signal and the output bit index value when triggered by the system clock signal, and then shift the indexed corresponding bit data to obtain the serial data, so that the parallel data is output sequentially from the high bit to the low bit.

[0007] Furthermore, the parallel-to-serial conversion control system is configured to expose a dedicated testing port. This testing port allows external signal detection devices to capture the corresponding output signals. The testing port includes a clock signal port for outputting the system clock signal, a start flag signal port for outputting the parallel-to-serial conversion start flag signal, a conversion flag signal port for outputting the conversion status flag signal, and a conversion result port for outputting serial data. This allows external signal detection devices to obtain the signal characteristics of the parallel data at each stage of the parallel-to-serial conversion through the testing port.

[0008] Furthermore, the external circuit is a circuit built into the analog-to-digital converter (ADC); the ADC indicates the end of one analog-to-digital conversion of the input analog signal by outputting the conversion end signal; wherein, the ratio of the frequency of the system clock signal to the frequency of the operating clock signal required by the ADC is greater than the number of bits of the ADC; the bit width of the parallel data is equal to the number of bits of the ADC.

[0009] Further, the clock synchronization unit includes a first delay unit and a second delay unit; the data input terminal of the first delay unit is used to input the conversion end signal; the first delay unit is used, under the trigger of the system clock signal, to synchronize the conversion end signal to the clock domain where the system clock signal is located based on the time interval between the edge of the conversion end signal and the edge of the system clock signal that is delayed in the same transition direction, to obtain the edge alignment flag signal; the data output terminal of the first delay unit is connected to the data input terminal of the second delay unit, the second delay unit is used to delay the output of the edge alignment flag signal under the trigger of the system clock signal, and the data output terminal of the second delay unit is used to output the parallel-to-serial conversion start flag signal; the clock synchronization unit also transmits the parallel-to-serial conversion start flag signal output by the data output terminal of the second trigger to the start flag signal port; wherein, the conversion end signal and the parallel-to-serial conversion start flag signal are controlled by different clock domains respectively; the pulse width of the parallel-to-serial conversion start flag signal and the pulse width of the edge alignment flag signal are both equal to an integer multiple of the clock period of the system clock signal PCLK.

[0010] Further, the first delay unit includes a first flip-flop, a second flip-flop, a third flip-flop, and a combinational logic unit; the data input terminal of the first flip-flop is used to input a conversion end signal, and the data input terminal of the first flip-flop is also the data input terminal of the first delay unit; the first flip-flop is used, under the trigger of the system clock signal, to delay the effective edge of the input conversion end signal until it is aligned with the effective edge of the system clock signal for the first time, to obtain a first edge-aligned signal, and then transmits the first edge-aligned signal to the second flip-flop; the data output terminal of the first flip-flop is connected to the data input terminal of the second flip-flop; the second flip-flop is used, under the trigger of the system clock signal, to delay the effective edge of the first edge-aligned signal until it is aligned with the effective edge of the system clock signal again, to obtain a second edge-aligned signal, and then transmits the second edge-aligned signal to the third flip-flop and the combinational logic unit respectively; the data output terminal of the second flip-flop is connected to the data input terminal of the third flip-flop; the third flip-flop is used, under the trigger of the system clock signal, to delay the effective edge of the second ... for the second edge-aligned signal. The effective edge of the alignment signal is delayed until it is aligned with the effective edge of the system clock signal again to obtain a third edge alignment signal, which is then transmitted to the combinational logic unit. The data output terminals of the second and third flip-flops are respectively connected to the corresponding data input terminals of the combinational logic unit. The combinational logic unit is used to output the edge alignment flag signal and set the output edge alignment flag signal to the first level state when the second edge alignment signal is in the first level state and the third edge alignment signal is in the second level state. The pulse width in the edge alignment flag signal is equal to the clock period of the system clock signal. The data output terminal of the first delay unit is the output terminal of the combinational logic unit, and the output terminal of the combinational logic unit is connected to the data input terminal of the second delay unit. The combinational logic unit is not connected to the system clock signal. The clock terminals of the first, second, and third flip-flops are all connected to the system clock signal. The first level state and the second level state are opposite logic level states.

[0011] Furthermore, the combinational logic unit includes at least a NOT gate logic circuit, an AND gate logic circuit, and a selector; the output terminal of the combinational logic unit is the data output terminal of the selector; the NOT gate logic circuit is used to input a third edge alignment signal, invert the third edge alignment signal, and then output the inverted third edge alignment signal; the first input terminal of the AND gate logic circuit is used to input a second edge alignment signal, the second input terminal of the AND gate logic circuit is connected to the output terminal of the NOT gate logic circuit, the AND gate logic circuit performs an AND operation on the second edge alignment signal and the inverted third edge alignment signal, and outputs the result of the AND operation; the output terminal of the AND gate logic circuit is connected to the selection terminal and the data input terminal of the selector respectively, the selector is used to output the result of the AND operation when the result of the AND operation obtained at its selection terminal is a first level state, and mark the result of the AND operation as the edge alignment flag signal; it is also used to output a signal set to the second level state when the result of the AND operation obtained at its selection terminal is a second level state.

[0012] Furthermore, the second delay unit includes at least a fourth flip-flop; the data input terminal of the second delay unit is the data input terminal of the fourth flip-flop; the fourth flip-flop is used to delay the edge alignment flag signal by one reference pulse period under the trigger of the system clock signal, and then output the edge alignment flag signal delayed by one reference pulse period to obtain the parallel-to-serial conversion start flag signal; wherein, the clock period of the system clock signal is the reference pulse period, and the reference pulse period is equal to the time interval between two adjacent rising edges of the system clock signal; the fourth flip-flop also outputs the parallel-to-serial conversion start flag signal to the start flag signal port.

[0013] Furthermore, the conversion end signal is a signal with a rising edge. The effective edges of the conversion end signal, the effective edges of the system clock signal, the effective edges of the first edge alignment signal, and the effective edges of the second edge alignment signal are all rising edges. The rising edge of the conversion end signal is delayed until it aligns with the rising edge of the system clock signal for the second time, and the delayed rising edge of the conversion end signal aligns with the rising edge of the edge alignment flag signal. The first level state is a high level state, and the second level state is a low level state. Both the edge alignment flag signal and the parallel-to-serial conversion start flag signal are pulse signals and are both active high.

[0014] Further, the bit indexing unit includes a sampling counter and an index value converter; the sampling counter is used to set the count value of the sampling counter to the initial count value and set the count enable signal to the second level state when the edge alignment flag signal or the counting enable signal is detected to the first level state, and the next valid edge of the system clock signal arrives; then, it counts once each time a valid edge of the system clock signal is detected, until it is full, and then sets the counting enable signal to the first level state; wherein, the number of bits of the parallel data is equal to the modulus of the sampling counter; the index value converter is used to control the difference between the modulus of the sampling counter and the value 1 and the difference between the count value generated by the sampling counter to be set as the bit index value, and then transmit the currently set bit index value to the parallel-to-serial execution unit.

[0015] Furthermore, the index value converter includes an adder and a NOT gate logic circuit; the input terminal of the NOT gate logic circuit is used to input the count value generated by the sampling counter, and the NOT gate logic circuit is used to invert the input count value and output the inverse code of the count value; the output terminal of the NOT gate logic circuit is connected to the first input terminal of the adder, and the second input terminal of the adder is used to input the modulus value of the sampling counter; the adder is used to add the inverse code of the count value to the modulus value, and then output the result of the addition as the bit index value, thereby realizing the setting of the difference between the modulus value of the sampling counter and the value 1 and the difference between the count value generated by the sampling counter as the bit index value.

[0016] Furthermore, the parallel-to-serial conversion start / stop control unit includes a conversion control register; the clock terminal of the conversion control register is used to input the system clock signal; the data output terminal of the conversion control register is used to output a conversion status flag signal to the parallel-to-serial execution unit; the conversion control register is used to adjust the conversion status flag signal to the first level state after detecting that the parallel-to-serial conversion start flag signal is in the first level state, if the next valid edge of the system clock signal arrives; the conversion control register is also used to adjust the conversion status flag signal to the second level state after the sampling counter has reached full count and set the count value to the initial count value, if the next valid edge of the system clock signal arrives; wherein, the conversion control register is also used to output the conversion status flag signal to the conversion flag signal port.

[0017] Furthermore, the parallel transmission unit includes a parallel register; the clock input of the parallel register is used to input the system clock signal, and the data input of the parallel register is used to input the parallel data in parallel; the parallel register is used to capture the parallel data from the external circuit and buffer the parallel data when the parallel-to-serial conversion start flag signal is detected to be in the first level state, if a valid edge of the system clock signal is detected, and then output the currently buffered parallel data to the parallel-to-serial execution unit.

[0018] Furthermore, the parallel-to-serial conversion execution unit is configured to, when the conversion status flag signal is detected to be set to the first level, whenever a valid edge of the system clock signal is detected, index the corresponding bit data from the parallel data output by the parallel transmission unit according to the bit index value currently transmitted by the bit index unit, and then output the currently indexed bit data to the conversion result port through a shift register to obtain the serial data; until all bits in the parallel data are shifted and output according to the bit index value, the parallel-to-serial conversion operation on the parallel data is determined to be completed; wherein, the order of the corresponding bit data indexed from the parallel data by the parallel-to-serial conversion execution unit using the sequentially set bit index values ​​is the order of the parallel data from the high bit data to the low bit data, so that the reverse order of the count values ​​generated in real time by the sampling counter forms the order of each bit data serially output by the parallel-to-serial conversion execution unit. The parallel-to-serial conversion execution unit includes a shift register that supports parallel input and serial output. The parallel input terminal of the shift register is used to input the parallel data output by the parallel transmission unit. The data output terminal of the shift register is connected to the conversion result port.

[0019] A chip that integrates the parallel-to-serial conversion control system and the external circuit, wherein the chip package has externally exposed test pins including a conversion result pin, wherein the physical external pin of the conversion result port is the conversion result pin.

[0020] To address the issue of excessive port count required for parallel output of analog-to-digital converters (ADCs), this application introduces a parallel-to-serial conversion control system. In this system, the parallel-to-serial conversion execution unit can simultaneously receive logic control from a bit indexing unit, a parallel transmission unit, and a parallel-to-serial conversion start / stop control unit. The parallel transmission unit, triggered by a flag signal synchronized to the system clock signal provided by a clock synchronization unit, synchronously samples the parallel data. Furthermore, triggered by the system clock signal, and combined with the timing guidance of the parallel-to-serial conversion using flag signals (including edge alignment flag signal, parallel-to-serial conversion start flag signal, and conversion status flag signal), and under the index information provided by the bit indexing unit, the parallel-to-serial conversion execution unit outputs the parallel data in reverse order following the rhythm of the system clock signal. This allows the encoded result of the analog signal input to the ADC to be represented as a serial signal. The parallel-to-serial conversion control system then provides an external port for outputting the conversion result of the serial data, enabling external probes to detect the serial data output by the parallel-to-serial conversion execution unit through this port, thus reducing the number of external probe ports required.

[0021] The parallel-to-serial conversion control system, when added to the analog-to-digital converter, can convert the parallel data converted from analog to digital into serial data under the high-speed operating clock signal required by the original analog-to-digital conversion circuit. It only needs to be sent to a single chip pin to obtain the signal characteristics of each bit of the parallel data. This allows for the understanding of the signal characteristics at each stage of the parallel-to-serial conversion, achieving the goal of capturing the SAR_ADC sampled data for performance analysis. It also reduces signal interference from the external ports of the chip or circuit and the chip packaging cost.

[0022] Based on this, the parallel-to-serial conversion control system disclosed in this application can introduce a parallel transmission unit for parallel data interfacing processing of the parallel data output by the external circuit (including an analog-to-digital converter or other circuits with parallel ports that support converting input signals into parallel data), so as to synchronize it to the clock domain where the system clock signal is located; it also introduces a clock synchronization unit, a bit indexing unit, and a parallel-to-serial start / stop control unit for synchronization processing of related control signals of the conversion end signal output by the external circuit, so that the conversion end signal is delayed into a flag signal (parallel-to-serial conversion start flag signal) whose edge is aligned with the same transition direction of the system clock signal and is output externally in the form of an output pulse signal, so that the conversion end signal is still... The flag signal (transition status flag signal) that can be delayed to be aligned with the edge of the system clock signal and can indicate the overflow state of the count of the bit index unit; then when the parallel-to-serial conversion start flag signal output by the clock synchronization unit and the transition status flag signal output by the parallel-to-serial start / stop control unit are detected externally through the corresponding ports, the start information of the parallel-to-serial conversion operation, the end information of the parallel-to-serial conversion, and the start / stop information of the count of the bits required for the parallel-to-serial conversion can be tracked with relatively independent pulse signals under the condition of being synchronized to the same clock domain. Therefore, it is not necessary to detect the parallel output ports at adjacent positions. Moreover, the relevant signals detected by the external ports in this application minimize the signal interference between the internal and external circuits of the analog-to-digital converter, and the number is small. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the overall structure of the parallel-to-serial conversion control system for parallel data disclosed in this embodiment.

[0024] Figure 2 This is a schematic diagram of the circuit unit connection between the parallel-to-serial control system and the analog-to-digital converter disclosed in this embodiment.

[0025] Figure 3 This is a schematic diagram of the external pins of the chip package MCU1 and the external pins of the chip package MCU2, which are the parallel-to-serial control system disclosed in this embodiment. Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. To further illustrate the embodiments, the present invention provides accompanying drawings. These drawings are part of the disclosure of the present invention, mainly used to illustrate the embodiments, and can be used in conjunction with the relevant descriptions in the specification to explain the operating principles of the embodiments. Unless otherwise defined, the technical or scientific terms involved in the present invention should have the ordinary meaning understood by those skilled in the art to which this application pertains. The terms "a," "an," and "the" used in this application do not indicate quantity limitation and can represent singular or plural. The terms "comprising," "including," "having," and any variations thereof used in this application are intended to cover non-exclusive inclusion, such as: a process, method, system product, or device that includes a series of steps or modules is not limited to the listed steps or units, but may also include steps or modules not listed, or may also include other steps or units inherent to these processes, methods, products, or devices. The terms "first," "second," and "third" used in this application are merely used to distinguish similar correspondences and do not represent a specific ordering of objects.

[0027] All unit modules involved in this application are logic circuit modules generated by mapping using the Verilog hardware programming language under EDA tools. Verilog is a hardware description language that describes the structure and behavior of digital system hardware in text form. It can represent logic circuit diagrams and logical expressions, as well as the logical functions performed by a digital logic system. In practical applications, a logic circuit module can be a logic circuit unit, a part of a logic circuit unit, or a combination of multiple logic circuit units. Furthermore, to highlight the innovative aspects of this invention, logic circuit modules that are not closely related to solving the technical problems proposed in this invention are not introduced in the embodiments of this invention. However, this does not mean that other modules are absent from the embodiments of this invention. The specific embodiments of this invention will be further described below with reference to the accompanying drawings.

[0028] As one embodiment, a parallel-to-serial conversion control system for parallel data is disclosed, see [link to documentation]. Figure 1It is understood that the parallel-to-serial conversion control system is connected to an external circuit so that the parallel port of the external circuit used to output parallel data AD_D[N:0] is not exposed externally. The external circuit is used to transmit the parallel data AD_D[N:0] to the parallel-to-serial conversion control system; it can also transmit the conversion end signal EOC_IP and other control signals related to the generation of the parallel data to the parallel-to-serial conversion control system to synchronize with the clock domain of the system clock signal (working clock signal) required by the parallel-to-serial conversion control system. The external circuit is not an internal circuit of the parallel-to-serial conversion control system; it is a circuit located outside the parallel-to-serial conversion control system and has a parallel port. The external circuit supports the conversion of input signals into parallel data and can convert input analog signals into multi-bit digital signals for parallel output. The parallel-to-serial conversion control system outputs a conversion result port for serial data. This system can perform parallel-to-serial conversion on parallel data input from external circuits, sampling and converting it under the system clock signal required by the system. The serial output is then captured by external devices such as logic analyzers or oscilloscopes. External devices can then probe the conversion result of the parallel data within the system via the conversion result port. Since the bit width of the conversion result is less than the bit width of the parallel data (i.e., the number of bits in the conversion result is less than the number of bits in the parallel data), the number of chip pins required (each chip pin corresponds to one port, and each port corresponds to one bit) is reduced.

[0029] In this embodiment, when the parallel-to-serial conversion control system and the external circuit are both packaged within the same chip or the same circuit board, and neither the chip nor the circuit board exposes a parallel port for outputting the parallel data AD_D[N:0], it is not necessary to synchronously or asynchronously capture the parallel data AD_D[N:0] using a logic analyzer or oscilloscope. Instead, the parallel-to-serial conversion control system exposes a dedicated test port, and the signal data output from this dedicated test port is synchronously or asynchronously captured using a logic analyzer or oscilloscope to indirectly analyze the data conversion function and output data in the external circuit. Analysis can be performed by converting the parallel data AD_D[N:0] output by the external circuit into data with fewer bits, and then capturing the converted data for the same type of analysis. If necessary, the conversion end signal EOC_IP and the signal after EOC_IP is processed in the parallel-to-serial control system can also be captured and analyzed according to the actual signal analysis requirements. This allows for capturing and analyzing the parallel data AD_D[N:0] using fewer ports, reducing crosstalk between signals output from the parallel ports from interfering with circuit port or chip pin testing, and also reducing the impact of signals output from the parallel ports on the internal circuitry of the external circuitry and adjacent circuitry.

[0030] When the external circuit is preferably an analog-to-digital converter (ADC), the parallel data AD_D[N:0] is the multi-bit data output by the ADC, which can be used as the encoded information of the parallel output of the ADC. N+1 is the number of bits of the ADC, representing the resolution of the ADC. Moreover, the conversion end signal EOC_IP serves as the sampling conversion end signal of the ADC. When the sampling conversion end signal EOC_IP is set to an active level, such as a high level, the ADC outputs a multi-bit binary number (encoded) representing the input analog signal in parallel.

[0031] When the analog-to-digital converter (ADC) adopts a successive approximation ADC (SAR_ADC), it is mainly used in medium-to-high resolution and medium-to-high conversion rate applications. Its working principle is based on a binary algorithm search method, generating a comparison voltage VREF bit by bit and comparing it successively with the input voltage to perform A / D conversion in a gradually approximating manner. Specifically, the conversion principle of SAR_ADC is to sample the input analog signal at specified time intervals (sampling), and then compare the obtained sampled values ​​sequentially with a series of standard digital signals (such as reference voltage values ​​generated by a D / A network). The digital signals converge successively until the two signals are equal (quantization), and finally output a multi-bit binary number representing the input analog signal (encoding), represented in this embodiment as parallel data AD_D[N:0]. Preferably, the default bit width of the ADC is 12 bits, which can be configured to 12, 10, 8, or 6 bits by its internal registers. The bit width of the ADC depends on the required conversion accuracy, allowing the number of bits of the parallel output of the external circuit of the parallel-to-serial conversion control system to be configured according to different application environments.

[0032] As one example, see Figure 1It is understood that the parallel-to-serial conversion control system includes a bit indexing unit, a clock synchronization unit, a parallel transmission unit, a parallel-to-serial conversion start / stop control unit, and a parallel-to-serial conversion execution unit. The bit indexing unit, clock synchronization unit, parallel transmission unit, parallel-to-serial conversion start / stop control unit, and parallel-to-serial conversion execution unit are all connected to the system clock signal and are controlled by the system clock signal. Under the triggering action of the system clock signal, they perform signal synchronization processing, data buffering, and data output counting control. The external circuitry is used to transmit the conversion end signal EOC_IP to the clock synchronization unit for synchronization processing of the conversion end signal EOC_IP, and also to transmit parallel data AD_D[N:0] to the parallel transmission unit and to buffer the parallel data AD_D[N:0] in real time. N+1 represents the bit width occupied by the parallel data. In this embodiment, the external circuit can be a circuit that provides a specific conversion function of conversion end signal EOC_IP and parallel data AD_D[N:0]. The execution status of the external circuit's conversion function on its input signal can only be obtained by probing the multi-bit data output in parallel by the data converted by the parallel-to-serial control system, including signal characteristics such as the level flipping state and pulse changes of each bit of data.

[0033] The clock synchronization unit is used to synchronize the conversion end signal EOC_IP to the clock domain where the system clock signal is located under the trigger of the system clock signal, and generate the edge alignment flag signal EOC_PCLK_POS. Specifically, it generates the edge alignment flag signal EOC_PCLK_POS with the edge aligned to the system clock signal. In this embodiment, the edge alignment flag signal EOC_PCLK_POS is a pulse signal. The high-level duration of the same pulse of the edge alignment flag signal EOC_PCLK_POS is equal to the clock period of the system clock signal. The rising edge of the same pulse of the edge alignment flag signal EOC_PCLK_POS is aligned with the first rising edge of the system clock signal, and the falling edge of the same pulse of the edge alignment flag signal EOC_PCLK_POS is aligned with the second rising edge of the system clock signal. The same pulse is the signal of the edge alignment flag signal EOC_PCLK_POS in the high pulse phase. The first rising edge and the second rising edge are two rising edges of the system clock signal that are adjacent in time.

[0034] The clock synchronization unit is also used to control the edge alignment flag signal EOC_PCLK_POS to follow the clock beat of the system clock signal to delay the output of the parallel-to-serial conversion start flag signal SYNC_EOC. That is, in order to stabilize the output signal, the output is selected by timing. The parallel-to-serial conversion start flag signal SYNC_EOC can be output by controlling the edge alignment flag signal EOC_PCLK_POS to delay the system clock signal by one clock cycle. The parallel-to-serial conversion start flag signal SYNC_EOC is then transmitted to the parallel transmission unit as a flag signal for the parallel transmission unit to start buffering the parallel data AD_D[N:0].

[0035] The clock synchronization unit is used to transmit the parallel-to-serial conversion start flag signal SYNC_EOC to the parallel-to-serial start / stop control unit under the trigger of the system clock signal, and to synchronize the start signal required for serial output to the clock domain where the system clock signal is located; the clock synchronization unit is also used to transmit the edge alignment flag signal EOC_PCLK_POS to the bit index unit, and to perform synchronization processing on the bits required for serial output data; thereby controlling the parallel-to-serial control system to perform serial output within the clock domain where the system clock signal is located.

[0036] Preferably, the parallel-to-serial conversion control system provides an external starting flag signal port for outputting the parallel-to-serial conversion start flag signal SYNC_EOC, so that the external system can detect the parallel-to-serial conversion start flag signal SYNC_EOC output by the clock synchronization unit through the starting flag signal port, reflecting the situation where the parallel-to-serial conversion control system synchronizes the conversion end signal EOC_IP and the parallel data AD_D[N:0] to the clock domain where the system clock signal is located.

[0037] The bit indexing unit, triggered by the system clock signal, controls the built-in counter to start counting, transmits the real-time count value CNTm to the parallel-to-serial conversion start / stop control unit, converts the real-time count value CNTm into a bit index value INDEX, and then transmits the bit index value INDEX to the parallel-to-serial conversion execution unit. The bit index value INDEX is the result of counting starting from the valid edge of the edge alignment flag signal EOC_PCLK_POS, triggered by the system clock signal. This is provided that the rising edge of the edge alignment flag signal EOC_PCLK_POS arrives or the counting state of full overflow is detected by the bit indexing unit. Specifically, it can detect the pulse or rising edge of the edge alignment flag signal EOC_PCLK_POS. Generally, before the pulse or rising edge of the edge alignment flag signal EOC_PCLK_POS arrives, the built-in counter has not reached full overflow or has not yet started counting, and the corresponding counting enable signal or count clearing control signal is in an invalid level state, such as a low level state.

[0038] The parallel transmission unit, triggered by the system clock signal, samples the parallel data AD_D[N:0] from the external circuit in parallel based on the activation function of the parallel-to-serial conversion start flag signal SYNC_EOC, and outputs PD_OUT[N:0] to the parallel-to-serial conversion execution unit. When the external circuit generates the parallel-to-serial conversion start flag signal SYNC_EOC, that is, detects that the parallel-to-serial conversion start flag signal SYNC_EOC is in a high-level state or the parallel-to-serial conversion start flag signal SYNC_EOC flips to the level state corresponding to logic 1, the parallel transmission unit starts sampling the parallel data AD_D[N:0] from the external circuit under the trigger of the system clock signal, that is, implements the activation function of the parallel-to-serial conversion start flag signal SYNC_EOC. It can buffer the parallel data AD_D[N:0] into the internal storage space of the parallel transmission unit within at least one clock cycle of the system clock signal or after a rising edge, forming the parallel data PD_OUT[N:0].

[0039] The parallel-to-serial conversion start / stop control unit, triggered by the system clock signal, adjusts the conversion status flag signal CONV_LEVEL based on the parallel-to-serial conversion start flag signal SYNC_EOC and the count value CNTm transmitted by the bit index unit, and transmits the conversion status flag signal CONV_LEVEL to the parallel-to-serial conversion execution unit. After the parallel-to-serial conversion start / stop control unit obtains the effective level state of the parallel-to-serial conversion start flag signal SYNC_EOC, the counter built into the bit index unit maintains the conversion status flag signal CONV_LEVEL in an effective level state for one counting cycle from the initial count value to full count. The conversion status flag signal CONV_LEVEL can be adjusted to a high level state and a low level state. When the conversion status flag signal CONV_LEVEL is maintained at a high level state, the parallel-to-serial conversion execution unit is triggered to control the serial output of the data on the corresponding bit position buffered by the parallel transmission unit according to the bit index value INDEX generated by the counter built into the bit index unit; otherwise, the serial output of the parallel data AD_D[N:0] buffered by the parallel transmission unit is not triggered.

[0040] Preferably, the parallel-to-serial control system provides an external port for outputting a conversion status flag signal CONV_LEVEL, so that external devices can detect the conversion status flag signal CONV_LEVEL output by the parallel-to-serial start-stop control unit through the conversion flag signal port. This allows external signal detection devices to obtain information about the duration of the parallel-to-serial operation of the parallel data AD_D[N:0] by the parallel-to-serial control system and the signal characteristics of the start and stop phases.

[0041] The parallel-to-serial conversion execution unit, triggered by the system clock signal, uses the output bit index value INDEX to index the corresponding bit data from the parallel data PD_OUT[N:0] buffered by the parallel transmission unit when the conversion status flag signal CONV_LEVEL transmitted by the parallel-to-serial start / stop control unit is set to a high level. The indexed bit data is PD_OUT[INDEX], where PD_OUT[N:0] is a binary number of (N+1) bits, and each bit index value INDEX corresponds to the indexed bit data PD_OUT[INDEX]. PD_OUT[INDEX] is the data already buffered by the parallel transmission unit. The AD_D[INDEX] in the line transmission unit can be indexed using a data path selection structure. Triggered by the system clock signal, it can sequentially buffer the parallel data AD_D[N:0] from the most significant bit to the least significant bit in the parallel-to-serial conversion execution unit. Then, the indexed corresponding bit is shifted and output to obtain the serial data ADC_SDO. This ensures that the parallel data AD_D[N:0] is output sequentially from the most significant bit to the least significant bit of the parallel data AD_D[N:0], following the clock cycle of the system clock signal. The first bit output serially is the most significant bit of the parallel data AD_D[N:0]. Furthermore, it guarantees the synchronization between the input of the parallel data AD_D[N:0] to the parallel-to-serial conversion execution unit and the output of the serial data ADC_SDO from the parallel-to-serial conversion execution unit.

[0042] The parallel-to-serial conversion control system leads out a conversion result port for outputting serial data. This port allows external systems to probe the serial data ADC_SDO output by the parallel-to-serial conversion execution unit. By using the conversion result port, the system can determine the characteristics of each bit signal output by PD_OUT[N:0] at each stage of the parallel-to-serial conversion, representing the encoding result of the analog signal input to the analog-to-digital converter in the form of a serial signal.

[0043] In summary, to address the issue of excessive port count required for parallel output of analog-to-digital converters (ADCs), this application introduces a parallel-to-serial conversion control system. In this system, the parallel-to-serial conversion execution unit can simultaneously receive logic control from a bit indexing unit, a parallel transmission unit, and a parallel-to-serial conversion start / stop control unit. The parallel transmission unit, triggered by a flag signal synchronized with the system clock signal provided by the clock synchronization unit, synchronously samples the parallel data. Furthermore, triggered by the system clock signal, and combined with the timing guidance of the parallel-to-serial conversion using flag signals (including edge alignment flag signal, parallel-to-serial conversion start flag signal, and conversion status flag signal), and under the index information provided by the bit indexing unit, the parallel-to-serial conversion execution unit outputs the parallel data in reverse order following the rhythm of the system clock signal. This allows the encoded result of the analog signal input to the ADC to be represented as a serial signal. The parallel-to-serial conversion control system then provides an external port for outputting the conversion result of the serial data, enabling external probes to detect the serial data output by the parallel-to-serial conversion execution unit through this port, thus reducing the number of external probe ports required.

[0044] Therefore, the parallel-to-serial conversion control system is equivalent to adding a parallel-to-serial circuit system to the analog-to-digital converter. It can convert the parallel data converted from analog to digital into serial data under the high-speed operating clock signal required by the original analog-to-digital conversion circuit. It only needs to be sent to a chip pin or port to obtain the signal characteristics of each bit of the parallel data. It can grasp the signal characteristics of each stage of parallel-to-serial conversion, achieve the goal of capturing the data sampled by SAR_ADC for performance analysis, and reduce the signal interference generated by the external ports of the chip or circuit and the chip packaging cost, including the case where the analog-to-digital converter and the parallel-to-serial conversion control system are packaged in the same chip.

[0045] Based on the above embodiments, see [link to relevant documentation]. Figures 1 to 3 It is understood that the parallel-to-serial conversion control system is configured to expose a dedicated test port. The parallel-to-serial conversion control system and the external circuit can be packaged in the same chip, which can be an analog-to-digital converter circuit. The chip can be configured as a microcontroller. The dedicated test port supports the capture of the corresponding output signal by an external signal detection device. The dedicated test port can also be electrically connected to the peripheral circuit of the chip. By converting parallel data through the parallel-to-serial conversion control system, the number of dedicated test ports can be reduced, thereby reducing the crosstalk caused by the signal output from the dedicated test ports to the peripheral circuit.

[0046] Specifically, the ports dedicated to testing include a clock signal port for outputting the system clock signal PCLK, a flag signal port for feedback on the start of sampling of the input analog signal by the external circuit (including the analog-to-digital converter), a start flag signal port for outputting the parallel-to-serial conversion start flag signal SYNC_EOC, a conversion flag signal port for outputting the conversion status flag signal CONV_LEVEL, and a conversion result port for outputting the serial data ADC_SDO. When the parallel-to-serial conversion control system and the external circuit are packaged in the same chip, the aforementioned ports dedicated to testing are externally accessible as pins that can be physically connected to the chip, so that external signal detection devices can obtain the signal characteristics of the parallel data AD_D[N:0] at each stage of the parallel-to-serial conversion through the ports dedicated to testing. The system clock signal PCLK is the working clock signal required by the parallel-to-serial conversion control system, which is different from the working clock signal required by the external circuit. The flag signal for feedback on the start of sampling of the input analog signal by the external circuit (including the analog-to-digital converter) is SOC, which is output by the external circuit. When the external circuit is an analog-to-digital converter, these dedicated test ports can reflect the flag information of the analog-to-digital converter sampling AD_D[N:0], the flag information of clock synchronization processing of AD_D[N:0], the start and end signals of parallel-to-serial conversion of AD_D[N:0], and the signal characteristics of each bit of AD_D[N:0] during the parallel-to-serial conversion process.

[0047] In some embodiments, the external circuit is a circuit built into the analog-to-digital converter (ADC). The ADC indicates the end of one analog-to-digital conversion of the input analog signal by outputting the conversion end signal. The ratio of the frequency of the system clock signal to the frequency of the operating clock signal required by the ADC is greater than the number of bits in the ADC. The conversion end signal EOC_IP is within the clock domain of the operating clock signal required by the ADC. The bit width of the parallel data is equal to the number of bits in the ADC. Preferably, the conversion end signal EOC_IP is output by the analog circuit built into the ADC. When the conversion end signal EOC_IP is set to a high level, it indicates that the ADC has finished one analog-to-digital conversion of the input analog signal and can start the analog circuit built into the ADC to begin parallel output of the parallel data, that is, outputting the parallel data to the parallel-to-serial conversion control system through the parallel port. However, since the parallel port is not allowed to be captured by external detection devices, the parallel port of the analog circuit built into the ADC can be encapsulated inside the parallel-to-serial conversion control system. When the analog circuit built into the analog-to-digital converter outputs the conversion end signal EOC_IP, the parallel port of the analog circuit built into the analog-to-digital converter outputs the parallel data AD_D[N:0], which represents the multi-bit binary number (encoded information) of the analog signal input to the analog-to-digital converter.

[0048] It should be noted that the ratio of the frequency of the system clock signal to the frequency of the working clock signal ADC_CLK (not shown in the figure) required by the analog-to-digital converter is greater than the number of bits of the analog-to-digital converter. Preferably, the frequency of the system clock signal PCLK is generally 36MHz or 72MHz, etc. When the number of bits of the analog-to-digital converter is 12, the frequency of PCLK must be greater than 12 times the frequency of ADC_CLK; wherein, the frequency of the working clock signal ADC_CLK required by the analog-to-digital converter is generally 32K.

[0049] In some embodiments, see Figure 2It can be seen that the number of bits (N+1) of the analog-to-digital converter (ADC) is equal to the bit width (N+1) of the parallel data; the system clock signal PCLK is the working clock signal required by the parallel-to-serial conversion control system, serving as the master clock signal required by each timing logic unit within the parallel-to-serial conversion control system, and can be generated by the clock source within the parallel-to-serial conversion control system; simultaneously, for the parallel-to-serial conversion control system, the enable signal that each timing logic unit within the parallel-to-serial conversion control system needs to access is the module enable signal ADC_EN, which can originate from the analog-to-digital converter (ADC); for the parallel-to-serial conversion control system, the reset signal that each timing logic unit within the parallel-to-serial conversion control system needs to access is the system reset signal PRESETn, which can also originate from the analog-to-digital converter (ADC), to ensure the synchronization of the parallel data AD_D[N:0] output by the analog-to-digital converter (ADC) and the conversion end signal EOC_IP received by the parallel-to-serial conversion control system.

[0050] As one example, combined with Figure 1 and Figure 2 It can be seen that, Figure 1 The clock synchronization unit shown includes Figure 2 The diagram shows a first delay unit and a second delay unit. The data input terminal of the first delay unit receives the conversion end signal EOC_IP. The first delay unit is used, under the triggering of the system clock signal PCLK, to synchronize the conversion end signal EOC_IP to the clock domain of the system clock signal PCLK based on the time interval between the edge of the conversion end signal EOC_IP and the edge of the system clock signal PCLK that is delayed and has the same transition direction, thereby obtaining the edge alignment flag signal EOC_PCLK_POS. This delays the conversion end signal EOC_IP until it is synchronized with the system clock signal PCLK for the first time. The edge of the conversion end signal EOC_IP and the edge of the system clock signal PCLK that is delayed and has the same transition direction can both be rising edges.

[0051] The data output terminal of the first delay unit is connected to the data input terminal of the second delay unit. The second delay unit, triggered by the system clock signal PCLK, delays the output of the edge alignment flag signal EOC_PCLK_POS. Specifically, it outputs the signal following the clock beat of the system clock signal PCLK, for example, after one clock beat, i.e., delaying the output by one clock cycle of the system clock signal PCLK. The data output terminal of the second delay unit is then used to output the parallel-to-serial conversion start flag signal SYNC_EOC. The clock synchronization unit can also transmit the parallel-to-serial conversion start flag signal SYNC_EOC to the parallel-to-serial start / stop control unit to trigger the parallel-to-serial execution unit to start sampling the bit data indexed in the parallel data PD_OUT[N:0]. The clock synchronization unit can also transmit the parallel-to-serial conversion start flag signal SYNC_EOC to the start flag signal port so that it can be captured by an external signal detection device to determine whether the parallel-to-serial conversion operation for the parallel data AD_D[N:0] has started within the parallel-to-serial control system. It should be noted that the conversion end signal EOC_IP and the parallel-to-serial conversion start flag signal SYNC_EOC are controlled by different clock domains. The edge alignment flag signal EOC_PCLK_POS, the parallel-to-serial conversion start flag signal SYNC_EOC, and the system clock signal PCLK are in the same clock domain. Therefore, to ensure that the initiation of the parallel-to-serial conversion operation of parallel data AD_D[N:0] is synchronized to the clock domain where the system clock signal PCLK is located, the system clock signal PCLK is synchronized with the parallel-to-serial conversion start flag signal SYNC_EOC. The parallel-to-serial conversion start flag signal SYNC_EOC is synchronized with the edge alignment flag signal EOC_PCLK_POS. The pulse width of the pulse signals maintained by the parallel-to-serial conversion start flag signal SYNC_EOC and the edge alignment flag signal EOC_PCLK_POS can be an integer multiple of the clock period of the system clock signal PCLK. In order to speed up the parallel-to-serial conversion, preferably, the pulse width of the parallel-to-serial conversion start flag signal SYNC_EOC and the pulse width of the edge alignment flag signal EOC_PCLK_POS are both equal to the clock period of the system clock signal PCLK.

[0052] From a hardware implementation perspective, the first delay unit may include multiple cascaded flip-flops and combinational logic circuits to achieve the timing effect of synchronizing the conversion end signal EOC_IP to the clock domain of the system clock signal PCLK; the second delay unit includes at least one flip-flop, which serves as a basic delay output effect; the clock terminals of each flip-flop included in the clock synchronization unit and the flip-flops included in the second delay unit are all connected to the system clock signal PCLK.

[0053] Specifically, based on the above implementation method, the connections between the various logic circuit units are as follows: The first delay unit includes a first flip-flop, a second flip-flop, a third flip-flop, and a combinational logic unit; the data output terminal of the first flip-flop is connected to the data input terminal of the second flip-flop, and the data output terminal of the second flip-flop is connected to the data input terminal of the third flip-flop; the data output terminals of the second and third flip-flops are respectively connected to the corresponding data input terminals of the combinational logic unit; wherein, the combinational logic unit is not connected to the system clock signal; the clock terminals of the first, second, and third flip-flops are all connected to the system clock signal PCLK. It will be understood by those skilled in the art that the enable terminals of the first, second, and third flip-flops are all connected to the module enable signal ADC_EN; the reset terminals of the first, second, and third flip-flops are all connected to the system reset signal PRESETn.

[0054] The data input terminal of the first flip-flop is used to input the conversion end signal EOC_IP and can buffer the conversion end signal EOC_IP. The data input terminal of the first flip-flop is also the data input terminal of the first delay unit. The first flip-flop is used to delay the effective edge of the input conversion end signal EOC_IP to the first effective edge of the system clock signal PCLK under the trigger of the system clock signal PCLK, obtain the first edge alignment signal, and then transmit the first edge alignment signal to the second flip-flop. This is equivalent to delaying the conversion end signal EOC_IP by one reference pulse period under the trigger of the system clock signal and then outputting it to the second flip-flop. That is, after one clock cycle, the registered conversion end signal EOC_IP is output to the second flip-flop. At this time, the conversion end signal EOC_IP delayed by one reference pulse period becomes the first edge alignment signal. The second flip-flop is used to delay the effective edge of the first edge alignment signal until it is aligned with the effective edge of the system clock signal again, thereby obtaining the second edge alignment signal. That is, the first edge alignment signal is stored in the second flip-flop for one clock cycle and then output as the second edge alignment signal. It is also equivalent to delaying the conversion end signal EOC_IP by two reference pulse cycles under the trigger of the system clock signal and then outputting it as the second edge alignment signal. That is, the conversion end signal EOC_IP is delayed under the trigger of the system clock signal until it is aligned with the effective edge of the system clock signal PCLK for the second time. The second edge alignment signal is then transmitted to the third flip-flop and the combinational logic unit respectively, so that the third flip-flop and the combinational logic unit can receive the same second edge alignment signal at the same time.

[0055] The third flip-flop is used to delay the effective edge of the second edge-aligned signal until it is aligned with the effective edge of the system clock signal again, thus obtaining the third edge-aligned signal. That is, the second edge-aligned signal is registered in the third flip-flop for one clock cycle and then output as the third edge-aligned signal. This is also equivalent to delaying the conversion end signal EOC_IP by three reference pulse cycles before outputting it as the third edge-aligned signal under the trigger of the system clock signal. In other words, the conversion end signal EOC_IP is delayed until it is aligned with the effective edge of the system clock signal PCLK for the third time under the trigger of the system clock signal. The third edge-aligned signal is then transmitted to the combinational logic unit, which performs combinational logic processing on the third edge-aligned signal and the second edge-aligned signal without introducing the first edge-aligned signal, thereby improving the stability of the signals processed by the combinational logic unit. It should be noted that the triggering of the system clock signal is generally triggered by the effective edge of the system clock signal. For example, each rising edge received by the clock terminal of the relevant flip-flop triggers a data register operation.

[0056] The combinational logic unit is used to output the edge alignment flag signal EOC_PCLK_POS, which can be a pulse signal obtained based on the logical operation of the second edge alignment signal and the third edge alignment signal. Specifically, when triggered by the system clock signal PCLK, the effective edge of the second edge alignment signal arrives before the effective edge of the third edge alignment signal; the pulse width in the edge alignment flag signal is equal to the clock period of the system clock signal. The data output terminal of the first delay unit is the output terminal of the combinational logic unit, and the output terminal of the combinational logic unit is connected to the data input terminal of the second delay unit. The combinational logic unit is configured to obtain the edge alignment flag signal EOC_PCLK_POS and output it to the second delay unit when the second edge alignment signal is in the first level state and the third edge alignment signal is in the second level state. The combinational logic unit also transmits the edge alignment flag signal EOC_PCLK_POS to the bit index unit and sets the output edge alignment flag signal EOC_PCLK_POS to the first level state. The first level state and the second level state are opposite logic level states. In order to ensure the validity of the level signal, generally, when the first level state represents the level state corresponding to logic 1, the second level state represents the level state corresponding to logic 0.

[0057] Preferably, the conversion end signal EOC_IP is a signal with a rising edge, but it is not necessarily a pulse signal, and it has a relatively long high-level holding time; the effective edges of the conversion end signal EOC_IP, the effective edges of the system clock signal PCLK, the effective edges of the first edge alignment signal, and the effective edges of the second edge alignment signal are all rising edges; wherein, the rising edge of the conversion end signal EOC_IP is delayed until it is aligned with the rising edge of the system clock signal for the second time, and the delayed rising edge of the conversion end signal EOC_IP is aligned with the rising edge of the edge alignment flag signal EOC_PCLK_POS; wherein, the first level state is a high level state, corresponding to the level state corresponding to logic 1, and the second level state is a low level state, corresponding to the level state corresponding to logic 0; the edge alignment flag signal EOC_PCLK_POS and the parallel-to-serial conversion start flag signal SYNC_EOC are both pulse signals and are both active high, so as to reduce interference to the internal and external circuits of the analog-to-digital converter.

[0058] In some embodiments, the combinational logic unit includes at least a NOT gate logic circuit, an AND gate logic circuit, and a selector; the output terminal of the combinational logic unit is the data output terminal of the selector, and the data output terminal of the selector is connected to the data input terminal of the second delay unit; the AND gate logic circuit may have at least two input terminals, the first input terminal of the AND gate logic circuit is used to input a second edge alignment signal, the second input terminal of the AND gate logic circuit is connected to the output terminal of the NOT gate logic circuit, the AND gate logic circuit performs an AND operation on the second edge alignment signal and the inverted third edge alignment signal, and outputs the result of the AND operation; the input terminal of the NOT gate logic circuit is used to input the third edge alignment signal; the output terminal of the AND gate logic circuit is connected to the selection terminal and the data input terminal of the selector respectively; the selector also has a data input terminal specifically for receiving signals in a second level state, generally a low level signal, corresponding to the level signal corresponding to logic 0. In the combinational logic unit, the third edge alignment signal is received through a NOT gate logic circuit to obtain an inverted third edge alignment signal. Here, the inversion operation flips the current level state of the third edge alignment signal. Then, an AND gate logic circuit performs an AND operation on the second edge alignment signal and the inverted third edge alignment signal. If the result of the AND operation is in a first level state, the result of the AND operation is output to the data input terminal of the second delay unit through a selector, and the result of the AND operation is marked as the edge alignment flag signal EOC_PCLK_POS. If the result of the AND operation is in a second level state, the edge alignment flag signal EOC_PCLK_POS can be set to the second level state and output, or the signal set to the second level state can be output to the data input terminal of the second delay unit through a selector, indicating that the edge alignment flag signal EOC_PCLK_POS has not been generated or the edge alignment flag signal EOC_PCLK_POS is not in the first level state.

[0059] For example, when the first level state represents the level state corresponding to logic 1, that is, when the first level state represents the high level state, the combinational logic unit generates an edge alignment flag signal EOC_PCLK_POS and outputs it when the second edge alignment signal is in a high level state and the third edge alignment signal is in a low level state. The output edge alignment flag signal EOC_PCLK_POS is in a high level state, and the output level signal corresponds to logic 1. When the second edge alignment signal is not in a high level state or the third edge alignment signal is not in a low level state, the combinational logic unit outputs the level signal corresponding to logic 0, so that the edge alignment flag signal EOC_PCLK_POS forms a pulse signal.

[0060] Based on the above embodiments, the second delay unit includes at least a fourth flip-flop; the data input terminal of the second delay unit is the data input terminal of the fourth flip-flop, and the output terminal of the combinational logic unit is connected to the data input terminal of the fourth flip-flop. The fourth flip-flop, upon receiving the edge alignment flag signal EOC_PCLK_POS output by the combinational logic unit, delays the edge alignment flag signal EOC_PCLK_POS by one reference pulse period under the trigger of the system clock signal PCLK, and then outputs the edge alignment flag signal EOC_PCLK_POS after the delay of one reference pulse period to obtain the parallel-to-serial conversion start flag signal SYNC_EOC. The fourth flip-flop also outputs the parallel-to-serial conversion start flag signal to the starting flag signal port, the parallel transmission unit, and the parallel-to-serial start / stop control unit, respectively. In this embodiment, the edge alignment flag signal EOC_PCLK_POS is incremented by one clock cycle within the fourth flip-flop before outputting the parallel-to-serial conversion start flag signal SYNC_EOC to the starting flag signal port. Preferably, the parallel-to-serial conversion start flag signal SYNC_EOC is considered to represent the signal output by the starting flag signal port. It should be noted that the clock period of the system clock signal is the reference pulse period, which is equal to the time interval between two adjacent rising edges of the system clock signal.

[0061] In summary, from the first edge alignment signal, the second edge alignment signal, the third edge alignment signal to the edge alignment flag signal EOC_PCLK_POS, all these control signals or flag signals indicating signal changes require trigger buffering, pausing output, etc. Under the premise that the ratio of the system clock signal frequency to the operating clock signal frequency required by the analog-to-digital converter remains constant, by using data delay to achieve clock synchronization, combinational logic can also be used to process the second and third edge alignment signals to reduce the phenomenon of large changes in the count value of the bit index unit caused by clock offset, and the instability of the conversion status flag signal CONV_LEVEL generated by the parallel-to-serial start / stop control unit. This reduces the probability of parallel data conversion errors in the parallel transmission unit by the parallel-to-serial execution unit. Therefore, it avoids the impact of input signal disturbances on the written configuration and ensures data stability.

[0062] As one example, combined with Figure 1 and Figure 2It is understood that the bit indexing unit includes a sampling counter and an index value converter; the sampling counter, after detecting that the edge alignment flag signal EOC_PCLK_POS is in the first level state or the counting enable signal is in the first level state, under the trigger of the system clock signal PCLK, if the next valid edge of the system clock signal PCLK is detected, sets the count value CNTm of the sampling counter to the initial count value (e.g., the value 0) to start counting from the initial count value, and sets the counting enable signal to the second level state, wherein the first level state and the second level state are opposite logic level states; then, Each time a valid edge of the system clock signal PCLK is detected, the counter counts once until it reaches full, then the counting enable signal is set to the first level state; that is, the count value CNTm reaches the difference between the modulus of the sampling counter and the value 1. This difference can be pre-configured in the function register built into the sampling counter. Preferably, the count is incremented once for each rising edge of the system clock signal PCLK detected. The number of bits (N+1) of the parallel data AD_D[N:0] is equal to the modulus of the sampling counter. When the external circuit uses an analog-to-digital converter (ADC), the number of bits of the ADC is equal to the modulus of the sampling counter. It should be noted that the modulus of a binary counter refers to the maximum number of counting states that the counter can represent.

[0063] When the effective edge of the system clock signal is a rising edge, the first level state is a high level state, which is the level signal corresponding to logic 1; the second level state is a low level state, which is the level signal corresponding to logic 0. Whenever the count value CNTm of the sampling counter reaches the difference between the modulus of the sampling counter and the value 1, the sampling counter sets the full count flag signal to a high level state. After maintaining the clock cycle of the system clock signal, the counting enable signal is set to a low level state, so that the full count flag signal is output as a pulse signal.

[0064] The index value converter is used to control the difference between the modulus of the sampling counter and the value 1, subtract the count value CNTm generated by the sampling counter, and then set the difference as the bit index value INDEX. The currently set bit index value INDEX is then transmitted to the parallel-to-serial conversion execution unit. However, the index value converter is not connected to the system clock signal PCLK and is therefore not controlled by the system clock signal PCLK.

[0065] In some embodiments, in order to avoid identifying the sign bit of the count value during the hardware circuit calculation process, the operation of subtracting the difference between the modulus of the sampling counter and the value 1 from the count value generated by the sampling counter is converted into adding the difference between the modulus of the sampling counter and the value 1 to the two's complement of the count value generated by the sampling counter. Since the two's complement of the count value generated by the sampling counter is the result of inverting the count value generated by the sampling counter and adding one, the addition operation of adding the difference between the modulus of the sampling counter and the value 1 to the two's complement of the count value generated by the sampling counter is simplified to adding the modulus of the sampling counter to the inverse complement of the count value generated by the sampling counter. Specifically, the index value converter includes an adder and a NOT gate logic circuit. The input of the NOT gate logic circuit is used to input the count value CNTm generated by the sampling counter. The NOT gate logic circuit is used to invert the input count value CNTm and output the inverse code of the count value. The output of the NOT gate logic circuit is connected to the first input of the adder, and the second input of the adder is used to input the modulus of the sampling counter. The adder is used to add the inverse code of the count value to the modulus, and then output the result as the bit index value INDEX. This realizes that the difference between the modulus of the sampling counter and the value 1 and the difference between the count value CNTm generated by the sampling counter are set as the bit index value INDEX. The modulus of the sampling counter is pre-configured, and both the count value and the modulus of the sampling counter can be represented by multi-bit binary numbers. This simplifies the design of the hardware computing circuit and makes it easier for the computer software environment to recognize.

[0066] Therefore, in the bit index unit, after the edge alignment flag signal EOC_PCLK_POS is detected to flip to the first level state, for example, after it flips to the high level state, whenever a valid edge of the system clock signal is detected, for example, a rising edge is detected, the sampling counter increments by one. Under the counting drive of the sampling counter, whenever the sampling counter obtains a count value CNTm, the index value converter inverts the count value CNTm logically to obtain the inverse code of the count value. Then, the inverse code of the count value is added to the modulus. The arrangement formed by the output addition result is equivalent to the reverse arrangement of the count values ​​CNTm generated by the sequential counting of the sampling counter. The output addition result is the bit index value INDEX; if the parallel data AD_D[1 If 1:0] is AD_D[N:0], then the sampling counter is a 4-bit counter and the modulus of the sampling counter is 12. After the edge alignment flag signal EOC_PCLK_POS is detected to flip to the first level state, when the second rising edge of the system clock signal PCLK arrives, the sampling and conversion stage of the parallel data is performed. The count value CNTm generated by the increment of the sampling counter is 0, 1, 2, 3, ..., 11 in sequence (from left to right: the sequence number of the least significant bit of the parallel data increases to the sequence number of the most significant bit of the parallel data). Then the bit index value INDEX is 11, 10, ..., 1, 0 in sequence (from left to right: the sequence number of the most significant bit of the parallel data decreases to the sequence number of the least significant bit of the parallel data).

[0067] As one embodiment, the parallel-to-serial conversion start / stop control unit includes a conversion control register. The input terminal of the control unit is used to input the parallel-to-serial conversion start flag signal SYNC_EOC to coordinate with the system clock signal PCLK to form the trigger condition of the register, thus activating the parallel-to-serial conversion start flag signal SYNC_EOC. The parallel-to-serial conversion start flag signal SYNC_EOC disclosed herein can be used as a data input or enable input to the conversion control register. The clock terminal of the conversion control register is used to input the system clock signal PCLK, and the set terminal of the conversion control register can input the count value CNTm generated by the sampling counter. The data output terminal of the conversion control register is used to output the conversion status flag signal CONV_LEVEL to the parallel-to-serial execution unit. Specifically, the conversion control register, upon detecting that the parallel-to-serial conversion start flag signal SYNC_EOC is in the first level state, if the next valid edge of the system clock signal PCLK arrives, adjusts the conversion status flag signal CONV_LEVEL to the first level state and transmits the conversion status flag signal CONV_LEVEL to the parallel-to-serial execution unit, triggering the parallel-to-serial execution unit to start working; if the rising edge of the conversion status flag signal CONV_LEVEL arrives one clock cycle later than the rising edge of the parallel-to-serial conversion start flag signal SYNC_EOC, then the serial output of parallel data by the parallel-to-serial execution unit controlled by the conversion status flag signal CONV_LEVEL can be executed one clock cycle later than the counting of the bit index unit. The conversion control register is also used to adjust the conversion status flag signal CONV_LEVEL to the second level state after the sampling counter has reached full and set the count value CNTm to the initial count value, if the next valid edge of the system clock signal PCLK arrives, and transmit the conversion status flag signal CONV_LEVEL to the parallel-to-serial execution unit, triggering the parallel-to-serial execution unit to stop serial output, or to determine to stop serial output of the parallel data AD_D[N:0]. The first level state and the second level state are opposite logic level states. The conversion control register is also used to output the conversion status flag signal CONV_LEVEL to the conversion flag signal port so that the parallel-to-serial control system can monitor the parallel-to-serial operation process of the parallel data AD_D[N:0] by external detection devices.

[0068] Therefore, in this embodiment, the conversion status flag signal CONV_LEVEL is jointly controlled by the count value CNTm and / or the parallel-to-serial conversion start flag signal SYNC_EOC. After detecting the first pulse of the parallel-to-serial conversion start flag signal SYNC_EOC, during the counting period from the initial count value CNTm incrementing by one to the maximum count value of the sampling counter (i.e., the difference between the modulus of the sampling counter and the value 1) and from the maximum count value back to the initial count value 0, the parallel-to-serial conversion execution unit is triggered to traverse all bits of the parallel data AD_D[11:0] and perform parallel-to-serial conversion operation in real time. The conversion status flag signal CONV_LEVEL maintains the first level state during this counting period.

[0069] As one embodiment, the parallel transmission unit includes a parallel register; in this embodiment, the parallel register is used to store the N+1 bits of binary code AD_D[N:0]. The clock input of the parallel register is used to input the system clock signal, and the parallel register is a parallel input and parallel output register. The data input of the parallel register is used to input the parallel data in parallel, and the data output of the parallel register is used to output its buffered data to the parallel-to-serial execution unit in parallel. Preferably, it can completely buffer all bits of the parallel data AD_D[N:0] in parallel within one clock cycle, and can output all bits of the parallel data PD_OUT[N:0] in parallel to the parallel-to-serial execution unit or be read by the parallel-to-serial execution unit within (N+1) clock cycles (the reading cycle involved can be (N+1) clock cycles, where the clock cycle refers to the clock cycle of the system clock signal PCLK), so that the parallel-to-serial execution unit has sufficient time to index and read all bit data. In this embodiment, the parallel register is used to capture the parallel data AD_D[N:0] from the analog-to-digital converter and buffer the parallel data when the parallel-to-serial conversion start flag signal SYNC_EOC is detected to be in the first level state and a valid edge of the system clock signal PCLK is detected. Since sampling only begins when the parallel-to-serial conversion start flag signal SYNC_EOC is detected to be in the valid level state or a corresponding pulse signal is detected, the parallel transmission unit synchronizes the parallel data AD_D[N:0] to the clock domain where the system clock signal PCLK is located, and then outputs it as parallel data PD_OUT[N:0]. The parallel data PD_OUT[N:0] is output to the parallel-to-serial execution unit with a delay of one clock cycle relative to the parallel data AD_D[N:0] sampled by the parallel register.

[0070] As one example, combined with Figure 1 and Figure 2 It is understood that the parallel-to-serial conversion execution unit is used to, when the conversion status flag signal CONV_LEVEL is detected to be set to the first level, whenever a valid edge of the system clock signal PCLK is detected, index the corresponding bit data PD_OUT[INDEX] from the parallel data PD_OUT[N:0] output by the parallel transmission unit according to the bit index value INDEX currently transmitted by the bit index unit, and then output the currently indexed bit data PD_OUT[INDEX] to the conversion result port through the shift register to obtain the serial data ADC_SDO=PD_OUT[INDEX]. Here, one bit data is output by one conversion result port. This continues until all bits in the parallel data PD_OUT[N:0] are shifted and output according to the bit index value INDEX (generated by the bit index unit counting under the trigger of the system clock signal PCLK), thus determining that one parallel-to-serial conversion operation of the parallel data PD_OUT[N:0] or AD_D[N:0] is completed, and the sampling and conversion are completed within the clock domain to which the system clock signal PCLK belongs.

[0071] In this embodiment, when the conversion status flag signal CONV_LEVEL is detected to be set to the first level, the parallel-to-serial conversion execution unit, in accordance with the clock cycle of the system clock signal PCLK, can perform a shift output on the bits indexed by the parallel data PD_OUT[N:0] to achieve the parallel-to-serial conversion operation during the counting phase from the count value CNTm from the count value 1 to the maximum count value of the sampling counter (i.e., the difference between the modulus of the sampling counter and the value 1) and then back to the initial count value 0. Specifically, the parallel-to-serial conversion execution unit will maintain a state of (N+1) clock cycles, according to the bit index value INDEX received under the clock cycle of the system clock signal PCLK, read the corresponding bit number PD_OUT[INDEX] of the parallel data from the parallel transmission unit, and output it as the serial data. Thus, the serial data represents the signal characteristics of each bit of the parallel data AD_D[N:0], and the signal characteristics of all bits can be obtained using only a dedicated test port output.

[0072] In this embodiment, the parallel-to-serial conversion execution unit includes a shift register that supports parallel input and serial output. The hardware implementation of the parallel-to-serial conversion execution unit can use a shift register, specifically a shift register that supports parallel input and serial output. The parallel input terminal of the shift register is used to input the parallel data PD_OUT[N:0] output by the parallel transmission unit. The data output terminal of the shift register is connected to the conversion result port and is used to output the serial data ADC_SDO. The shift register can cache the corresponding indexed bits from the parallel data PD_OUT[N:0] according to the sorting of the real-time counted bit index values ​​INDEX and output them bit by bit, specifically shifting and outputting in order from high bits to low bits. The shift register is composed of flip-flops with storage functions. One flip-flop can store 1 bit of binary code. Therefore, a register that stores (N+1) bits of binary code needs to be constructed using (N+1) flip-flops. It can provide (N+1) data input terminals to input parallel data PD_OUT[N:0] in parallel, but only provides one data output terminal to output serial data ADC_SDO=PD_OUT[INDEX] and can be brought out to the outside of the system. Compared with the number of pin ports required to bring out multiple bits of AD_D[N:0] in parallel, this embodiment significantly reduces the number of external probe ports.

[0073] Based on the aforementioned embodiment corresponding to the bit indexing unit, the parallel-to-serial conversion execution unit uses the sequentially set bit index values ​​INDEX to index the corresponding bit data from the parallel data PD_OUT[N:0] in a sorted order from high bit data to low bit data in the parallel data PD_OUT[N:0]. This reverses the sorting order of the count values ​​CNTm generated in real time by the sampling counter, forming the order of each bit data serially output by the parallel-to-serial conversion execution unit. Each bit of the parallel data PD_OUT[N:0] corresponds to a pulse of the system clock signal PCLK. When each rising edge of the system clock signal PCLK arrives, the parallel-to-serial conversion execution unit samples one bit of the parallel data PD_OUT[N:0] transmitted by the parallel transmission unit, realizing the serial output ADC_SDO. Specifically... The first output ADC_SDO is PD_OUT[N], which is the highest bit of the parallel data. The corresponding bit index value INDEX is the count value 0 counted by the sampling counter, which is the initial count value of the sampling counter. In the parallel data PD_OUT[N:0], the binary data at the bit position with the larger order is configured to be converted into the serial data first. Then, the corresponding bit data indexed is shifted and output to obtain the serial data, so that the parallel data is output sequentially from the high bit to the low bit. The serial-to-serial conversion control system leads out a conversion result port for outputting the serial data, so that the external system can detect and convert the serial data output by the serial-to-serial execution unit through the conversion result port. When the external circuit that outputs the parallel data AD_D[N:0] is an analog-to-digital converter, the serial data represents the encoding result of the analog signal input to the analog-to-digital converter in the form of a serial signal.

[0074] In the foregoing embodiments, when the effective edge of the system clock signal is a rising edge, the first level state is a high level state, corresponding to the level state of logic 1, and the second level state is a low level state, corresponding to the level state of logic 0. The relevant registers are all composed of flip-flops with storage functions, which can then form counters. In addition, the registers should also have control circuits for executing data reception and clear commands, generally composed of gate circuits, to satisfy the basic functional operations required by the registers, such as cache update, clearing, and setting to 1. Figure 2 The clock terminals of the sampling counter, conversion control register, parallel transmission unit, and parallel-to-serial conversion execution unit are all connected to the system clock signal PCLK. As will be understood by those skilled in the art, the enable terminals of the sampling counter, conversion control register, parallel transmission unit, and parallel-to-serial conversion execution unit are all connected to the module enable signal ADC_EN; and the reset terminals of the sampling counter, conversion control register, parallel transmission unit, and parallel-to-serial conversion execution unit are all connected to the system reset signal PRESETn.

[0075] In summary, the parallel-to-serial conversion execution unit, when the conversion status flag signal transmitted by the parallel-to-serial start / stop control unit is set to a high level, triggers the system clock signal and uses the output bit index value to index the corresponding bit data from the parallel data transmitted by the parallel transmission unit. It then shifts the indexed corresponding bit data to obtain serial data, so that the parallel data is output sequentially from the high bit to the low bit. Furthermore, the parallel-to-serial control system provides an external port for outputting the conversion result of the serial data. When the external circuit is an analog-to-digital converter, the external circuit uses the conversion result port to detect the serial data output by the parallel-to-serial conversion execution unit, representing the encoding result of the analog signal input to the analog-to-digital converter in the form of a serial signal. The parallel-to-serial conversion control system is equivalent to adding a parallel-to-serial circuit to the analog-to-digital converter. It can convert the parallel data converted from analog to serial data under the high-speed operating clock signal required by the original analog-to-digital conversion circuit. Only one chip pin needs to be sent to obtain the signal characteristics of each bit of the parallel data. This allows for the grasp of the signal characteristics of each stage of the parallel-to-serial conversion, thereby achieving the goal of capturing the SAR_ADC sampled data for performance analysis. It also reduces signal interference generated by the external ports of the chip or circuit and the chip packaging cost, including the case where the analog-to-digital converter and the parallel-to-serial conversion control system are packaged in the same chip.

[0076] Based on this, the parallel-to-serial conversion control system disclosed in this application can introduce a parallel transmission unit for parallel data interfacing processing of the parallel data output by the external circuit (including an analog-to-digital converter or other circuits with parallel ports that support converting input signals into parallel data), so as to synchronize it to the clock domain where the system clock signal is located; it also introduces a clock synchronization unit, a bit indexing unit, and a parallel-to-serial start / stop control unit for synchronization processing of related control signals of the conversion end signal output by the external circuit, so that the conversion end signal is delayed into a flag signal (parallel-to-serial conversion start flag signal) whose edge is aligned with the same transition direction of the system clock signal and is output externally in the form of an output pulse signal, so that the conversion end signal is still... The flag signal (transition status flag signal) that can be delayed to be aligned with the edge of the system clock signal and can indicate the overflow state of the count of the bit index unit; then when the parallel-to-serial conversion start flag signal output by the clock synchronization unit and the transition status flag signal output by the parallel-to-serial start / stop control unit are detected externally through the corresponding ports, the start information of the parallel-to-serial conversion operation, the end information of the parallel-to-serial conversion, and the start / stop information of the count of the bits required for the parallel-to-serial conversion can be tracked with relatively independent pulse signals under the condition of being synchronized to the same clock domain. Therefore, it is not necessary to detect the parallel output ports at adjacent positions. Moreover, the relevant signals detected by the external ports in this application minimize the signal interference between the internal and external circuits of the analog-to-digital converter, and the number is small.

[0077] Based on the aforementioned embodiments of the parallel-to-serial conversion control system, this application also discloses a chip that integrates the parallel-to-serial conversion control system and the external circuit. The chip's package includes dedicated test pins for the conversion result, wherein the physical external pins of the conversion result port are the conversion result pins, corresponding to... Figure 3 The chip MCU1 on the left side, the external circuit is an analog-to-digital converter (ADC), and the conversion result port of the control system is used to output serial data ADC_SDO. Figure 3 The left-hand pin for marking the ADC_SDO conversion result is connected to the conversion result port of the parallel-to-serial conversion control system, serving as the physical external pin for the conversion result port. In this embodiment, the dedicated test pin exposed by the chip package is only the conversion result pin. It can convert the parallel data converted from analog to digital into serial data under the high-speed operating clock signal required by the original analog-to-digital conversion circuit. By sending it to only one chip pin, the signal characteristics of the parallel data at each bit can be obtained, and the signal characteristics of each stage of the parallel-to-serial conversion can be grasped. This achieves the goal of capturing the SAR_ADC sampled data for performance analysis, and also reduces signal interference generated by the external ports of the chip or circuit and the chip packaging cost, including the case where the analog-to-digital converter and the parallel-to-serial conversion control system are packaged in the same chip.

[0078] Figure 3 In the left-hand chip MCU1, the chip pins dedicated to testing may also include a clock signal pin for outputting the system clock signal PCLK, a pin for feedback of the SOC flag signal indicating that the analog-to-digital converter (ADC) has started sampling the input analog signal, a start flag signal pin for outputting the parallel-to-serial conversion start flag signal SYNC_EOC, and a conversion flag signal pin for outputting the conversion status flag signal CONV_LEVEL. Therefore, Figure 3 Five dedicated chip pins for chip testing are brought out from the chip package MCU1 on the left side, allowing external signal detection devices to obtain the signal characteristics of parallel data AD_D[N:0] at each stage of parallel-to-serial conversion through the dedicated testing pins.

[0079] It is worth noting that, Figure 3The MCU2 chip on the right integrates an analog-to-digital converter (ADC), but does not integrate the parallel-to-serial conversion control system. The chip pins dedicated to testing include a clock signal pin for outputting the ADC's operating clock (ADC_CLK), a pin for feedback of the ADC's start sampling of the input analog signal (SOC), a pin for outputting the ADC's end sampling of the input analog signal (EOC_IP), and a pin for parallel output of the (N+1) bits of the ADC's conversion result. There are (N+1) pins for parallel output of the (N+1) bits of the ADC's conversion result, where (N+1) represents the number of bits in the ADC. When (N+1) is greater than or equal to 3... Figure 3 The total number of dedicated chip pins for chip testing from the MCU1 chip is less than Figure 3 The cumulative number of dedicated chip pins for chip testing in the MCU2 chip, and Figure 3 The pins in the MCU2 chip that are used to output the conversion results of the (N+1) bits of the analog-to-digital converter (ADC) in parallel are adjacent to each other, which can easily cause crosstalk and affect the stability of the signal to be tested.

[0080] Based on the foregoing embodiments, the parallel-to-serial conversion control system includes a bit indexing unit, a clock synchronization unit, a parallel transmission unit, a parallel-to-serial conversion start / stop control unit, and a parallel-to-serial conversion execution unit. The clock synchronization unit is used to synchronize the conversion end signal output by the external circuit of the parallel-to-serial conversion control system to the system clock signal. The clock synchronization unit is used to transmit the edge alignment flag signal processed by synchronization to the bit indexing unit and the parallel-to-serial conversion start / stop control unit respectively, and to transmit the parallel-to-serial conversion start flag signal delayed from the edge alignment flag signal to the parallel transmission unit. The parallel-to-serial conversion execution unit is used, triggered by the conversion status flag signal transmitted by the parallel-to-serial conversion start / stop control unit, to use the bit index value output by the bit indexing unit to index the corresponding bit data from the parallel data transmitted by the parallel transmission unit and output it as serial data, so that the external system can detect the serial data through the conversion result port.

[0081] exist Figure 3In this design, MCU1 provides an external port for outputting the conversion result of serial data. The internal parallel-to-serial conversion control system of MCU1 performs parallel-to-serial conversion on the parallel data output from the analog-to-digital converter. This is done under the system clock signal required by the control system, and the serial output is captured by external devices such as logic analyzers or oscilloscopes. External devices can then probe the conversion result of the parallel data within the parallel-to-serial conversion control system through the conversion result port. Since the bit width of the conversion result is less than the bit width of the parallel data (i.e., the number of bits in the conversion result is less than the number of bits in the parallel data), the number of chip pins required (each chip pin corresponds to one port, and each port corresponds to one bit) is reduced. This allows for the capture and analysis of parallel data using fewer ports, reducing crosstalk between signals output from parallel ports and its interference with circuit port or chip pin testing. It also reduces the impact of the signals output from parallel ports on internal and adjacent external circuits.

[0082] It should be added that a "microcontroller unit (MCU), also known as a single-chip microcomputer or microcontroller, is a chip-level computer that appropriately reduces the frequency and specifications of a central processing unit (CPU) and integrates memory, timer, USB, A / D conversion, UART, PLC, DMA and other peripheral interfaces, and even LCD driver circuits, onto a single chip to form a chip-level computer, which can perform different combinations of control for different applications."

[0083] The above embodiments are only for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent transformations or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A parallel-to-serial conversion control system for parallel data, characterized in that, The parallel-to-serial control system is connected to an external circuit so that the parallel port in the external circuit used for outputting parallel data is not brought out to the outside. An external circuit is used to transmit parallel data to the parallel-to-serial conversion control system; wherein the external circuit is a circuit located outside the parallel-to-serial conversion control system and having a parallel port, and the external circuit supports the conversion of the input signal into the parallel data; The parallel-to-serial conversion control system outputs a conversion result port for serial data, allowing external systems to detect the conversion result of the parallel data within the control system. The bit width of the conversion result is less than the bit width of the parallel data. The parallel-to-serial conversion control system includes a bit indexing unit, a clock synchronization unit, a parallel transmission unit, a parallel-to-serial conversion start / stop control unit, and a parallel-to-serial conversion execution unit; The clock synchronization unit is used to synchronize the conversion end signal to the clock domain where the system clock signal is located under the trigger of the system clock signal, generate an edge alignment flag signal, and then control the edge alignment flag signal to follow the clock beat of the system clock signal to delay the output of the parallel-to-serial conversion start flag signal; the clock synchronization unit is also used to transmit the edge alignment flag signal to the bit index unit, and transmit the parallel-to-serial conversion start flag signal to the parallel transmission unit and the parallel-to-serial start / stop control unit respectively. The bit index unit is used to control the built-in counter to start counting when triggered by the system clock signal, and transmit the real-time count value to the parallel-to-serial start / stop control unit, convert the real-time count value into a bit index value, and then transmit the bit index value to the parallel-to-serial execution unit. A parallel transmission unit is used to sample the parallel data in parallel based on the activation function of the parallel-to-serial conversion start flag signal, triggered by the system clock signal. The parallel-to-serial conversion start / stop control unit is used to adjust the conversion status flag signal based on the parallel-to-serial conversion start flag signal and the count value transmitted by the bit index unit under the trigger of the system clock signal, and transmit the conversion status flag signal to the parallel-to-serial conversion execution unit; The parallel-to-serial execution unit is used to, under the trigger of the system clock signal, index the corresponding bit data from the parallel data based on the conversion status flag signal and the output bit index value, and then shift the indexed corresponding bit data to obtain the serial data, so that the parallel data is output sequentially from the high bit to the low bit.

2. The parallel-to-serial conversion control system according to claim 1, characterized in that, The parallel-to-serial conversion control system is configured to expose a dedicated test port; the dedicated test port supports the capture of the corresponding output signal by external signal detection equipment; The ports dedicated to testing include a clock signal port for outputting the system clock signal, a start flag signal port for outputting the parallel-to-serial conversion start flag signal, a conversion flag signal port for outputting the conversion status flag signal, and a conversion result port for outputting serial data, so that external signal detection devices can obtain the signal characteristics of the parallel data at each stage of the parallel-to-serial conversion through the ports dedicated to testing.

3. The parallel-to-serial conversion control system according to claim 1, characterized in that, The external circuit is the circuitry built into the analog-to-digital converter (ADC); the ADC indicates the end of one analog-to-digital conversion of the input analog signal by outputting the conversion end signal. The ratio of the frequency of the system clock signal to the frequency of the operating clock signal required by the analog-to-digital converter is greater than the number of bits of the analog-to-digital converter; the bit width of the parallel data is equal to the number of bits of the analog-to-digital converter.

4. The parallel-to-serial conversion control system according to claim 2, characterized in that, The clock synchronization unit includes a first delay unit and a second delay unit; The data input terminal of the first delay unit is used to input the conversion end signal; the first delay unit is used to synchronize the conversion end signal to the clock domain where the system clock signal is located based on the time interval between the edge of the conversion end signal and the edge of the system clock signal that is delayed and generated in the same transition direction, under the trigger of the system clock signal, to obtain the edge alignment flag signal. The data output terminal of the first delay unit is connected to the data input terminal of the second delay unit. The second delay unit is used to delay the output of the edge alignment flag signal under the trigger of the system clock signal. The data output terminal of the second delay unit is used to output the parallel-to-serial conversion start flag signal. The clock synchronization unit also transmits the parallel-to-serial conversion start flag signal output by the data output terminal of the second trigger to the starting point flag signal port. The conversion end signal and the parallel-to-serial conversion start flag signal are controlled by different clock domains; the pulse width of the parallel-to-serial conversion start flag signal and the pulse width of the edge alignment flag signal are both integer multiples of the clock period of the system clock signal PCLK.

5. The parallel-to-serial conversion control system according to claim 4, characterized in that, The first delay unit includes a first flip-flop, a second flip-flop, a third flip-flop, and a combinational logic unit; The data input terminal of the first flip-flop is used to input the conversion end signal, and the data input terminal of the first flip-flop is the data input terminal of the first delay unit; the first flip-flop is used to delay the effective edge of the input conversion end signal to the first time aligned with the effective edge of the system clock signal under the trigger of the system clock signal, to obtain the first edge alignment signal, and then transmit the first edge alignment signal to the second flip-flop; The data output terminal of the first flip-flop is connected to the data input terminal of the second flip-flop; The second flip-flop is used to delay the effective edge of the first edge alignment signal until it is aligned with the effective edge of the system clock signal again when triggered by the system clock signal, so as to obtain the second edge alignment signal, and then transmit the second edge alignment signal to the third flip-flop and the combinational logic unit respectively. The data output terminal of the second flip-flop is connected to the data input terminal of the third flip-flop; The third flip-flop is used to delay the effective edge of the second edge alignment signal until it is aligned with the effective edge of the system clock signal again when triggered by the system clock signal, so as to obtain the third edge alignment signal, and then transmit the third edge alignment signal to the combinational logic unit. The data output terminals of the second and third flip-flops are respectively connected to the corresponding data input terminals of the combinational logic unit; the combinational logic unit is used to output the edge alignment flag signal and set the output edge alignment flag signal to the first level state when the second edge alignment signal is in the first level state and the third edge alignment signal is in the second level state; wherein, the pulse width in the edge alignment flag signal is equal to the clock period of the system clock signal; the data output terminal of the first delay unit is the output terminal of the combinational logic unit, and the output terminal of the combinational logic unit is connected to the data input terminal of the second delay unit; In this configuration, the combinational logic unit is not connected to the system clock signal; the clock terminals of the first flip-flop, the second flip-flop, and the third flip-flop are all connected to the system clock signal; the first level state and the second level state are opposite logic level states.

6. The parallel-to-serial conversion control system according to claim 5, characterized in that, The combinational logic unit includes at least a NOT gate logic circuit, an AND gate logic circuit, and a selector; the output terminal of the combinational logic unit is the data output terminal of the selector. The NOT gate logic circuit is used to input the third edge alignment signal, invert the third edge alignment signal, and then output the inverted third edge alignment signal. The first input terminal of the AND gate logic circuit is used to input the second edge alignment signal. The second input terminal of the AND gate logic circuit is connected to the output terminal of the NOT gate logic circuit. The AND gate logic circuit performs an AND operation on the second edge alignment signal and the inverted third edge alignment signal, and outputs the result of the AND operation. The output of the AND gate logic circuit is connected to the selection terminal and the data input terminal of the selector, respectively. When the result of the AND operation obtained at its selection terminal is in the first level state, the selector outputs the result of the AND operation and marks the result of the AND operation as the edge alignment flag signal. It is also used to set the signal output to the second level state when the result of the AND operation obtained at its selection terminal is the second level state.

7. The parallel-to-serial conversion control system according to claim 5, characterized in that, The second delay unit includes at least a fourth flip-flop; the data input terminal of the second delay unit is the data input terminal of the fourth flip-flop. The fourth flip-flop is used to delay the edge alignment flag signal by one reference pulse period under the trigger of the system clock signal, and then output the edge alignment flag signal after the delay of one reference pulse period to obtain the parallel-to-serial conversion start flag signal. The clock period of the system clock signal is the reference pulse period, which is equal to the time interval between two adjacent rising edges of the system clock signal. The fourth trigger also outputs the parallel-to-serial conversion start flag signal to the starting point flag signal port.

8. The parallel-to-serial conversion control system according to claim 5, characterized in that, The conversion end signal is a signal with a rising edge. The effective edges of the conversion end signal, the effective edges of the system clock signal, the effective edges of the first edge alignment signal, and the effective edges of the second edge alignment signal are all rising edges. The rising edge of the conversion end signal is delayed until it is aligned with the rising edge of the system clock signal for the second time. The delayed rising edge of the conversion end signal is aligned with the rising edge of the edge alignment flag signal. The first level state is a high level state, and the second level state is a low level state; the edge alignment flag signal and the parallel-to-serial conversion start flag signal are both pulse signals and are both active high.

9. The parallel-to-serial conversion control system according to claim 2, characterized in that, The bit indexing unit includes a sampling counter and an index value converter; A sampling counter is used to set the count value of the sampling counter to the initial count value and set the count enable signal to the second level state if the next valid edge of the system clock signal arrives after detecting that the edge alignment flag signal is in the first level state or the counting enable signal is in the first level state. Then, each time a valid edge of the system clock signal is detected, the count is repeated until the count is full, and then the counting enable signal is set to the first level state; wherein, the number of bits of the parallel data is equal to the modulus of the sampling counter; The index value converter is used to control the difference between the modulus of the sampling counter and the value 1 and the difference between the count value generated by the sampling counter to set the bit index value, and then transmit the currently set bit index value to the parallel-to-serial execution unit.

10. The parallel-to-serial conversion control system according to claim 9, characterized in that, Index-value converters include adders and NOT gate logic circuits; The input terminal of the NOT gate logic circuit is used to input the count value generated by the sampling counter, and the NOT gate logic circuit is used to invert the input count value and output the inverse code of the count value; The output of the NOT gate logic circuit is connected to the first input of the adder, and the second input of the adder is used to input the modulus of the sampling counter; The adder is used to add the inverse code of the count value to the modulus value, and then output the result of the addition as the bit index value, so as to set the difference between the modulus value of the sampling counter and the value 1 and the difference between the count value generated by the sampling counter as the bit index value.

11. The parallel-to-serial conversion control system according to claim 9, characterized in that, The serial start / stop control unit includes a conversion control register; The clock terminal of the conversion control register is used to input the system clock signal; the data output terminal of the conversion control register is used to output the conversion status flag signal to the parallel-to-serial conversion execution unit. The conversion control register is used to adjust the conversion status flag signal to the first level state after detecting that the parallel-to-serial conversion start flag signal is in the first level state, if the next valid edge of the system clock signal arrives. The conversion control register is also used to adjust the conversion status flag signal to the second level state if the next valid edge of the system clock signal arrives after the sampling counter has reached full count and set the count value to the initial count value. The conversion control register is also used to output the conversion status flag signal to the conversion flag signal port.

12. The parallel-to-serial control system according to claim 11, characterized in that, The parallel transmission unit includes parallel registers; The clock input of the parallel register is used to input the system clock signal, and the data input of the parallel register is used to input the parallel data in parallel. When the parallel-to-serial conversion start flag signal is detected to be in the first level state, if a valid edge of the system clock signal is detected, the parallel register captures the parallel data from the external circuit, buffers the parallel data, and then outputs the currently buffered parallel data to the parallel-to-serial execution unit.

13. The parallel-to-serial conversion control system according to claim 12, characterized in that, The parallel-to-serial conversion execution unit is configured to, when the conversion status flag signal is detected to be set to the first level, whenever a valid edge of the system clock signal is detected, index the corresponding bit data from the parallel data output by the parallel transmission unit according to the bit index value currently transmitted by the bit index unit, and then shift the currently indexed bit data to the conversion result port through a shift register to obtain the serial data. The parallel-to-serial conversion operation on the parallel data is considered complete when all bits in the parallel data have been shifted and output according to their bit index values. The parallel-to-serial execution unit uses the bit index values ​​set sequentially to index the corresponding bit data from the parallel data, and the sorting of the corresponding bit data is the sorting of the parallel data from high bit data to low bit data, so that the reverse order of the count values ​​generated by the sampling counter in real time forms the order of each bit data serially output by the parallel-to-serial execution unit. The parallel-to-serial execution unit includes a shift register, which supports parallel input and serial output. The parallel input terminal of the shift register is used to input the parallel data output by the parallel transmission unit; the data output terminal of the shift register is connected to the conversion result port.

14. A chip, characterized in that, The chip integrates the parallel-to-serial conversion control system as described in any one of claims 1 to 13 and the external circuit. The chip package has externally exposed test pins, including conversion result pins, wherein the physical external pins of the conversion result port are the conversion result pins.

Images