Method and device for drawing pipeline cpu architecture diagram, medium and program

Abstract

The application provides a pipeline CPU architecture drawing method and a terminal device, the method is applied to the terminal device, and the method comprises the following steps: acquiring a module selection instruction input by a user through the terminal device, determining a CPU initial framework in a working area according to the module selection instruction; acquiring an instruction set selection instruction input by the user through the terminal device, determining the CPU instruction set in the working area according to the instruction set selection instruction; acquiring a combination instruction input by the user through the terminal device, combining a target instruction in the CPU instruction set with the CPU initial framework according to the combination instruction, and generating a module component in the working area according to a combination result; acquiring a completion instruction input by the user through the terminal device, and generating a CPU architecture diagram according to the module component and the CPU initial framework. The pipeline CPU architecture drawing method is softwareized, and the visibility and convenience of drawing are improved.

Description

Technical Field

[0001] This application relates to the field of CPU design, and in particular to a method, device, medium and program for drawing a pipelined CPU architecture diagram. Background Technology

[0002] Currently, there are few teaching design methods, systems, and devices for CPUs based on pipelined architecture. Most teaching design methods, systems, and devices for CPUs use single-cycle or multi-cycle CPUs based on state machines. This does not reflect the characteristics of pipelined CPU architecture well and is not conducive to engineers, technicians, and students quickly mastering the methods of drawing pipelined CPU architecture diagrams.

[0003] Therefore, existing technologies still need improvement. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the purpose of this application is to provide a method for drawing a pipeline CPU architecture diagram and a terminal device, which aims to solve the problem that the existing teaching and design methods for CPUs are not conducive to engineers, technicians and students quickly mastering them.

[0005] To achieve the above objectives, this application adopts the following technical solution:

[0006] In a first aspect, this application provides a method for drawing a pipelined CPU architecture diagram, applied in a terminal device, the method comprising:

[0007] The system obtains a module selection instruction input by the user through the terminal device, and determines the initial CPU framework in the working area according to the module selection instruction. The working area is used to display drawing controls, which include CPU instruction set, target instruction, and module components.

[0008] The system obtains an instruction set selection instruction input by the user through the terminal device, and determines the CPU instruction set in the working area according to the instruction set selection instruction. The CPU instruction set includes one or more target instructions, which are used to implement a preset operation.

[0009] The system acquires a combination instruction input by the user through the terminal device, combines the target instruction in the CPU instruction set with the CPU initial frame according to the combination instruction, and generates the module component in the working area according to the combination result. The module component is used to implement the preset operation of the target instruction.

[0010] The system obtains the completion command input by the user through the terminal device and generates a CPU architecture diagram based on the module components and the initial CPU framework.

[0011] As can be seen, this application solves the problem that existing technologies are not conducive to engineers, students and others quickly mastering the drawing method of pipeline CPU architecture diagrams by softwareizing the drawing method of pipeline CPU architecture diagrams, and improves the visibility and convenience of drawing.

[0012] Secondly, this application also provides a terminal device, including: a processor and a memory; the memory stores a computer-readable program that can be executed by the processor; when the processor executes the computer-readable program, it implements the steps in the method described above.

[0013] Thirdly, this application also provides a computer-readable storage medium storing one or more programs that can be executed by one or more processors to implement the steps described above. Attached Figure Description

[0014] Figure 1 The structural schematic diagram of the terminal device provided in this application;

[0015] Figure 2 The CPU architecture diagram provided in this application;

[0016] Figure 3 A structural diagram of the working area provided in this application;

[0017] Figure 4a Instruction data flow diagram for the mov instruction provided in this application;

[0018] Figure 4b Instruction data flow diagram of the Lui instructions provided in this application;

[0019] Figure 4c The instruction data flow diagram for the inc or dec instruction provided in this application;

[0020] Figure 4d Instruction data flow diagram for the ori instructions provided in this application;

[0021] Figure 4e Instruction data flow diagram of the jmp instruction provided in this application;

[0022] Figure 4f Instruction data flow diagram for the beq instruction provided in this application;

[0023] Figure 4g The instruction data flow diagram for the in instruction provided in this application;

[0024] Figure 4h The instruction data flow diagram for the out instruction provided in this application;

[0025] Figure 5 The CPU structure block diagram provided in this application;

[0026] Figure 6 A flowchart illustrating the method for drawing the pipelined CPU architecture diagram provided in this application. Detailed Implementation

[0027] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0028] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0029] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0030] In this application, "at least one" refers to one or more, and "multiple" refers to two or more. In this application, "and / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a and b, a and c, b and c, or a, b, and c, where each of a, b, and c can be an element itself or a set containing one or more elements.

[0031] It should be noted that the term "equal to" in the embodiments of this application can be used with "greater than" to apply to technical solutions adopted when "greater than", and can also be used with "less than" to apply to technical solutions adopted when "less than". It should be pointed out that when "equal to" is used with "greater than", it is not used with "less than"; conversely, when "equal to" is used with "less than", it is not used with "greater than". In the embodiments of this application, "of", "corresponding (relevant)", and "corresponding" can sometimes be used interchangeably. It should be noted that when their distinction is not emphasized, their intended meanings are consistent.

[0032] First, some of the terms used in the embodiments of this application will be explained to facilitate understanding by those skilled in the art.

[0033] 1. CPU. The Central Processing Unit (CPU) is the core component of computer hardware. The three core components of an electronic computer are the CPU, internal memory, and input / output devices. As the core of the computer system's computation and control, the CPU is the final execution unit for information processing and program execution. It is one of the main devices in an electronic computer and a core component. Its main functions are interpreting computer instructions and processing data in computer software. The CPU is the core component in a computer responsible for reading instructions, decoding instructions, and executing instructions. The CPU mainly consists of two parts: the control unit and the arithmetic logic unit (ALU), which also includes high-speed cache memory and the data and control buses that connect them. The main functions of the CPU are processing instructions, executing operations, controlling timing, and processing data. Currently, almost all commercially available CPUs or microcontrollers (MCUs) adopt a pipelined architecture.

[0034] 2. Work Area. The work area generally includes a toolbar, editing area, resource area, and other areas. The toolbar is an area in a software program that integrates various tools for convenient user access; the editing area is where users edit the CPU architecture diagram using various commands, allowing them to move, add, delete, and modify documents; the resource area displays various drawing controls. In this application, the editing area is the structure display area; the resource area includes the instruction set area and module component area; the toolbar contains default settings for common drawing tools, including but not limited to move tools, font tools, paragraph tools, and editing tools; other areas include but are not limited to confirmation areas and information display areas.

[0035] 3. Instruction Data Flow Graph. An instruction data flow graph illustrates the flow of data within a system caused by an instruction. In this application, it refers to the specific data flow required to complete the preset function of the target instruction. Currently, there are few teaching design methods, systems, and devices for CPUs based on pipelined architectures. Most teaching design methods, systems, and devices for CPUs use single-cycle or multi-cycle CPUs based on state machines. This does not accurately reflect the characteristics of pipelined CPU architectures, hindering engineers and students from quickly mastering the drawing methods of pipelined CPU architecture diagrams, and also fails to guide beginners to quickly familiarize themselves with the overall CPU architecture.

[0036] To address the aforementioned issues, this application provides a method for drawing pipelined CPU architecture diagrams, which solves the problem that existing technologies are not conducive to engineers, students, and others quickly mastering the drawing methods of pipelined CPU architecture diagrams, and also fail to guide novices to quickly become familiar with the overall CPU architecture.

[0037] The information retrieval method provided in this application will be described below with specific embodiments.

[0038] like Figure 3 and Figure 6 As shown, this application provides a method for drawing a pipelined CPU architecture diagram, applied in a terminal device. The method includes:

[0039] Step 101: Obtain the module selection instruction input by the user through the terminal device, and determine the initial CPU frame in the working area 10 according to the module selection instruction.

[0040] For example, the user can be anyone who uses a terminal device to draw a pipeline CPU architecture diagram. The user can input the module selection instruction to the terminal device through an external device, and the processor in the terminal device determines the initial CPU framework in the working area 10 according to the module selection instruction.

[0041] Specifically, the specific operations vary depending on the input method of the selected instruction in the module. Examples are given below.

[0042] Method 1: The module selection instruction can be a click operation triggered by an external device or touch screen, etc., and the initial CPU framework is determined by clicking the corresponding module.

[0043] Method 2: The module selection command can also be a drag-and-drop operation triggered by a mouse or touch screen to drag the CPU initial frame to the working area 10 to determine the CPU initial frame.

[0044] The working area 10 is used to display drawing controls, which include CPU instruction sets, target instructions, and module components.

[0045] In one possible instance, after step 101, the method further includes:

[0046] 201. Obtain the port setting instruction input by the user through the terminal device, and configure the port definition of the CPU initial architecture according to the port setting instruction.

[0047] For an example, please refer to Figure 5 The initial CPU architecture only includes initial modules, requiring configuration of corresponding port definitions for each module, such as input ports, output ports, and clock ports. Port attributes include, but are not limited to: 1. Port name; 2. Data directionality: input / output / bidirectional; 3. Data bit width. Based on the initial CPU architecture, port definitions, and module components, a CPU structure block diagram is obtained. The CPU structure block diagram includes the CPU main body (CPU), which is configured with input ports (Instr), reset ports (Rst_n), data input ports (Port_in), data output ports (Port_out), instruction memory enable ports (Rom_e), clock input ports (Clk), and address output ports (Add). The CPU main body also includes a control module 110 and a data path module 111. The data path module and the control module interact with each other via control signals (Control_signal) and instruction opcodes (Instr_op).

[0048] In one possible instance, please refer to [link / reference needed]. Figure 3 The working area 10 includes a structure display area 11, an instruction set area 12, a module component area 13, an information display area 14, and a confirmation area 15. The structure display area 11 is used to display the initial architecture of the CPU, the instruction set area 12 is used to display all instructions in the instruction set, the module component area 13 is used to display the module components, the information display area 14 is used to prompt the operation to be performed in the current step, and the confirmation area 15 is used to input the completion instruction.

[0049] In one possible instance, step 101 includes:

[0050] Step 1011: Obtain the first module selection instruction input by the user through the terminal device, and determine the control module 110 in the structure display area 11.

[0051] For example, the first selection instruction can be a click operation triggered by an external device or a touch screen, which adds the control module 110 to the structure display area 11 by clicking the control module 110; the first selection instruction can also be a drag operation triggered by a mouse or a touch screen, which drags the control module 110 to the structure display area.

[0052] Step 1012: Obtain the second module selection instruction input by the user through the terminal device, and determine the data path module 111 in the structure display area 11.

[0053] For example, the first selection instruction can be a click operation triggered by an external device or touch screen, which adds the control module 110 to the structure display area 11 by clicking the data path module 111; the first selection instruction can also be a drag operation triggered by a mouse or touch screen, which drags the data path module 111 to the structure display area.

[0054] Step 1013: The CPU initial framework is formed by the control module 110 and the data path module 111.

[0055] For example, the control module 110 and the data path module 111 are connected to form the initial CPU architecture.

[0056] As can be seen, this example implements a drawing visualization operation, where corresponding modules are placed in the structure display area 11 by clicking or dragging to form the initial CPU framework.

[0057] Step 102: Obtain the instruction set selection instruction input by the user through the terminal device, and determine the CPU instruction set in the working area 10 according to the instruction set selection instruction.

[0058] For example, the user can input the instruction set selection command to the terminal device via an external device. After receiving the instruction set selection command, the terminal device determines the CPU instruction set as shown in Table 1 based on the instruction set selection command, and simultaneously sets the instruction width and data width of the target instruction in the CPU instruction set. The instruction width is used to limit the bit width of the target instruction, and the data width is used to limit the bit width of the data. It is understood that the CPU instruction set can be customized and is not limited to the target instructions in Table 1.

[0059] The CPU instruction set includes one or more target instructions, which are used to implement preset operations.

[0060] Specifically, the specific operations will vary depending on the input method of the selected instruction from the instruction set. Examples will be given below.

[0061] Method 1: The instruction set selection instruction can be a click operation triggered by an external device or touch screen, etc. The corresponding target instruction is added to the CPU instruction set and displayed in the working area 10.

[0062] Method 2: The instruction set selection instruction can also be obtained by dragging and dropping the target instruction to the working area 10 via a mouse or touch screen to determine the CPU instruction set.

[0063] Table 1 CPU Instruction Set

[0064]

[0065] Step 103: Obtain the combined instruction input by the user through the terminal device, combine the target instruction in the CPU instruction set with the CPU initial framework according to the combined instruction, and generate the module component in the working area 10 according to the combination result.

[0066] For example, the user can input the combined instruction to the terminal device through an external device. After receiving the combined instruction, the terminal device combines the CPU initial framework with the target instruction according to the combined instruction.

[0067] The module component is used to implement the preset operation of the target instruction.

[0068] Specifically, the specific operations will vary depending on the input method of the combined instructions, as illustrated below with examples.

[0069] Method 1: The combined instruction can be a single-click operation triggered by an external device or touchscreen, where the target instruction is added to the CPU initial frame by clicking the corresponding target instruction; or it can be a series of combined operations consisting of multiple single-click operations to ultimately realize the function of the combined instruction. For example, clicking the CPU initial frame will bring up a target instruction selection interface, where the corresponding target instruction can be selected and added to the CPU initial frame to complete the input of the combined instruction.

[0070] Method 2: The combined instructions can also be added to the CPU initial frame by dragging and dropping the target instructions one by one through a mouse or touch screen, thereby completing the input of the combined instructions.

[0071] Furthermore, after the combined instruction is input, the terminal device filters out the module components of the actual circuit modules required to implement the target instruction based on the combined instruction, and displays them in the working area 10. It is understood that there can be one or more module components implementing the same target instruction; uniqueness is not limited here. Therefore, this example implements automatic filtering of module components.

[0072] In one possible instance, step 103 includes:

[0073] Step 1031: Obtain the target instruction from the instruction set area 12 according to the combined instruction and combine it with the control module 110.

[0074] For example, the control module 110 combines the corresponding target instruction from the CPU instruction set with the combination instruction. Specifically, the combination operation involves: obtaining the module components required by the control module 110 to execute the target instruction according to preset rules, and generating a combination result.

[0075] Step 1032: Generate the module component in the module component area 13 according to the combination result.

[0076] Specifically, the module components are used to form the data path module 111 and to implement the function of the target instruction.

[0077] For example, the module component is generated in the module component area 13 according to the combination result. The module component that achieves the same function may include one or more, which can be freely selected by the user.

[0078] Step 104: Obtain the completion command input by the user through the terminal device, and generate a CPU architecture diagram based on the module components and the initial CPU framework.

[0079] For an example, please refer to Figure 2 After selecting the module components, the user inputs a completion command. Upon receiving the completion command, the terminal device generates a sequence based on the module components and the initial CPU framework, as shown below. Figure 2 The CPU architecture diagram shown.

[0080] like Figure 2As shown in the diagram, the CPU architecture includes a control module 110, a data path module 111, and a storage module (ROM). The control module 110 is a pure combinational logic circuit, while the data path module 111 includes combinational logic circuits and sequential logic circuits. The combinational logic circuits include a data selector (MUX), an arithmetic logic unit (ALU), a subtractor (Sub), and a comparator (Cmp_zero). The sequential logic circuits include a program counter (PC), a register set (Regs), an output register (Output_reg), and an address register (Add_reg).

[0081] Specifically, the specific operations will vary depending on the input method of the completion command, as illustrated below with examples.

[0082] Method 1: The completion instruction can be a click operation triggered by an external device or touch screen, and the completion instruction can be input by clicking a confirmation control or confirmation button; or the completion instruction can be a series of combined operations consisting of multiple click operations.

[0083] Method 2: The completion instruction can be a drag-and-drop operation triggered by a mouse or touch screen, whereby the corresponding module component is selected and dragged to the working area 10 to form a CPU architecture diagram.

[0084] Method 3: The completion instruction can also be a combination of one or more click operations and one or more drag operations to input the completion instruction. For example, dragging a module component to the work area 10, and then automatically generating a CPU architecture diagram by clicking the confirmation control or confirmation button.

[0085] Furthermore, during the automatic generation of the CPU architecture diagram, connections can be automatically generated based on each module component, the initial CPU framework, and port definitions to produce the CPU architecture diagram. For example, this can be achieved by interconnecting interfaces with the same port number.

[0086] In one possible instance, after step 104, the method further includes:

[0087] Step 105, or, obtain the component selection instruction input by the user through the terminal device, add the module component into the data path module 111 to form the data path module 111, and obtain the CPU architecture diagram.

[0088] For example, the component selection instruction can be a click operation triggered by an external device or touchscreen, or a series of click operations, or a drag operation triggered by a mouse or touchscreen, or a combination of one or more click operations and one or more drag operations. By triggering the component selection instruction, the corresponding module components are added one by one to the data path module 111, ultimately forming a complete data path module 111. Finally, the control module 110 and the data path module 111 constitute the CPU architecture diagram.

[0089] In one possible instance, after step 104, the method further includes:

[0090] Step 301: Obtain the simulation command input by the user through the terminal device and simulate the CPU architecture diagram.

[0091] For example, after obtaining the CPU architecture diagram, simulation is required to determine whether the CPU architecture diagram can accurately implement the corresponding functions. Therefore, a simulation function is set up to obtain the simulation instructions input by the user through the terminal device and enter the simulation mode so that the user can perform the corresponding simulation operations.

[0092] In one possible instance, after step 301, the method further includes:

[0093] Step 302: Obtain the first instruction input by the user based on the CPU instruction set, and the CPU architecture diagram performs the corresponding operation according to the first instruction to obtain the execution result.

[0094] For example, inputting a first instruction selects a first target instruction in the CPU instruction set, causing the CPU architecture to execute the first target instruction, and obtaining the execution result of the CPU architecture after executing the first target instruction.

[0095] Step 303: If the execution result is correct, a message indicating successful simulation will be displayed.

[0096] For example, the execution result is compared with the preset result of the target instruction. If they are the same, the execution result is determined to be correct, and then a pop-up window prompts that the simulation is successful.

[0097] Step 304: If the execution result is incorrect, an error message will be displayed.

[0098] For example, the execution result is compared with the preset result of the target instruction. If they are different, the execution result is determined to be incorrect, and an error message is displayed in a pop-up window so that the user can check the source of the error.

[0099] In one possible instance, after step 104, the method further includes:

[0100] Step 401: Obtain the mode switching command input by the user through the terminal device, and switch to teaching mode or normal mode according to the mode switching command.

[0101] For example, the component selection instruction can be a click operation triggered by a device or touch screen, a click operation triggered by an external device or touch screen, a series of combined operations consisting of multiple click operations, a drag operation triggered by a mouse or touch screen, or a combined operation consisting of one or more click operations and one or more drag operations.

[0102] Specifically, after receiving the mode switching instruction, if the current mode is normal, the current work area 10 is switched to teaching mode according to the mode switching instruction; if the current mode is teaching mode, the current work area 10 is switched to normal mode according to the mode switching instruction.

[0103] Step 402: When in teaching mode, lock the work area 10 that is not involved in the current step, and display the operation and operation requirements to be performed in the current step in the information display area 14.

[0104] For example, in the teaching mode, steps 101-104 are executed sequentially. The work area 10 involved in the executed step (i.e., the current step) is in an editable state, while the work area 10 not involved in the executed step is in a locked state. When the corresponding step is executed, the information display area 14 prompts the current step with the operation and operation requirements to guide newcomers to perform the corresponding operation, so that newcomers can quickly become familiar with the drawing process of CPU architecture diagrams and improve the speed of mastering CPU structure.

[0105] It is understood that all steps in this application may be performed in a specific order, and are not limited to steps 101-104.

[0106] Step 403: After completing the current step, unlock the work area 10 involved in the next step, and display the operation and operation requirements to be performed in the next step in the information display area 14.

[0107] For example, after unlocking the work area 10 involved in the next step, the system begins to guide the user to perform the relevant operations and requirements of the next step through the information display area 14, while locking the areas not involved in the next step.

[0108] As can be seen, this example provides guidance on drawing CPU architecture diagrams for students, new employees, and other users by setting up a teaching mode, so that novices can quickly become familiar with the process of drawing CPU architecture diagrams and improve their speed of mastering CPU structure.

[0109] In one possible instance, after step 104, the method further includes:

[0110] Step 501: Generate an instruction data flow graph based on the instruction set and the CPU initial framework.

[0111] For example, after generating the CPU architecture diagram, an instruction data flow diagram can also be generated simultaneously. The CPU instruction set may include target instructions as shown in Table 1. Please refer to [reference needed]. Figures 4a-4h The following examples illustrate the instruction data flow diagrams for each instruction.

[0112] like Figure 4a As shown, the diagram illustrates the instruction data flow of the `mov` instruction. The `mov` instruction transfers the value of the read register corresponding to the `rs` address to the write register corresponding to the `rd` address. Specifically, in the first clock cycle, the address of the read register (Raddr), the address of the write register (Waddr), and the data to be written to the registers (the value of the read register) are given. In the second clock cycle, the data is written to the second register.

[0113] like Figure 4b As shown, the figure illustrates the instruction data flow of the lui instruction. The lui instruction transfers the immediate value (bits 0 to 7 of the instruction) to the register corresponding to the rd address. Specifically, the address of the write register and the immediate value (imm) are given in the first clock cycle, and the immediate value is written to the write register in the second clock cycle.

[0114] like Figure 4c As shown, the diagram illustrates the instruction data flow of the `inc` or `dec` instruction. The data flow diagrams for `inc` and `dec` are identical; the difference lies in the operations performed in the ALU. The read and write addresses for both `inc` and `dec` instructions are the same. In the first clock cycle, register data (`Rdata`) is read and sent to the ALU for computation, then sent to the data input (`Wdata`) of the register bank (`Regs`). In the second clock cycle, the computation result is written to the write register.

[0115] like Figure 4d As shown, the diagram illustrates the instruction data flow of the ori instruction. In the first clock cycle, the ori instruction provides the address to read the register (Raddr) and the address to write the register (Waddr), sending the immediate value (imm) and register data (Rdata) to the ALU for bitwise OR operation. In the second clock cycle, the result of the ALU operation is written to the register.

[0116] like Figure 4e As shown, the diagram illustrates the instruction data flow of the jmp instruction. In the first clock cycle, the jmp instruction inputs the value of the given register (Rdata) to the address in the program memory (Rom) to implement the instruction jump. Simultaneously, it inputs the value of the given register (Rdata) to the Pc module (program counter). The input address is updated when the next valid clock edge arrives.

[0117] like Figure 4f As shown in the figure, this is the instruction data flow diagram of the beq instruction. In the first clock cycle, the beq instruction compares the value of the corresponding register with 0 using the Sub module (subtractor). If they are equal, the Sub module outputs the current address value plus one, allowing the instructions to execute sequentially. If they are not equal, the Sub module outputs the current address value minus the value of num, causing the instruction to jump. Simultaneously, the output value of the Sub module is assigned to the Pc module (program counter) so that the address can be updated in the next clock cycle.

[0118] like Figure 4g As shown in the figure, this is the instruction data flow diagram of the in instruction. The in instruction provides the address (Waddr) of the register to be written in the first clock cycle, and writes the data of the input port (port_in) into the corresponding register in the second clock cycle.

[0119] like Figure 4h As shown, the figure is the instruction data flow diagram of the out instruction. The out instruction provides the address (Raddr) of the register to be read in the first clock cycle and reads the data to the input of the output register (output_reg). In the second clock cycle, it outputs the data to the port (port_out).

[0120] Step 502: Generate a CPU structure block diagram based on the module components and the initial CPU framework.

[0121] For an example, please refer to Figure 5 After generating the CPU architecture diagram, a CPU structure block diagram can also be generated simultaneously. This CPU structure block diagram is specifically a modular structure diagram of the CPU. Since the CPU structure block diagram has already been described in detail above, it will not be repeated here.

[0122] In one possible instance, prior to step 101, the method further includes:

[0123] Step 601: Pre-configure one or more first templates of the initial architecture of the CPU. When the module selection instruction is obtained, directly add the selected first template to the structure display area 11 in the working area 10.

[0124] For example, to improve the efficiency of drawing CPU architecture diagrams, one or more commonly used initial CPU architectures can be formed into first templates and stored. When needed, the first template can be directly added to the structure display area 11 through the module selection instruction. For example, commonly used CPU two-layer pipeline structures, three-layer pipeline structures, etc., can be used as first templates, or other pipeline structures can be set; there is no unique limitation here.

[0125] In one possible instance, prior to step 101, the method further includes:

[0126] Step 701: Pre-configure one or more second templates of the CPU instruction set. When the instruction set selection instruction is obtained, directly add the selected second template to the instruction set area 12 in the working area 10.

[0127] For example, in order to improve the drawing efficiency of CPU architecture diagrams, commonly used CPU instruction sets can be further formed into one or more second templates and stored. When needed, the second template can be directly added to the structure display area 11 by selecting the instruction set.

[0128] In summary, this application provides a method and terminal device for drawing a pipelined CPU architecture diagram. The method, applied in a terminal device, includes: acquiring a module selection instruction input by a user through the terminal device, and determining an initial CPU framework in a working area based on the module selection instruction; acquiring an instruction set selection instruction input by the user through the terminal device, and determining the CPU instruction set in the working area based on the instruction set selection instruction; acquiring a combination instruction input by the user through the terminal device, combining the target instruction in the CPU instruction set with the initial CPU framework based on the combination instruction, and generating the module component in the working area based on the combination result; and acquiring a completion instruction input by the user through the terminal device, and generating a CPU architecture diagram based on the module component and the initial CPU framework. This application improves the visibility and convenience of drawing by software-based methods for drawing pipelined CPU architecture diagrams.

[0129] This application also provides a computer-readable storage medium storing one or more programs that can be executed by one or more processors to implement the steps in the methods described in the above embodiments.

[0130] This application also provides a terminal device 25, such as Figure 1As shown, it includes at least one processor 20; a display screen 21; and a memory 22, and may also include a communications interface 23 and a bus 24. The processor 20, display screen 21, memory 22, and communications interface 23 can communicate with each other via the bus 24. The display screen 21 is configured to display a preset user guide interface in the initial setup mode. The communications interface 23 can transmit information. The processor 20 can invoke logical instructions in the memory 22 to execute the methods described in the above embodiments.

[0131] Furthermore, the logical instructions in the aforementioned memory 22 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.

[0132] The memory 22, as a computer-readable storage medium, can be configured to store software programs, computer-executable programs, such as program instructions or modules corresponding to the methods in the embodiments of this disclosure. The processor 20 executes functional applications and data processing by running the software programs, instructions, or modules stored in the memory 22, thereby implementing the methods in the above embodiments.

[0133] The memory 22 may include a program storage area and a data storage area. The program storage area may store the operating system and application programs required for at least one function; the data storage area may store data created based on the use of the terminal device 25. Furthermore, the memory 22 may include high-speed random access memory (RAM) and may also include non-volatile memory. For example, various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks, may be used, or they may be transient storage media.

[0134] Optional, such as Figure 1 As shown, the method for drawing the pipelined CPU architecture diagram is specifically embodied in a drawing software. This drawing software is applied to a terminal device, and its interface is displayed on the screen 21. The specific program for drawing the pipelined CPU architecture diagram is stored in the memory 22 and called by the processor 20. Users input corresponding instructions to the terminal device through external devices or a touchscreen to perform the corresponding drawing operations. The external devices include, but are not limited to, one or more devices such as a mouse, buttons, keyboard, and voice module.

[0135] Furthermore, the specific process of loading and executing multiple instructions in the aforementioned storage medium and mobile terminal has been described in detail in the above method, and will not be repeated here.

[0136] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A method for drawing a pipelined CPU architecture diagram, characterized in that, When applied in a terminal device, the method includes: The system obtains module selection instructions input by the user through the terminal device, and determines the initial CPU framework in the work area according to the module selection instructions. The work area is used to display drawing controls, which include CPU instruction sets, target instructions, and / or module components. The work area includes a toolbar, an editing area, and a material area. The system obtains an instruction set selection instruction input by the user through the terminal device, and determines the CPU instruction set in the working area according to the instruction set selection instruction. The CPU instruction set includes one or more target instructions, which are used to implement a preset operation. The system acquires a combination instruction input by the user through the terminal device, combines the target instruction in the CPU instruction set with the CPU initial frame according to the combination instruction, and generates the module component in the working area according to the combination result. The module component is used to implement the preset operation of the target instruction. Obtain the completion command input by the user through the terminal device, and generate a CPU architecture diagram based on the module components and the initial CPU framework.

2. The method according to claim 1, characterized in that, After generating the CPU architecture diagram based on the module components and the initial CPU framework, the method further includes: The simulation command input by the user through the terminal device is obtained, and the CPU architecture diagram is simulated.

3. The method according to claim 2, characterized in that, After simulating the CPU architecture diagram, the method further includes: The CPU architecture diagram obtains a first instruction input by the user based on the CPU instruction set, and performs corresponding operations according to the first instruction to obtain the execution result. If the execution result is correct, a message indicating successful simulation will be displayed. If the execution result is incorrect, an error message will be displayed.

4. The method according to any one of claims 1 to 3, characterized in that, The working area includes a structure display area, an instruction set area, a module component area, an information display area, and a confirmation area; the structure display area is used to display the initial CPU framework, the instruction set area is used to display all instructions in the instruction set, the module component area is used to display the module components, the information display area is used to prompt the operation to be performed in the current step, and the confirmation area is used to input the completion command; The step of obtaining the module selection instruction input by the user through the terminal device and determining the initial CPU framework based on the module selection instruction includes: Obtain the first module selection instruction input by the user through the terminal device, and determine the control module in the structure display area; Obtain the second module selection instruction input by the user through the terminal device, and determine the data path module in the structure display area; The CPU initial framework is composed of the control module and the data path module.

5. The method according to claim 4, characterized in that, The step of combining the target instruction from the CPU instruction set with the CPU initial framework according to the combination instruction, and generating the module component in the working area according to the combination result, includes: According to the combined instruction, the target instruction in the CPU instruction set is obtained from the instruction set region and combined with the control module; Based on the combination result, the module component is generated in the module component area, wherein the module component is specifically used to constitute the data path module and implement the function of the target instruction.

6. The method according to claim 4, characterized in that, After generating the CPU architecture diagram based on the module components and the initial CPU framework, the method further includes: obtaining the component selection instruction input by the user through the terminal device, adding the module components into the data path module to form the data path module, and obtaining the CPU architecture diagram.

7. The method according to claim 4, characterized in that, The method further includes: Obtain the mode switching command input by the user through the terminal device, and switch to teaching mode or normal mode according to the mode switching command; When in teaching mode, the work area not involved in the current step is locked, and the operation and operation requirements to be performed in the current step are displayed in the information display area; After completing the current step, the work area involved in the next step is unlocked, and the operation and operation requirements to be performed in the next step are displayed in the information display area.

8. The method according to any one of claims 1 to 3, characterized in that, After generating the CPU architecture diagram based on the module components and the initial CPU framework, the method further includes: Generate an instruction data flow graph based on the instruction set and the CPU initial framework; A CPU structure diagram is generated based on the module components and the initial CPU framework.

9. A terminal device, characterized in that, include: A processor and a memory; the memory stores a computer-readable program that can be executed by the processor; when the processor executes the computer-readable program, it implements the method as described in any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores one or more programs, which can be executed by one or more processors to implement the method as described in any one of claims 1 to 8.

11. A computer program product, characterized in that, The computer program product is used to implement the method as described in any one of claims 1 to 8.

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