Gamma voltage conversion circuit, display device, and gamma voltage conversion method

Abstract

The present disclosure provides a gamma voltage conversion circuit, which includes: having a plurality of first input terminals and a plurality of first voltage division output terminals; one first input terminal is configured to receive a first gamma voltage signal input by a first gamma channel, and a first voltage division circuit is configured to generate a plurality of first analog voltage signals according to the first gamma voltage signal, and one first voltage division output terminal is configured to output one first analog voltage signal; a Gray code control circuit, configured to generate a corresponding Gray code control signal according to the gray scale value to be displayed and output it; a first encoding circuit, configured to generate a plurality of second analog voltage signals according to the Gray code control signal and one of the plurality of first analog voltage signals and output them; a first output control circuit, configured to generate an analog gray scale voltage signal according to the plurality of second analog voltage signals and output it. The present disclosure also provides a display device and a gamma voltage conversion method.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a gamma voltage conversion circuit, a display device, and a gamma voltage conversion method. Background Art

[0002] An organic light-emitting diode (OLED) display substrate is a display substrate different from the traditional liquid crystal display (LCD). It has the advantages of active light emission, good temperature characteristics, low power consumption, fast response, bendability, ultra-thinness, and low cost. It has become one of the important development directions of new-generation display devices. In addition, active-matrix organic light-emitting diode (AMOLED) display substrates have also started to stand out in the small-size field. In the corresponding display system, the corresponding gamma voltage needs to be converted into an analog gray-scale voltage for display. At this time, a corresponding gamma voltage conversion circuit is required. At present, the traditional conversion circuit has relatively large noise, slow response speed, and problems such as gray-scale display brightness jitter and poor uniformity of the display substrate during gamma voltage conversion. Summary of the Invention

[0003] The present disclosure aims to at least solve one of the technical problems existing in the prior art, and provides a gamma voltage conversion circuit, a display device, and a gamma voltage conversion method.

[0004] To achieve the above object, in a first aspect, an embodiment of the present disclosure provides a gamma voltage conversion circuit, which includes:

[0005] A first voltage division circuit having a plurality of first input terminals and a plurality of first voltage division output terminals; one of the first input terminals is configured to receive a first gamma voltage signal input by a first gamma channel, and the first voltage division circuit is configured to generate multiple first analog voltage signals according to the first gamma voltage signal, and one of the first voltage division output terminals is configured to output one of the first analog voltage signals;

[0006] A Gray code control circuit for generating a corresponding Gray code control signal according to the gray-scale value to be displayed and outputting it;

[0007] A first encoding circuit for generating multiple second analog voltage signals according to the Gray code control signal and one of the multiple first analog voltage signals and outputting them;

[0008] A first output control circuit for generating an analog gray-scale voltage signal according to the multiple second analog voltage signals and outputting it.

[0009] In some embodiments, the first voltage dividing circuit includes a plurality of resistors connected in series. The connection node between any two serially connected resistors is a series node, and one of the series nodes corresponds to one of the first voltage dividing output terminals.

[0010] In some embodiments, the Gray code control signal includes a first Gray code signal and a second Gray code signal, wherein each bit of the first Gray code signal and the second Gray code signal is opposite;

[0011] The first encoding circuit is specifically configured to generate and output the multiple second analog voltage signals according to one of the first Gray code signal, the second Gray code signal, and the multiple first analog voltage signals.

[0012] In some embodiments, the first encoding circuit includes a plurality of switch sub - circuits and a plurality of output sub - circuits;

[0013] Each switch sub - circuit includes multiple branches. Each branch has a second input terminal and multiple third input terminals. One second input terminal is configured to receive one of the first analog voltage signals output from one of the first voltage dividing output terminals, and one third input terminal is configured to receive a first preset bit of the Gray code control signal. Each branch is configured to control its own on - off state according to the multiple first preset bits of the Gray code control signal, and generate a voltage signal to be output according to the received first analog voltage signal when in the conducting state;

[0014] Each output sub - circuit has multiple fourth input terminals and multiple fifth input terminals. One fourth input terminal is configured to receive the voltage signal to be output from one of the switch sub - circuits, and one fifth input terminal is configured to receive a second preset bit of the Gray code control signal. Each output sub - circuit is configured to control its connection with one of the switch sub - circuits according to the multiple second preset bits of the Gray code control signal, and generate and output the second analog voltage signal according to the received voltage signal to be output.

[0015] In some embodiments, the first analog voltage signal, the first voltage dividing output terminal, and the gray - scale value correspond one - to - one, the second analog gray - scale voltage and the gray - scale value correspond one - to - one, and there are 2m levels of gray - scale values, where m is a positive integer;

[0016] The multiple switch sub - circuits include multiple first switch sub - circuits and multiple second switch sub - circuits. Each first switch sub - circuit includes 2n branches, and each second switch sub - circuit includes 2n branches, where n is a positive integer;

[0017] Sort in ascending order according to the corresponding gray scale values, and every n adjacent first voltage dividing output terminals are grouped; wherein, for N groups of the first voltage dividing output terminals corresponding to the gray scale values less than or equal to a preset first threshold, every two adjacent first voltage dividing output terminals are connected to each second input terminal within a first switching sub-circuit, and N is a positive integer; for M groups of the first voltage dividing output terminals corresponding to the gray scale values greater than or equal to a preset second threshold, every two adjacent first voltage dividing output terminals are connected to each second input terminal of a second switching sub-circuit, the second threshold is greater than the first threshold, and M is a positive integer.

[0018] In some embodiments, the multiple switching sub-circuits further include a third switching sub-circuit and multiple fourth switching sub-circuits, the third switching sub-circuit includes k branches, and each fourth switching sub-circuit includes n branches, where k=(2m - N*n - M*n) / n, and k is a positive integer;

[0019] For multiple groups of the first voltage dividing output terminals corresponding to the gray scale values greater than the first threshold and less than the second threshold, wherein, the gray scale value corresponding to each group of the first voltage dividing output terminals includes the smallest first gray scale value and n - 1 second gray scale values, and the first voltage dividing output terminals corresponding to every n adjacent first gray scale values are alternately connected to the n second input terminals of the third switching sub-circuit and each second input terminal of a fourth switching sub-circuit in sequence.

[0020] In some embodiments, m = 8, n = 4, the corresponding gray scale values are sorted in ascending order from level 0 to level 255, and the Gray code control signal includes bit 0 to bit 7 in order from the lowest bit to the highest bit; the first threshold is equal to the gray scale value of level 31; the second threshold is equal to the gray scale value of level 224.

[0021] In some embodiments, the first preset bits corresponding to the first switching sub-circuit and the second switching sub-circuit both include bit 0 to bit 4, the first preset bit corresponding to the third switching sub-circuit includes bit 2 to bit 7, and the first preset bit corresponding to the fourth switching sub-circuit includes bit 3 to bit 7.

[0022] In some embodiments, the first encoding circuit has multiple switching transistors, and the switching transistors include: a first transistor to an eighth transistor, whose control electrodes are respectively used to receive opposite bit 0 to opposite bit 7; a ninth transistor to a sixteenth transistor, whose control electrodes are respectively used to receive bit 0 to bit 7;

[0023] One of the first switch sub - circuits and one of the second switch sub - circuits each include a first branch to an eighth branch. Among them, the first branch includes a first transistor, a second transistor, a third transistor, a twelfth transistor, and a thirteenth transistor connected in sequence, which are configured to receive the first analog voltage signal output from the first voltage - dividing output terminal corresponding to the 5 + 8i - th gray - scale value; the second branch includes a ninth transistor, a second transistor, a third transistor, a twelfth transistor, and a thirteenth transistor connected in sequence, which are configured to receive the first analog voltage signal output from the first voltage - dividing output terminal corresponding to the 4 + 8i - th gray - scale value; the third branch includes a first transistor, a tenth transistor, a third transistor, a twelfth transistor, and a thirteenth transistor connected in sequence, which are configured to receive the first analog voltage signal output from the first voltage - dividing output terminal corresponding to the 6 + 8i - th gray - scale value; the fourth branch includes a ninth transistor, a tenth transistor, a third transistor, a twelfth transistor, and a thirteenth transistor connected in sequence, which are configured to receive the first analog voltage signal output from the first voltage - dividing output terminal corresponding to the 7 + 8i - th gray - scale value; the fifth branch includes a first transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor connected in sequence, which are configured to receive the first analog voltage signal output from the first voltage - dividing output terminal corresponding to the 1 + 8i - th gray - scale value; the sixth branch includes a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor connected in sequence, which are configured to receive the first analog voltage signal output from the first voltage - dividing output terminal corresponding to the 0 + 8i - th gray - scale value; the seventh branch includes a first transistor, a second transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor connected in sequence, which are configured to receive the first analog voltage signal output from the first voltage - dividing output terminal corresponding to the 2 + 8i - th gray - scale value; the eighth branch includes a ninth transistor, a second transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor connected in sequence, which are configured to receive the first analog voltage signal output from the first voltage - dividing output terminal corresponding to the 3 + 8i - th gray - scale value;

[0024] Among them, for the first switch sub - circuit, the value of i is any one of 0, 1, 2, 3, and for the second switch sub - circuit, the value of i is any one of 28, 29, 30, 31.

[0025] In some embodiments, the twelfth transistor and the thirteenth transistor are multiplexed among the first branch to the eighth branch, the third transistor is multiplexed among the first branch to the fourth branch, the eleventh transistor is multiplexed among the fifth branch to the eighth branch, one second transistor is multiplexed between the first branch and the second branch, one tenth transistor is multiplexed between the third branch and the fourth branch, another tenth transistor is multiplexed between the fifth branch and the sixth branch, and another second transistor is multiplexed between the seventh branch and the eighth branch.

[0026] In some embodiments, one of the fourth switch sub-circuits includes a ninth branch to a twelfth branch. Among them, the ninth branch includes a fourth transistor, a thirteenth transistor, a sixth transistor, a fifteenth transistor, and a sixteenth transistor connected in sequence, and is configured to receive the first analog voltage signal output from the first voltage dividing output terminal corresponding to the first gray scale value of the 60 + 32j level; the tenth branch includes a twelfth transistor, a thirteenth transistor, a sixth transistor, a fifteenth transistor, and a sixteenth transistor connected in sequence, and is configured to receive the first analog voltage signal output from the first voltage dividing output terminal corresponding to the first gray scale value of the 52 + 32j level; the eleventh branch includes a fourth transistor, a fifth transistor, a sixth transistor, a fifteenth transistor, and a sixteenth transistor connected in sequence, and is configured to receive the first analog voltage signal output from the first voltage dividing output terminal corresponding to the first gray scale value of the 44 + 32j level; the twelfth branch includes a twelfth transistor, a fifth transistor, a sixth transistor, a fifteenth transistor, and a sixteenth transistor connected in sequence, and is configured to receive the first analog voltage signal output from the first voltage dividing output terminal corresponding to the first gray scale value of the 36 + 32j level; where j takes any one of 0, 1, 2, 3, 4, 5;

[0027] The third switch sub - circuit includes a plurality of basic units. One basic unit includes the thirteenth to sixteenth branches. Among them, the thirteenth branch includes a third transistor, a thirteenth transistor, a sixth transistor, a fifteenth transistor, and a sixteenth transistor connected in sequence, and is configured to receive the first analog voltage signal output from the first voltage - dividing output terminal corresponding to the first gray - scale value of the 56 + 32j level; the fourteenth branch includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, a sixth transistor, a fifteenth transistor, and a sixteenth transistor connected in sequence, and is configured to receive the first analog voltage signal output from the first voltage - dividing output terminal corresponding to the first gray - scale value of the 48 + 32j level; the fifteenth branch includes a third transistor, a fifth transistor, a sixth transistor, a fifteenth transistor, and a sixteenth transistor connected in sequence, and is configured to receive the first analog voltage signal output from the first voltage - dividing output terminal corresponding to the first gray - scale value of the 40 + 32j level; the sixteenth branch includes an eleventh transistor, a twelfth transistor, a fifth transistor, a sixth transistor, a fifteenth transistor, and a sixteenth transistor connected in sequence, and is configured to receive the first analog voltage signal output from the first voltage - dividing output terminal corresponding to the first gray - scale value of the 32 + 32j level; for one basic unit, a fourth transistor is further connected between the eleventh transistor of the fourteenth branch and the fifth transistor of the fifteenth branch; for two adjacent basic units, a fourth transistor is further connected between the eleventh transistor of the sixteenth branch of one basic unit and the thirteenth transistor of the thirteenth branch of the other basic unit.

[0028] In some embodiments, the ninth to twelfth branches multiplex the sixth transistor, the fifteenth transistor, and the sixteenth transistor. The ninth and tenth branches multiplex the thirteenth transistor. The eleventh and twelfth branches multiplex the fifth transistor;

[0029] For one basic unit, the thirteenth to sixteenth branches multiplex the sixth transistor, the fifteenth transistor, and the sixteenth transistor. The thirteenth and fourteenth branches multiplex the thirteenth transistor. The fifteenth and sixteenth branches multiplex the fifth transistor.

[0030] In some embodiments, the plurality of output sub - circuits include a first output sub - circuit, a second output sub - circuit, and a third output sub - circuit. Each output sub - circuit has four of the fourth input terminals, which are respectively configured to receive the to - be - output voltage signals output from the corresponding plurality of first switch sub - circuits, the plurality of second switch sub - circuits, the third switch sub - circuit, and the plurality of fourth switch sub - circuits;

[0031] Both the first output sub - circuit and the second output sub - circuit are configured to output one path of the second analog voltage signal according to the to - be - output voltage signal, and the third output sub - circuit is configured to output two identical second analog voltage signals according to the to - be - output voltage.

[0032] In some embodiments, the first output sub - circuit is configured to control itself to be connected to one of the first switch sub - circuits or one of the second switch sub - circuits according to the 5th, 6th, and 7th bits of the Gray - code control signal, or control itself to be connected to the third switch sub - circuit or one of the fourth switch sub - circuits according to the 2nd and 3rd bits of the Gray - code control signal;

[0033] The second output sub - circuit is configured to control itself to be connected to one of the first switch sub - circuits or one of the second switch sub - circuits according to the 5th, 6th, and 7th bits of the Gray - code control signal, or control itself to be connected to the third switch sub - circuit or one of the fourth switch sub - circuits according to the 0th and 1st bits of the Gray - code control signal;

[0034] The third output sub - circuit is configured to control itself to be connected to one of the first switch sub - circuits or one of the second switch sub - circuits according to the 5th, 6th, and 7th bits of the Gray - code control signal, or control itself to be connected to the third switch sub - circuit or one of the fourth switch sub - circuits according to the 1st bit of the Gray - code control signal.

[0035] In some embodiments, each output sub - circuit has multiple switching transistors. The switching transistors include: the first transistor to the eighth transistor, whose control electrodes are respectively used to receive the opposite 0th bit to the opposite 7th bit; the ninth transistor to the sixteenth transistor, whose control electrodes are respectively used to receive the 0th bit to the 7th bit;

[0036] The first output sub - circuit is connected to the output ends of the multiple fourth switch sub - circuits through the third transistor and the twelfth transistor, and is also connected to the output ends of the multiple fourth switch sub - circuits through the fourth transistor and the eleventh transistor; the first output sub - circuit is connected to the third switch sub - circuit through the eleventh transistor and the twelfth transistor, and is also connected to the third switch sub - circuit through the fourth transistor and the third transistor; the first output sub - circuit is connected to the output ends of the multiple first switch sub - circuits through the fourteenth transistor, the fifteenth transistor, and the sixteenth transistor; the first output sub - circuit is connected to the output ends of the multiple second switch sub - circuits through the fourteenth transistor, the fifteenth transistor, and the eighth transistor;

[0037] The second output sub-circuit is connected to the output ends of the plurality of fourth switch sub-circuits through a second transistor and a ninth transistor, and is also connected to the output ends of the plurality of fourth switch sub-circuits through a first transistor and a tenth transistor; the second output sub-circuit is connected to the third switch sub-circuit through the ninth transistor and the tenth transistor, and is also connected to the third switch sub-circuit through the first transistor and the second transistor; the second output sub-circuit is connected to the output ends of the plurality of first switch sub-circuits through a fourteenth transistor, a fifteenth transistor and a sixteenth transistor; the second output sub-circuit is connected to the output ends of the plurality of second switch sub-circuits through the fourteenth transistor, the fifteenth transistor and an eighth transistor.

[0038] The third output sub-circuit is connected to the output ends of the plurality of fourth switch sub-circuits through a second transistor; the third output sub-circuit is connected to the third switch sub-circuit through a tenth transistor; the third output sub-circuit is connected to the output ends of the plurality of first switch sub-circuits through a fourteenth transistor, a fifteenth transistor and a sixteenth transistor; the third output sub-circuit is connected to the output ends of the plurality of second switch sub-circuits through the fourteenth transistor, the fifteenth transistor and an eighth transistor.

[0039] In some embodiments, the first output control circuit includes an operational amplifier. The input end of the first output control circuit is configured to receive four second analog voltage signals output by the plurality of output sub-circuits, and the operational amplifier is configured to perform weighted summation according to the four second analog voltage signals to generate the analog gray-scale voltage signal.

[0040] In some embodiments, the gamma voltage conversion circuit further includes:

[0041] A second voltage dividing circuit, having a plurality of sixth input ends and a plurality of second voltage dividing output ends. One of the sixth input ends is configured to receive a second gamma voltage signal input by a second gamma channel. The second voltage dividing circuit is configured to generate multiple third analog voltage signals according to the second gamma voltage signal, and one of the second voltage dividing output ends is configured to output one of the third analog voltage signals;

[0042] A second encoding circuit, configured to generate and output multiple fourth analog voltage signals according to the Gray code control signal and one of the multiple third analog voltage signals;

[0043] A second output control circuit, configured to generate and output an analog gray-scale voltage signal according to the multiple fourth analog voltage signals.

[0044] In some embodiments, it further includes:

[0045] The first encoding circuit and the second encoding circuit both include a plurality of switching transistors. The switching transistors in the first encoding circuit are one of P-type transistors and N-type transistors, and the switching transistors in the second encoding circuit are the other of P-type transistors and N-type transistors. Each bit of the control signal corresponding to the switching transistors in the first encoding circuit is opposite to each bit of the control signal corresponding to the switching transistors in the second encoding circuit.

[0046] In a second aspect, an embodiment of the present disclosure provides a display device, which includes: a gamma voltage conversion circuit

[0047] The gamma voltage conversion circuit uses the gamma voltage conversion circuit described in any one of the above embodiments.

[0048] In a third aspect, an embodiment of the present disclosure provides a gamma voltage conversion method, which is applied to the gamma voltage conversion circuit described in any one of the above embodiments. The method includes:

[0049] Generating a plurality of first analog voltage signals according to a first gamma voltage signal input by a first gamma channel;

[0050] Generating a corresponding Gray code control signal according to the gray scale value to be displayed;

[0051] Generating a plurality of second analog voltage signals according to the Gray code control signal and one of the plurality of first analog voltage signals;

[0052] Generating and outputting an analog gray scale voltage signal according to the plurality of second analog voltage signals.

[0053] In some embodiments, the generating a plurality of second analog voltage signals according to the Gray code control signal and one of the plurality of first analog voltage signals includes:

[0054] Controlling the on / off state of a branch of one switching sub-circuit of itself according to a plurality of first preset bits of the Gray code control signal, and generating a voltage signal to be output according to the first analog voltage signal received by the conducting branch;

[0055] Controlling the output sub-circuit of itself to be connected to the switching sub-circuit according to a plurality of second preset bits of the Gray code control signal, and generating and outputting the second analog voltage signal according to the voltage signal to be output.

[0056] In some embodiments, the generating and outputting an analog gray scale voltage signal according to the plurality of second analog voltage signals includes:

[0057] Performing weighted summation on the plurality of second analog voltage signals to generate the analog gray scale voltage signal.

[0058] In some embodiments, the method further comprises:

[0059] generating a plurality of third analog voltage signals according to the second gamma voltage signal inputted from the second gamma channel;

[0060] generating a plurality of fourth analog voltage signals according to the Gray code control signal and one of the plurality of third analog voltage signals;

[0061] An analog grayscale voltage signal is generated according to the multiple fourth analog voltage signals and outputted. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing detailed example embodiments with reference to the accompanying drawings. In the accompanying drawings:

[0063] Figure 1 A schematic structural diagram of a gamma voltage conversion circuit provided by an embodiment of the present disclosure;

[0064] Figure 2 A schematic structural diagram of a first encoding circuit provided in an embodiment of the present disclosure;

[0065] Figure 3 A schematic diagram of another first encoding circuit provided by an embodiment of the present disclosure;

[0066] Figure 4a A schematic structural diagram of a first switch sub-circuit or a second switch sub-circuit provided by the present disclosure;

[0067] Figure 4b A schematic structural diagram of a fourth switch sub-circuit provided by the present disclosure;

[0068] Figure 4c A schematic structural diagram of multiple basic units of a third switch sub-circuit provided by the present disclosure;

[0069] Figure 5 A schematic diagram of an output sub-circuit provided in an embodiment of the present disclosure;

[0070] Figure 6a A schematic structural diagram of a first output sub-circuit provided in an embodiment of the present disclosure;

[0071] Figure 6b A schematic structural diagram of a second output sub-circuit provided in an embodiment of the present disclosure;

[0072] Figure 6cSchematic diagram of a third output sub - circuit provided by an embodiment of the present disclosure;

[0073] Figure 7 Schematic diagram of another gamma voltage conversion circuit provided by an embodiment of the present disclosure;

[0074] Figure 8 Flowchart of a gamma voltage conversion method provided by an embodiment of the present disclosure;

[0075] Figure 9 Flowchart of a specific implementation method for step S3 in an embodiment of the present disclosure. Detailed implementation manners

[0076] To enable those skilled in the art to better understand the technical solutions of the present disclosure, the gamma voltage conversion circuit, display device, and gamma voltage conversion method provided by the present disclosure will be described in detail below with reference to the accompanying drawings.

[0077] In the following, example embodiments will be described more fully with reference to the accompanying drawings. However, the example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0078] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It will also be understood that when the terms "comprises" and / or "is made of" are used in this specification, it specifies the presence of the stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0079] It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, without departing from the teachings of the present disclosure, the first element, first component, or first module discussed below may be referred to as the second element, second component, or second module.

[0080] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless expressly so defined herein.

[0081] Figure 1 This is a schematic structural diagram of a gamma voltage conversion circuit provided by an embodiment of the present disclosure. As Figure 1 shown, the gamma voltage conversion circuit includes: a first voltage division circuit 1, a Gray code control circuit 2, a first encoding circuit 3, and a first output control circuit 4.

[0082] Among them, the first voltage division circuit 1 has multiple first input terminals 101 and multiple first voltage division output terminals 102; one first input terminal 101 is configured to receive a first gamma voltage signal input by a first gamma (Gamma) channel, and the first voltage division circuit 1 is configured to generate multiple first analog voltage signals according to the first gamma voltage signal, and one first voltage division output terminal 102 is configured to output one first analog voltage signal.

[0083] The Gray code control circuit 2 is used to generate a corresponding Gray code control signal according to the gray scale value to be displayed and output it.

[0084] The first encoding circuit 3 is used to generate multiple second analog voltage signals according to the Gray code control signal and one of the multiple first analog voltage signals and output them.

[0085] The first output control circuit 4 is used to generate an analog gray scale voltage signal according to the multiple second analog voltage signals and output it.

[0086] In some embodiments, the first voltage division circuit 1 includes multiple serially connected resistors, and the connection node between any two serially connected resistors is a series node, and one series node corresponds to one first voltage division output terminal; in some embodiments, the first voltage division circuit 1 is also called a resistor string.

[0087] In some embodiments, the Gray code control signal includes a first Gray code signal and a second Gray code signal, wherein each bit of the first Gray code signal and the second Gray code signal is opposite. The first encoding circuit 3 is specifically used to generate multiple second analog voltage signals according to the first Gray code signal, the second Gray code signal, and one of the multiple first analog voltage signals and output them.

[0088] In some embodiments, the mutual conversion between binary codes and Gray codes can be performed based on the following methods: The conversion from binary codes to Gray codes includes retaining the highest bit of the binary code, taking the exclusive OR result of the highest bit and the second highest bit of the binary code as the second highest bit of the Gray code, and so on. Subsequently, taking the exclusive OR result of the previous bit and the current bit of the binary code as the current bit of the Gray code, the Gray code corresponding to the binary code can be obtained; The conversion from Gray codes to binary codes includes taking 0 and the highest bit of the Gray code as the highest bit of the binary code, taking the exclusive OR result of the highest bit of the binary code and the second highest bit of the Gray code as the second highest bit of the binary code, and so on. Subsequently, taking the exclusive OR result of the previous bit of the binary code and the current bit of the Gray code as the current bit of the binary code, the binary code corresponding to the Gray code can be obtained.

[0089] Corresponding to the current gamma voltage conversion scheme based on binary codes, problems such as display brightness jitter, uneven brightness, and power supply fluctuations will occur during the switching of each gray level. This is mainly because when performing gray level conversion based on binary codes, there may be a situation where multiple bits flip simultaneously. For example, when switching from the 127th gray level to the 128th gray level, the corresponding binary code changes from 01111111 to 10000000, and 8 bits will flip simultaneously, generating relatively large glitches and noises; At the same time, because the wire lengths and load sizes are different, the switches controlled by 8 bits cannot act simultaneously, and an intermediate state may be formed during the flip, such as from 01111111 to 00011111 and then to 10000000. The intermediate state 00011111, which is the 31st gray level, is not desired. It will cause the voltage corresponding to the 31st gray level to be briefly connected during the switching process, resulting in fluctuations in the output voltage and being unable to quickly and accurately output the required gray level, that is, the voltage corresponding to the 128th gray level, affecting the response speed and the time to reach the steady state; Moreover, due to the short charging time for each row, it is easy to cause insufficient charging at the far end and low brightness, resulting in poor uniformity of the panel and the device; Multiple bits switching simultaneously will also cause a large instantaneous load draw on the digital circuit and the analog circuit, resulting in power supply fluctuations. When using Gray codes, when switching from the 127th gray level to the 128th gray level, the corresponding Gray code changes from 01001000 to 11000000, and only the 7th bit and the 3rd bit change. Another example is when switching from the 199th gray level to the 200th gray level, the corresponding Gray code changes from 10100100 to 10101100, and only the 3rd bit changes. And in the application of Gray codes, the situation where only one bit changes accounts for the majority. Therefore, using Gray codes to participate in the conversion greatly reduces the indeterminate states during the conversion process, avoids fluctuations in the output voltage caused by non-simultaneous switching of multiple bits during the gray level switching process, enables the output to reach the target voltage more quickly and accurately, and improves the response speed.

[0090] In the embodiments of the present disclosure, a coding circuit based on Gray code is used for gamma voltage conversion. During the adjacent gray-scale switching process corresponding to the Gray code, there are at most two-bit changes, avoiding multi-bit switching and the indeterminate state and intermediate state during this process, improving the response speed, reducing circuit glitches and noise, and making the brightness change of gray-scale display smoother during gray-scale-by-gray-scale switching, thereby solving problems such as display jitter and power supply fluctuations caused by gray-scale-by-gray-scale switching. Further, since the output reaches the target potential more accurately, the voltages at the far end and near end of the panel are consistent, so the brightness is consistent, and the uniformity of the panel is better.

[0091] Figure 2 FIG. is a schematic structural diagram of a first coding circuit provided by an embodiment of the present disclosure. Specifically, this structure is a specific and optional implementation scheme based on Figure 1 the gamma voltage conversion circuit shown. As Figure 2 shown, the first coding circuit includes a plurality of switch sub-circuits 301 and a plurality of output sub-circuits 302.

[0092] Among them, each switch sub-circuit 301 includes multiple branches. Each branch has a second input terminal 3011 and multiple third input terminals 3012. One second input terminal 3011 is configured to receive a first analog voltage signal output from a first voltage-dividing output terminal, and one third input terminal 3012 is configured to receive a first preset bit of a Gray code control signal; each branch is configured to control its own on-off state according to multiple first preset bits of the Gray code control signal, and generate a to-be-output voltage signal according to the received first analog voltage signal when in the conducting state.

[0093] Among them, each output sub-circuit 302 has multiple fourth input terminals 3021 and multiple fifth input terminals 3022. One fourth input terminal 3021 is configured to receive a to-be-output voltage signal output from a switch sub-circuit 301, and one fifth input terminal 3022 is configured to receive a second preset bit of the Gray code control signal; each output sub-circuit 302 is configured to control itself to be connected to a switch sub-circuit 301 according to multiple second preset bits of the Gray code control signal, and generate and output a second analog voltage signal according to the received to-be-output voltage signal. It should be noted that in the embodiments of the present disclosure, the circuit connected between a second input terminal and the output terminal of the switch sub-circuit is used as a branch in the switch sub-circuit.

[0094] Figure 3 FIG. is a schematic diagram of another first coding circuit provided by an embodiment of the present disclosure. Specifically, this structure is a specific and optional implementation scheme based on Figure 2 the first coding circuit shown; among them, the first analog voltage signal and the first voltage-dividing output terminal correspond to the gray-scale values one by one, the second analog gray-scale voltage signal corresponds to the gray-scale values one by one, and there are 2m grayscale value, m is a positive integer.

[0095] Among them, Figure 3 As shown, the multiple switch subcircuits include multiple first switch subcircuits 501 and multiple second switch subcircuits 502. Each first switch subcircuit 501 includes 2n branches, and each second switch subcircuit 502 includes 2n branches, where n is a positive integer. The first voltage-dividing output terminals are arranged in ascending order according to their corresponding grayscale values, with every n adjacent first voltage-dividing output terminals forming a group. For N groups of first voltage-dividing output terminals whose corresponding grayscale values are less than or equal to a preset first threshold, every two adjacent groups of first voltage-dividing output terminals are connected to each second input terminal 3011 within a first switch subcircuit 501, where N is a positive integer. For M groups of first voltage-dividing output terminals whose corresponding grayscale values are greater than or equal to a preset second threshold, every two adjacent groups of first voltage-dividing output terminals are connected to each second input terminal 3011 of a second switch subcircuit 502, where the second threshold is greater than the first threshold, and M is a positive integer. As shown in the figure, the first switch subcircuit 501 corresponds to the output terminal D, and the second switch subcircuit 502 corresponds to the output terminal E.

[0096] In some embodiments, m=8, n=4, the corresponding grayscale values are sorted from small to large, including level 0 to level 255, and the Gray code control signal is sorted from low to high, including bit 0 to bit 7; the first threshold is equal to the grayscale value of level 31; the second threshold is equal to the grayscale value of level 224.

[0097] Specifically, since the output of the first voltage divider circuit is nonlinear, especially when the output corresponds to low grayscale (for example, level 0 to level 31 in this embodiment) and high grayscale (for example, level 224 to level 255 in this embodiment), the nonlinearity is large, so the low grayscale and high grayscale parts need to be output grayscale by grayscale.

[0098] In some embodiments, the first encoding circuit has a plurality of switching transistors, including: a first transistor 601 to an eighth transistor 608, whose control electrodes are respectively used to receive the opposite 0th bit to the opposite 7th bit. <0> Indicates the opposite 0th bit, and other identifiers can be deduced in the same way; the ninth transistor 609 to the sixteenth transistor 616, whose control electrodes are used to receive the 0th bit to the 7th bit respectively, in the figure, S <0> Indicates the 0th bit, and the same applies to other identifiers.

[0099] Figure 4a This is a schematic diagram of the structure of a first switch sub-circuit or a second switch sub-circuit provided by the present disclosure. Figure 4aAs shown, corresponding to the case of m = 8 and n = 4, the structure of a first switch sub - circuit 501 and a second switch sub - circuit 502 is exemplarily shown. It should be noted that this value will not limit the technical solutions in this embodiment and subsequent embodiments. It is only for exemplary description. When the values of m and n are other values, they can also be applicable to the technical solutions of this application.

[0100] Among them, the first preset bits corresponding to the first switch sub - circuit 501 and the second switch sub - circuit 502 both include the 0th bit to the 4th bit.

[0101] Among them, there are a total of 4 first switch sub-circuits 501 and 4 second switch sub-circuits 502. A first switch sub-circuit 501 and a second switch sub-circuit 502 both include a first branch to an eighth branch. Among them, the first branch includes a first transistor 601, a second transistor 602, a third transistor 603, a twelfth transistor 612, and a thirteenth transistor 613 connected in sequence, which are configured to receive a first analog voltage signal output from a first voltage dividing output terminal corresponding to the gray scale value of the (5 + 8i)-th level. In the figure, INH<5 + 8i> is used to represent the object that this branch is configured to receive, and other identifications can be deduced by analogy; the second branch includes a ninth transistor 609, a second transistor 602, a third transistor 603, a twelfth transistor 612, and a thirteenth transistor 613 connected in sequence, which are configured to receive a first analog voltage signal output from a first voltage dividing output terminal corresponding to the gray scale value of the (4 + 8i)-th level; the third branch includes a first transistor 601, a tenth transistor 610, a third transistor 603, a twelfth transistor 612, and a thirteenth transistor 613 connected in sequence, which are configured to receive a first analog voltage signal output from a first voltage dividing output terminal corresponding to the gray scale value of the (6 + 8i)-th level; the fourth branch includes a ninth transistor 609, a tenth transistor 610, a third transistor 603, a twelfth transistor 612, and a thirteenth transistor 613 connected in sequence, which are configured to receive a first analog voltage signal output from a first voltage dividing output terminal corresponding to the gray scale value of the (7 + 8i)-th level; the fifth branch includes a first transistor 601, a tenth transistor 610, an eleventh transistor 611, a twelfth transistor 612, and a thirteenth transistor 613 connected in sequence, which are configured to receive a first analog voltage signal output from a first voltage dividing output terminal corresponding to the gray scale value of the (1 + 8i)-th level; the sixth branch includes a ninth transistor 609, a tenth transistor 610, an eleventh transistor 611, a twelfth transistor 612, and a thirteenth transistor 613 connected in sequence, which are configured to receive a first analog voltage signal output from a first voltage dividing output terminal corresponding to the gray scale value of the (0 + 8i)-th level; the seventh branch includes a first transistor 601, a second transistor 602, an eleventh transistor 611, a twelfth transistor 612, and a thirteenth transistor 613 connected in sequence, which are configured to receive a first analog voltage signal output from a first voltage dividing output terminal corresponding to the gray scale value of the (2 + 8i)-th level; the eighth branch includes a ninth transistor 609, a second transistor 602, an eleventh transistor 611, a twelfth transistor 612, and a thirteenth transistor 613 connected in sequence, which are configured to receive a first analog voltage signal output from a first voltage dividing output terminal corresponding to the gray scale value of the (3 + 8i)-th level.

[0102] Among them, for the first switch sub-circuit 501, the value of i is any one of 0, 1, 2, and 3. For the second switch sub-circuit 502, the value of i is any one of 28, 29, 30, and 31. For example Figure 4aAs shown, the first switch sub-circuit 501 corresponds to the output D terminal, and the second switch sub-circuit 502 corresponds to the output E terminal.

[0103] In some embodiments, as Figure 4a As shown, the first branch to the eighth branch multiplex the twelfth transistor 612 and the thirteenth transistor 613, the first branch to the fourth branch multiplex the third transistor 603, the fifth branch to the eighth branch multiplex the eleventh transistor 611, the first branch and the second branch multiplex a second transistor 602, the third branch and the fourth branch multiplex a tenth transistor 610, the fifth branch and the sixth branch multiplex another tenth transistor 610, and the seventh branch and the eighth branch multiplex another second transistor 602.

[0104] In some embodiments, as Figure 3 As shown, the multiple switch subcircuits further include a third switch subcircuit 503 and multiple fourth switch subcircuits 504, the third switch subcircuit 503 includes k branches, and each fourth switch subcircuit 504 includes n branches, where k = (2m-N*nM*n) / n, and k is a positive integer.

[0105] For multiple groups of first voltage-divided output terminals whose corresponding grayscale values are greater than a first threshold and less than a second threshold, where the grayscale values corresponding to each group of first voltage-divided output terminals include the smallest first grayscale value and n-1 second grayscale values, the first voltage-divided output terminals corresponding to every four adjacent first grayscale values are alternately connected to the n second input terminals 3011 of the third switch sub-circuit 503 and each second input terminal 3011 of a fourth switch sub-circuit 504. As shown in the figure, the first switch sub-circuit 501 corresponds to the output terminal B, and the second switch sub-circuit 502 corresponds to the output terminal A.

[0106] Specifically, since the output of the first voltage divider circuit is nonlinear, especially the nonlinearity is large when the output corresponds to low grayscale and high grayscale, the low grayscale and high grayscale parts need to be output grayscale by grayscale based on the first switch sub-circuit 501 and the second switch sub-circuit 502, while the grayscale located in the middle part can be output using the third switch sub-circuit and the fourth switch sub-circuit described below based on the principle of reducing the occupied area.

[0107] Figure 4b This is a schematic diagram of the structure of a fourth switch sub-circuit provided by the present disclosure. Figure 4b , which corresponds to the case where m=8 and n=4, exemplarily shows a structure of the fourth switch sub-circuit 504. The first preset bits corresponding to the fourth switch sub-circuit 504 include the 3rd to the 7th bits.

[0108] Among them, there are a total of six fourth switch sub-circuits 504. One fourth switch sub-circuit 504 includes the ninth to twelfth branches. Among them, the ninth branch includes a fourth transistor 604, a thirteenth transistor 613, a sixth transistor 606, a fifteenth transistor 615, and a sixteenth transistor 616 connected in sequence, and is configured to receive the first analog voltage signal output from the first voltage dividing output terminal 102 corresponding to the first gray scale value of the 60 + 32j level; the tenth branch includes a twelfth transistor 612, a thirteenth transistor 613, a sixth transistor 606, a fifteenth transistor 615, and a sixteenth transistor 616 connected in sequence, and is configured to receive the first analog voltage signal output from the first voltage dividing output terminal 102 corresponding to the first gray scale value of the 52 + 32j level; the eleventh branch includes a fourth transistor 604, a fifth transistor 605, a sixth transistor 606, a fifteenth transistor 615, and a sixteenth transistor 616 connected in sequence, and is configured to receive the first analog voltage signal output from the first voltage dividing output terminal 102 corresponding to the first gray scale value of the 44 + 32j level; the twelfth branch includes a twelfth transistor 612, a fifth transistor 605, a sixth transistor 606, a fifteenth transistor 615, and a sixteenth transistor 616 connected in sequence, and is configured to receive the first analog voltage signal output from the first voltage dividing output terminal 102 corresponding to the first gray scale value of the 36 + 32j level; where j can take any one of 0, 1, 2, 3, 4, 5.

[0109] In some embodiments, as Figure 4b shown, the ninth to twelfth branches share the sixth transistor 606, the fifteenth transistor 615, and the sixteenth transistor 616. The ninth and tenth branches share the thirteenth transistor 613, and the eleventh and twelfth branches share the fifth transistor 605.

[0110] Figure 4c It is a schematic structural diagram of multiple basic units of a third switch sub-circuit provided by the present disclosure. As Figure 4c shown, it corresponds to the case of m = 8 and n = 4, and exemplarily shows the structure of a third switch sub-circuit 503. Among them, the first preset bits corresponding to the third switch sub-circuit 503 include the 2nd to 7th bits.

[0111] Specifically, the third switch sub-circuit 503 includes a total of 6 basic units, two of which are exemplarily shown in the figure, wherein one basic unit includes the thirteenth branch to the sixteenth branch, wherein the thirteenth branch includes the third transistor 603, the thirteenth transistor 613, the sixth transistor 606, the fifteenth transistor 615 and the sixteenth transistor 616 connected in sequence, which is configured to receive the first analog voltage signal output from the first voltage divider output terminal 102 corresponding to the first grayscale value of the 56+32j level; the fourteenth branch includes the eleventh transistor 611, the twelfth transistor 612, the thirteenth transistor 613, the sixth transistor 606, the fifteenth transistor 615 and the sixteenth transistor 616 connected in sequence, which is configured to receive the first analog voltage signal output from the first voltage divider output terminal 100 corresponding to the first grayscale value of the 48+32j level; the fifteenth branch includes the third transistor 603, the fifth transistor 605, the sixth transistor 606, the fifteenth transistor 615 and the sixteenth transistor 616 connected in sequence The body transistor 606, the fifteenth transistor 615 and the sixteenth transistor 616 are configured to receive the first analog voltage signal output from the first voltage divider output terminal 102 corresponding to the first grayscale value of the 40+32j level; the sixteenth branch includes the eleventh transistor 611, the twelfth transistor 612, the fifth transistor 605, the sixth transistor 606, the fifteenth transistor 615 and the sixteenth transistor 616 connected in sequence, which are configured to receive the first analog voltage signal output from the first voltage divider output terminal 102 corresponding to the first grayscale value of the 32+32j level; for a basic unit, a fourth transistor 604 is further connected between the eleventh transistor 611 of the fourteenth branch and the fifth transistor 605 of the fifteenth branch; for two adjacent basic units, a fourth transistor 604 is further connected between the eleventh transistor 611 of the sixteenth branch of one basic unit and the thirteenth transistor 613 of the thirteenth branch of the other basic unit.

[0112] In some embodiments, as Figure 4c As shown, for one basic unit, the thirteenth to sixteenth branches multiplex the sixth transistor 606 , the fifteenth transistor 615 , and the sixteenth transistor 616 , the thirteenth and fourteenth branches multiplex the thirteenth transistor 613 , and the fifteenth and sixteenth branches multiplex the fifth transistor 605 .

[0113] Figure 5 This is a schematic diagram of an output subcircuit provided by an embodiment of the present disclosure. Specifically, the structure is based on Figure 3 A specific optional implementation of the first encoding circuit shown; Figure 5As shown, the multiple output sub - circuits include a first output sub - circuit 701, a second output sub - circuit 702, and a third output sub - circuit 703. Each output sub - circuit 302 has four fourth input terminals 3021, which are respectively configured to receive the to - be - output voltage signals output by the corresponding multiple first switch sub - circuits, multiple second switch sub - circuits, a third switch sub - circuit, and multiple fourth switch sub - circuits, that is, connected to the output A, B, D, and E terminals of each switch sub - circuit.

[0114] Both the first output sub - circuit 701 and the second output sub - circuit 702 are configured to output a first - path second analog voltage signal according to the to - be - output voltage signal, and the third output sub - circuit 703 is configured to output two identical second analog voltage signals according to the to - be - output voltage.

[0115] In some embodiments, each output sub - circuit has multiple switching transistors. The switching transistors include: a first transistor 601 to an eighth transistor 608, whose control electrodes are respectively used to receive the opposite bit 0 to the opposite bit 7; a ninth transistor 609 to a sixteenth transistor 616, whose control electrodes are respectively used to receive bit 0 to bit 7.

[0116] Figure 6a It is a schematic structural diagram of a first output sub - circuit provided by an embodiment of the present disclosure. It is correspondingly connected to each of the above - mentioned Figures 4a to 4c switch sub - circuits. Among them, the first output sub - circuit 701 is configured to control itself to be connected to a first switch sub - circuit or a second switch sub - circuit according to the 5th, 6th, and 7th bits of the Gray - code control signal, or control itself to be connected to the third switch sub - circuit or a fourth switch sub - circuit according to the 2nd and 3rd bits of the Gray - code control signal, that is, to be connected to the output D or E terminal according to the 5th, 6th, and 7th bits of the Gray - code control signal, or to be connected to the output A or B terminal according to the 2nd and 3rd bits of the Gray - code control signal.

[0117] As Figure 6a shown, the first output sub - circuit 701 is connected to the output terminals of multiple fourth switch sub - circuits through a third transistor 603 and a twelfth transistor 612, and is also connected to the output terminals of multiple fourth switch sub - circuits through a fourth transistor 604 and an eleventh transistor 611; the first output sub - circuit is connected to the third switch sub - circuit through the eleventh transistor 611 and the twelfth transistor 612, and is also connected to the third switch sub - circuit through the fourth transistor 604 and the third transistor 603; the first output sub - circuit is connected to the output terminals of multiple first switch sub - circuits through a fourteenth transistor 614, a fifteenth transistor 615, and a sixteenth transistor 616; the first output sub - circuit is connected to the output terminals of multiple second switch sub - circuits through a fourteenth transistor 614, a fifteenth transistor 615, and an eighth transistor 608.

[0118] Figure 6b A schematic structural diagram of a second output sub - circuit provided by an embodiment of the present disclosure. Among them, the second output sub - circuit 702 is configured to connect itself to a first switch sub - circuit or a second switch sub - circuit according to the 5th, 6th, and 7th bits of the Gray - code control signal, or connect itself to a third switch sub - circuit or a fourth switch sub - circuit according to the 0th and 1st bits of the Gray - code control signal.

[0119] As Figure 6b shown, the second output sub - circuit 702 is connected to the output terminals of multiple fourth switch sub - circuits through the second transistor 602 and the ninth transistor 609, and is also connected to the output terminals of multiple fourth switch sub - circuits through the first transistor 601 and the tenth transistor 610; the second output sub - circuit is connected to the third switch sub - circuit through the ninth transistor 609 and the tenth transistor 610, and is also connected to the third switch sub - circuit through the first transistor 601 and the second transistor 602; the second output sub - circuit 702 is connected to the output terminals of multiple first switch sub - circuits through the fourteenth transistor 614, the fifteenth transistor 615, and the sixteenth transistor 616; the second output sub - circuit 702 is connected to the output terminals of multiple second switch sub - circuits through the fourteenth transistor 614, the fifteenth transistor 615, and the eighth transistor 608.

[0120] Figure 6c A schematic structural diagram of a third output sub - circuit provided by an embodiment of the present disclosure. Among them, the third output sub - circuit 703 is configured to connect itself to a first switch sub - circuit or a second switch sub - circuit according to the 5th, 6th, and 7th bits of the Gray - code control signal, or connect itself to a third switch sub - circuit or a fourth switch sub - circuit according to the 1st bit of the Gray - code control signal.

[0121] As Figure 6c shown, the third output sub - circuit 703 is connected to the output terminals of multiple fourth switch sub - circuits through the second transistor 602; the third output sub - circuit is connected to the third switch sub - circuit through the tenth transistor 610; the third output sub - circuit is connected to the output terminals of multiple first switch sub - circuits through the fourteenth transistor 614, the fifteenth transistor 615, and the sixteenth transistor 616; the third output sub - circuit is connected to the output terminals of multiple second switch sub - circuits through the fourteenth transistor 614, the fifteenth transistor 615, and the eighth transistor 608.

[0122] In some embodiments, the first output control circuit includes an operational amplifier. The input terminal of the first output control circuit is configured to receive four - way second analog voltage signals output by multiple output sub - circuits. The operational amplifier is configured to perform weighted summation according to the four - way second analog voltage signals to generate an analog gray - scale voltage signal.

[0123] Specifically, the above gamma voltage conversion circuit will be described in detail below with reference to an actual application. Taking enabling a group of first voltage division output terminals as an example, the gray scale values corresponding to this group include a first gray scale value and three second gray scale values. The first gray scale value is the 48th gray scale value, and the second gray scale values include the 49th, 50th, and 51st gray scale values. When the analog gray scale voltage signal output by the gamma voltage conversion circuit corresponds to the 48th gray scale value, the corresponding Gray code is 00100000. The first output circuit outputs the analog voltage corresponding to the 48th gray scale value, the second output circuit outputs the analog voltage corresponding to the 48th gray scale value, and the third output circuit outputs two paths of analog voltages corresponding to the 48th gray scale value. Thus, the first output control circuit generates and outputs the analog gray scale voltage signal corresponding to the 48th gray scale value; when the analog gray scale voltage output by the gamma voltage conversion circuit corresponds to the 49th gray scale value, its corresponding Gray code is 00100001. The first output circuit outputs the analog voltage corresponding to the 48th gray scale value, the second output circuit outputs the analog voltage corresponding to the 52nd gray scale value, and the third output circuit outputs two paths of analog voltages corresponding to the 48th gray scale value. Thus, the first output control circuit generates and outputs the analog gray scale voltage signal corresponding to the 49th gray scale value according to these four paths of analog voltages; when the analog gray scale voltage output by the gamma voltage conversion circuit corresponds to the 51st gray scale value, its corresponding Gray code is 00100010. The first output circuit outputs the analog voltage corresponding to the 48th gray scale value, the second output circuit outputs the analog voltage corresponding to the 52nd gray scale value, and the third output circuit outputs two paths of analog voltages corresponding to the 52nd gray scale value. Thus, the first output control circuit generates and outputs the analog gray scale voltage signal corresponding to the 51st gray scale value according to these four paths of analog voltages; when the analog gray scale voltage output by the gamma voltage conversion circuit corresponds to the 50th gray scale value, its corresponding Gray code is 00100011. The first output circuit outputs the analog voltage corresponding to the 48th gray scale value, the second output circuit outputs the analog voltage corresponding to the 48th gray scale value, and the third output circuit outputs two paths of analog voltages corresponding to the 52nd gray scale value. Thus, the first output control circuit generates and outputs the analog gray scale voltage signal corresponding to the 50th gray scale value according to these four paths of analog voltages.

[0124] Embodiments of the present disclosure provide a gamma voltage conversion circuit, which can be used for gamma voltage conversion by using a coding circuit based on Gray code, etc., improving the response speed, reducing circuit glitches and noise, and making the change of gray-scale display brightness smoother during gray-scale switching one by one, thus solving problems such as display jitter and power supply fluctuation caused by gray-scale switching one by one. Further, since the output reaches the target potential more accurately, the voltages at the distal end and proximal end of the panel are consistent, so the brightness is consistent and the uniformity of the panel is better. On this basis, embodiments of the present disclosure provide a segmented coding type first coding circuit. For low gray scales and high gray scales, such as the 0th to 31st gray scales and the 224th to 255th gray scales as described above, the method of encoding and outputting gray scales one by one is adopted, and the first switching sub-circuit and the second switching sub-circuit are used for encoding and outputting. For the middle part of the gray scales, the third switching sub-circuit and the fourth switching sub-circuit are used for encoding and outputting. The analog voltages output by it correspond to the first gray-scale values of each first voltage-dividing output end, and the first output control circuit is used to generate an analog gray-scale voltage based on multiple analog voltages, realizing that while ensuring the gray-scale accuracy of the output of the gamma voltage conversion circuit, the occupied area is reduced by half.

[0125] Specifically, taking 8-bit digital-to-analog conversion as an example, a traditional switch tree structure digital-to-analog conversion circuit requires 2^9, that is, 512 switch transistors to implement 8-bit digital-to-analog conversion; while the present disclosure realizes 8-bit digital-to-analog conversion based on 6-bit digital-to-analog conversion and a 2-bit interpolation operational amplifier. Based on the above-mentioned switch transistor multiplexing structure, only 297 switch transistors need to be set, and the occupied area can be saved by half.

[0126] Figure 7 FIG. [Specific figure number] is a schematic structural diagram of another gamma voltage conversion circuit provided by an embodiment of the present disclosure. Specifically, this structure is a specific and optional implementation scheme based on the Figure 1 gamma voltage conversion circuit shown.

[0127] As Figure 7 shown, this circuit further includes:

[0128] A second voltage-dividing circuit 10, having multiple sixth input terminals 103 and multiple second voltage-dividing output terminals 104. One sixth input terminal 103 is configured to receive a second gamma voltage signal input by a second gamma channel. The second voltage-dividing circuit is configured to generate multiple third analog voltage signals according to the second gamma voltage signal, and one second voltage-dividing output terminal 104 is configured to output one third analog voltage signal.

[0129] A second coding circuit 30, configured to generate and output multiple fourth analog signal voltages according to one of the Gray code control signal and multiple third analog voltage signals.

[0130] The second output control circuit 40 is configured to generate an analog grayscale voltage signal based on multiple fourth analog voltage signals and output the same.

[0131] In some embodiments, in this circuit, both the first encoding circuit 3 and the second encoding circuit 30 include multiple switching transistors. The switching transistors of the first encoding circuit 3 are one of P-type transistors and N-type transistors, and the switching transistors of the second encoding circuit 30 are the other of P-type transistors and N-type transistors. The control gate signals corresponding to the switching transistors of the first encoding circuit 3 and the control gate signals corresponding to the switching transistors of the second encoding circuit 30 are opposite to each other bit by bit. Specifically, since the signals adopt the form of all positive half voltages, P-type transistors and N-type transistors are used to transmit high voltages and low voltages respectively.

[0132] In some embodiments, the first encoding circuit 3 and the second encoding circuit 30 are connected to the same Gray code control circuit 2, or the Gray code control circuits 2 corresponding to the first encoding circuit 3 and the second encoding circuit 30 are independently provided.

[0133] An embodiment of the present disclosure further provides a display device, which includes: a gamma voltage conversion circuit as described in any of the above embodiments.

[0134] Figure 8 It is a flowchart of a gamma voltage conversion method provided by an embodiment of the present disclosure. Specifically, this method is applied to a gamma voltage conversion circuit as described in any of the above embodiments, as Figure 8 shown, this method includes:

[0135] Step S1: Generate multiple first analog voltage signals based on the first gamma voltage signal input by the first gamma channel.

[0136] Step S2: Generate a corresponding Gray code control signal according to the grayscale value to be displayed.

[0137] Step S3: Generate multiple second analog voltage signals based on the Gray code control signal and one of the multiple first analog voltage signals.

[0138] Step S4: Generate an analog grayscale voltage signal based on the multiple second analog voltage signals and output the same.

[0139] In some embodiments, in step S4, the step of generating an analog grayscale voltage signal based on the multiple second analog voltage signals and outputting the same includes: performing weighted summation on the multiple analog voltages to generate an analog grayscale voltage.

[0140] In some embodiments, the method further includes: generating multiple third analog voltage signals according to a second gamma voltage signal input through a second gamma channel; generating multiple fourth analog voltage signals according to a Gray code control signal and one of the multiple third analog voltage signals; generating and outputting an analog gray-scale voltage signal according to the multiple fourth analog voltage signals.

[0141] Figure 9 This is a flowchart of a specific implementation method for step S3 in the embodiments of the present disclosure. Specifically, as Figure 9 shown, step S3, the step of generating multiple analog voltages according to the first analog voltage signal and its corresponding Gray code control signal, includes:

[0142] Step S301: Control the on / off state of a branch of one switch sub-circuit of itself according to multiple first preset bits of the Gray code control signal, and generate a to-be-output voltage signal according to the first analog voltage signal received by the branch in the on state.

[0143] Step S302: Control the output sub-circuit of itself to be connected to the switch sub-circuit according to multiple second preset bits of the Gray code control signal, and generate and output a second analog voltage signal according to the to-be-output voltage signal.

[0144] The embodiments of the present disclosure provide a gamma voltage conversion method, which is applied to a corresponding gamma voltage conversion circuit. This method can be used for gamma voltage conversion based on Gray code. During the switching process between adjacent gray scales corresponding to the Gray code, at most two bits change, avoiding multi-bit switching and the indeterminate state and intermediate state during this process, improving the response speed, reducing the glitches and noise of the circuit, and making the brightness change of the gray scale display smoother during the switching of each gray scale, thus solving the problems such as display jitter and power supply fluctuation caused by the switching of each gray scale. Further, since the output more accurately reaches the target potential, the voltages at the far end and near end of the panel are the same, so the brightness is the same, and the uniformity of the panel is better.

[0145] Those of ordinary skill in the art will understand that all or some of the steps in the methods disclosed above, and the functional modules / units in the devices, can be implemented as software, firmware, hardware, and their appropriate combinations. In a hardware implementation, the division between the functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, one physical component can have multiple functions, or one function or step can be executed by several physical components in cooperation. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include a computer storage medium (or non-transitory medium) and a communication medium (or transitory medium). As is well known to those of ordinary skill in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data. Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, as is well known to those of ordinary skill in the art, a communication medium typically includes computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and can include any information delivery medium.

[0146] Example embodiments have been disclosed herein, and although specific terms have been used, they are used for and should be construed only as general illustrative meanings and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that, unless otherwise explicitly stated, the features, characteristics, and / or elements described in connection with a particular embodiment can be used alone or in combination with the features, characteristics, and / or elements described in connection with other embodiments. Accordingly, those skilled in the art will understand that various forms and details can be changed without departing from the scope of the present disclosure as set forth by the appended claims.

Claims

1. A gamma voltage conversion circuit, comprising: A first voltage divider circuit has a plurality of first input terminals and a plurality of first voltage divider output terminals; One of the first input terminals is configured to receive a first gamma voltage signal input from a first gamma channel, the first voltage divider circuit is configured to generate a plurality of first analog voltage signals according to the first gamma voltage signal, and one of the first voltage divider output terminals is configured to output one of the first analog voltage signals; Gray code control circuit, used to generate and output a corresponding Gray code control signal according to the grayscale value to be displayed; a first encoding circuit, configured to generate and output four second analog voltage signals according to the Gray code control signal and one of the multiple first analog voltage signals; a first output control circuit, configured to perform weighted summation on the four second analog voltage signals to generate and output an analog grayscale voltage signal; Wherein, the first encoding circuit includes a plurality of switch sub-circuits and a plurality of output sub-circuits; The multiple switch subcircuits include multiple first switch subcircuits, multiple second switch subcircuits, a third switch subcircuit, and multiple fourth switch subcircuits. Each of the first switch subcircuits, each of the second switch subcircuits, each of the third switch subcircuit, and each of the fourth switch subcircuits includes multiple branches. Each branch has a second input terminal and multiple third input terminals. One of the second input terminals is configured to receive one of the first analog voltage signals output by one of the first voltage divider output terminals, and one of the third input terminals is configured to receive a first preset bit of the Gray code control signal. Each branch is configured to control its own on / off state according to the multiple first preset bits of the Gray code control signal, and to generate a voltage signal to be output according to the received first analog voltage signal when in the on state. The multiple output sub-circuits include a first output sub-circuit, a second output sub-circuit, and a third output sub-circuit. Each of the output sub-circuits has four fourth input terminals and multiple fifth input terminals. The four fourth input terminals are respectively configured to receive the voltage signals to be output outputted by the corresponding first switch sub-circuit, the second switch sub-circuit, the third switch sub-circuit, and the fourth switch sub-circuit. One of the fifth input terminals is configured to receive a second preset bit of the Gray code control signal. Each of the output sub-circuits is configured to control itself to be connected to one of the switch sub-circuits according to the multiple second preset bits of the Gray code control signal, and to generate and output the second analog voltage signal according to the received voltage signal to be outputted. The first output sub-circuit and the second output sub-circuit are both configured to output one channel of the second analog voltage signal according to the voltage signal to be output, and the third output sub-circuit is configured to output two identical second analog voltage signals according to the voltage to be output; Among them, the first analog voltage signal and the first voltage divider output terminal correspond to the grayscale value one by one, and the second analog voltage signal corresponds to the grayscale value one by one. m grayscale value, m is a positive integer.

2. The gamma voltage conversion circuit according to claim 1, wherein: The first voltage divider circuit includes a plurality of resistors connected in series, wherein a connection node between any two resistors connected in series is a series node, and one series node corresponds to one first voltage divider output terminal.

3. The gamma voltage conversion circuit according to claim 1, wherein: The Gray code control signal includes a first Gray code signal and a second Gray code signal, wherein each bit of the first Gray code signal and the second Gray code signal are opposite; The first encoding circuit is specifically configured to generate and output the four second analog voltage signals according to the first Gray code signal, the second Gray code signal, and one of the multiple first analog voltage signals.

4. The gamma voltage conversion circuit according to claim 1, wherein: Each of the first switch sub-circuits includes 2n branches, and each of the second switch sub-circuits includes 2n branches, where n is a positive integer; The first voltage divider output terminals are sorted in ascending order according to the corresponding grayscale values, and every n adjacent first voltage divider output terminals form a group; wherein, for the N groups of the first voltage divider output terminals whose corresponding grayscale values are less than or equal to the preset first threshold value, every two adjacent groups of the first voltage divider output terminals are connected to the second input terminals in a first switch sub-circuit, and N is a positive integer; for the M groups of the first voltage divider output terminals whose corresponding grayscale values are greater than or equal to the preset second threshold value, every two adjacent groups of the first voltage divider output terminals are connected to the second input terminals of a second switch sub-circuit, the second threshold value is greater than the first threshold value, and M is a positive integer.

5. The gamma voltage conversion circuit according to claim 4, wherein: The third switch subcircuit includes k branches, and each of the fourth switch subcircuits includes n branches, wherein k=(2 m -N*nM*n) / n, k is a positive integer; For multiple groups of first voltage divider output terminals whose corresponding grayscale values are greater than the first threshold and less than the second threshold, wherein the grayscale values corresponding to each group of first voltage divider output terminals include the smallest first grayscale value and n-1 second grayscale values, the first voltage divider output terminals corresponding to every n adjacent first grayscale values are alternately connected to the n second input terminals of the third switch sub-circuit and each second input terminal of one of the fourth switch sub-circuits.

6. The gamma voltage conversion circuit according to claim 5, wherein: m=8, n=4, the corresponding grayscale values are sorted from level 0 to level 255 in ascending order, and the Gray code control signal is sorted from bit 0 to bit 7 in descending order; the first threshold is equal to the grayscale value of level 31; The second threshold is equal to the 224th grayscale value.

7. The gamma voltage conversion circuit according to claim 6, wherein: The first preset bits corresponding to the first switch sub-circuit and the second switch sub-circuit both include bits 0 to 4, the first preset bits corresponding to the third switch sub-circuit include bits 2 to 7, and the first preset bits corresponding to the fourth switch sub-circuit include bits 3 to 7.

8. The gamma voltage conversion circuit according to claim 7, wherein: The first encoding circuit has a plurality of switching transistors, the switching transistors including: first to eighth transistors, whose control electrodes are respectively used to receive the opposite 0th bit to the opposite 7th bit; ninth to sixteenth transistors, whose control electrodes are respectively used to receive the 0th bit to the 7th bit; Each of the first switch sub-circuit and the second switch sub-circuit includes a first branch to an eighth branch, wherein the first branch includes a first transistor, a second transistor, a third transistor, a twelfth transistor, and a thirteenth transistor connected in sequence, and is configured to receive the first analog voltage signal outputted from the first voltage-dividing output terminal corresponding to the 5+8i level grayscale value; the second branch includes a ninth transistor, a second transistor, a third transistor, a twelfth transistor, and a thirteenth transistor connected in sequence, and is configured to receive the first analog voltage signal outputted from the first voltage-dividing output terminal corresponding to the 4+8i level grayscale value; the third branch includes a first transistor, a tenth transistor, a third transistor, a twelfth transistor, and a thirteenth transistor connected in sequence, and is configured to receive the first analog voltage signal outputted from the first voltage-dividing output terminal corresponding to the 6+8i level grayscale value; the fourth branch includes a ninth transistor, a tenth transistor, a third transistor, a twelfth transistor, and a thirteenth transistor connected in sequence, and is configured to receive the first analog voltage signal outputted from the first voltage-dividing output terminal corresponding to the 7+8i level grayscale value. the first analog voltage signal outputted from the first voltage-divided output terminal; the fifth branch comprises a first transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor connected in sequence, and is configured to receive the first analog voltage signal outputted from the first voltage-divided output terminal corresponding to the 1+8i grayscale value; the sixth branch comprises a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor connected in sequence, and is configured to receive the first analog voltage signal outputted from the first voltage-divided output terminal corresponding to the 0+8i grayscale value; the seventh branch comprises a first transistor, a second transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor connected in sequence, and is configured to receive the first analog voltage signal outputted from the first voltage-divided output terminal corresponding to the 2+8i grayscale value; the eighth branch comprises a ninth transistor, a second transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor connected in sequence, and is configured to receive the first analog voltage signal outputted from the first voltage-divided output terminal corresponding to the 3+8i grayscale value; For the first switch sub-circuit, the value of i is any one of 0, 1, 2, and 3; for the second switch sub-circuit, the value of i is any one of 28, 29, 30, and 31.

9. The gamma voltage conversion circuit according to claim 8, wherein: The first branch to the eighth branch multiplex the twelfth transistor and the thirteenth transistor, the first branch to the fourth branch multiplex the third transistor, the fifth branch to the eighth branch multiplex the eleventh transistor, the first branch and the second branch multiplex a second transistor, the third branch and the fourth branch multiplex a tenth transistor, the fifth branch and the sixth branch multiplex another tenth transistor, and the seventh branch and the eighth branch multiplex another second transistor.

10. The gamma voltage conversion circuit according to claim 8, wherein: One of the fourth switch sub-circuits includes a ninth branch to a twelfth branch, wherein the ninth branch includes a fourth transistor, a thirteenth transistor, a sixth transistor, a fifteenth transistor, and a sixteenth transistor connected in sequence, and is configured to receive the first analog voltage signal outputted by the first voltage divider output terminal corresponding to the first grayscale value of level 60+32j; the tenth branch includes a twelfth transistor, a thirteenth transistor, a sixth transistor, a fifteenth transistor, and a sixteenth transistor connected in sequence, and is configured to receive the first analog voltage signal outputted by the first voltage divider output terminal corresponding to the first grayscale value of level 52+32j. The eleventh branch includes a fourth transistor, a fifth transistor, a sixth transistor, a fifteenth transistor, and a sixteenth transistor connected in sequence, and is configured to receive the first analog voltage signal outputted by the first voltage-divided output terminal corresponding to the first grayscale value of level 44+32j. The twelfth branch includes a twelfth transistor, a fifth transistor, a sixth transistor, a fifteenth transistor, and a sixteenth transistor connected in sequence, and is configured to receive the first analog voltage signal outputted by the first voltage-divided output terminal corresponding to the first grayscale value of level 36+32j. The value of j is any one of 0, 1, 2, 3, 4, and 5. The third switch subcircuit includes a plurality of basic units, one of which includes a thirteenth branch to a sixteenth branch, wherein the thirteenth branch includes a third transistor, a thirteenth transistor, a sixth transistor, a fifteenth transistor, and a sixteenth transistor connected in sequence, and is configured to receive the first analog voltage signal outputted from the first voltage divider output terminal corresponding to the first grayscale value of level 56+32j; the fourteenth branch includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, a sixth transistor, a fifteenth transistor, and a sixteenth transistor connected in sequence, and is configured to receive the first analog voltage signal outputted from the first voltage divider output terminal corresponding to the first grayscale value of level 48+32j; the fifteenth branch includes a third transistor, a fifth transistor, a sixth transistor, a fifteenth transistor, and a sixteenth transistor connected in sequence The six transistors are configured to receive the first analog voltage signal output from the first voltage divider output terminal corresponding to the first grayscale value of level 40+32j; the sixteenth branch includes an eleventh transistor, a twelfth transistor, a fifth transistor, a sixth transistor, a fifteenth transistor and a sixteenth transistor connected in sequence, which are configured to receive the first analog voltage signal output from the first voltage divider output terminal corresponding to the first grayscale value of level 32+32j; for one of the basic units, a fourth transistor is further connected between the eleventh transistor of the fourteenth branch and the fifth transistor of the fifteenth branch; for two adjacent basic units, a fourth transistor is further connected between the eleventh transistor of the sixteenth branch of one of the basic units and the thirteenth transistor of the thirteenth branch of the other basic unit.

11. The gamma voltage conversion circuit according to claim 10, wherein: The ninth branch to the twelfth branch multiplex the sixth transistor, the fifteenth transistor and the sixteenth transistor, the ninth branch and the tenth branch multiplex the thirteenth transistor, and the eleventh branch and the twelfth branch multiplex the fifth transistor; For one basic unit, the thirteenth to sixteenth branches multiplex the sixth transistor, the fifteenth transistor and the sixteenth transistor, the thirteenth branch and the fourteenth branch multiplex the thirteenth transistor, and the fifteenth branch and the sixteenth branch multiplex the fifth transistor.

12. The gamma voltage conversion circuit according to claim 1, wherein: The first output sub-circuit is configured to control itself to be connected to one of the first switching sub-circuit or one of the second switching sub-circuit according to bits 5, 6, and 7 of the Gray code control signal, or to control itself to be connected to the third switching sub-circuit or one of the fourth switching sub-circuit according to bits 2 and 3 of the Gray code control signal; The second output sub-circuit is configured to control itself to be connected to one of the first switching sub-circuit or one of the second switching sub-circuit according to bits 5, 6, and 7 of the Gray code control signal, or to control itself to be connected to the third switching sub-circuit or one of the fourth switching sub-circuit according to bits 0 and 1 of the Gray code control signal; The third output sub-circuit is configured to control itself to be connected to one of the first switching sub-circuit or one of the second switching sub-circuit according to the 5th, 6th and 7th bits of the Gray code control signal, or to control itself to be connected to the third switching sub-circuit or one of the fourth switching sub-circuit according to the 1st bit of the Gray code control signal.

13. The gamma voltage conversion circuit according to claim 12, wherein: Each of the output sub-circuits has a plurality of switching transistors, the switching transistors including: first to eighth transistors, whose control electrodes are respectively used to receive the opposite 0th bit to the opposite 7th bit; ninth to sixteenth transistors, whose control electrodes are respectively used to receive the 0th bit to the 7th bit; The first output subcircuit is connected to the output terminals of the plurality of fourth switch subcircuits through the third transistor and the twelfth transistor, and is connected to the output terminals of the plurality of fourth switch subcircuits through the fourth transistor and the eleventh transistor; the first output subcircuit is connected to the third switch subcircuit through the eleventh transistor and the twelfth transistor, and is connected to the third switch subcircuit through the fourth transistor and the third transistor; the first output subcircuit is connected to the output terminals of the plurality of first switch subcircuits through the fourteenth transistor, the fifteenth transistor, and the sixteenth transistor; the first output subcircuit is connected to the output terminals of the plurality of second switch subcircuits through the fourteenth transistor, the fifteenth transistor, and the eighth transistor; The second output subcircuit is connected to the output terminals of the plurality of fourth switch subcircuits through the second transistor and the ninth transistor, and is connected to the output terminals of the plurality of fourth switch subcircuits through the first transistor and the tenth transistor; the second output subcircuit is connected to the third switch subcircuit through the ninth transistor and the tenth transistor, and is connected to the third switch subcircuit through the first transistor and the second transistor; the second output subcircuit is connected to the output terminals of the plurality of first switch subcircuits through the fourteenth transistor, the fifteenth transistor, and the sixteenth transistor; the second output subcircuit is connected to the output terminals of the plurality of second switch subcircuits through the fourteenth transistor, the fifteenth transistor, and the eighth transistor; The third output sub-circuit is connected to the output ends of the multiple fourth switch sub-circuits through the second transistor; the third output sub-circuit is connected to the third switch sub-circuit through the tenth transistor; the third output sub-circuit is connected to the output ends of the multiple first switch sub-circuits through the fourteenth transistor, the fifteenth transistor and the sixteenth transistor; the third output sub-circuit is connected to the output ends of the multiple second switch sub-circuits through the fourteenth transistor, the fifteenth transistor and the eighth transistor.

14. The gamma voltage conversion circuit according to claim 1, wherein: The first output control circuit includes an operational amplifier, and the input end of the first output control circuit is configured to receive the four second analog voltage signals output by the multiple output sub-circuits. The operational amplifier is configured to perform weighted summation based on the four second analog voltage signals to generate the analog grayscale voltage signal.

15. The gamma voltage conversion circuit according to any one of claims 1 to 14, wherein: Also includes: a second voltage divider circuit having a plurality of sixth input terminals and a plurality of second voltage divider output terminals, wherein one of the sixth input terminals is configured to receive a second gamma voltage signal inputted by a second gamma channel, the second voltage divider circuit is configured to generate a plurality of third analog voltage signals according to the second gamma voltage signal, and one of the second voltage divider output terminals is configured to output one third analog voltage signal; a second encoding circuit, configured to generate and output a plurality of fourth analog voltage signals according to the Gray code control signal and one of the plurality of third analog voltage signals; The second output control circuit is used to generate and output analog grayscale voltage signals according to the multiple fourth analog voltage signals.

16. The gamma voltage conversion circuit according to claim 15, wherein: Also includes: The first encoding circuit and the second encoding circuit both include multiple switching transistors. The switching transistors in the first encoding circuit are one of a P-type transistor and an N-type transistor, and the switching transistors in the second encoding circuit are the other of a P-type transistor and an N-type transistor. The control electrode signals corresponding to the switching transistors in the first encoding circuit and the control electrode signals corresponding to the switching transistors in the second encoding circuit are opposite in every bit.

17. A display device comprising: Gamma voltage conversion circuit The gamma voltage conversion circuit adopts the gamma voltage conversion circuit according to any one of claims 1 to 16.

18. A gamma voltage conversion method, applied to the gamma voltage conversion circuit according to any one of claims 1 to 16, the method comprising: Generate multiple first analog voltage signals according to the first gamma voltage signal input from the first gamma channel; generating a corresponding Gray code control signal according to the grayscale value to be displayed; generating a plurality of second analog voltage signals according to the Gray code control signal and one of the plurality of first analog voltage signals; An analog grayscale voltage signal is generated according to the multiple second analog voltage signals and outputted.

19. The gamma voltage conversion method according to claim 18, wherein: The generating of multiple second analog voltage signals according to the Gray code control signal and one of the multiple first analog voltage signals includes: controlling the on / off state of a branch of a switching sub-circuit thereof according to a plurality of first preset bits of the Gray code control signal, and generating a voltage signal to be output according to the first analog voltage signal received by the branch in the on state; The output sub-circuit thereof is controlled to be connected to the switch sub-circuit according to a plurality of second preset bits of the Gray code control signal, and the second analog voltage signal is generated and output according to the voltage signal to be output.

20. The gamma voltage conversion method according to claim 18, wherein: The step of generating and outputting an analog grayscale voltage signal according to the multiple second analog voltage signals includes: The analog grayscale voltage signal is generated by performing weighted summation on the multiple second analog voltage signals.

21. The gamma voltage conversion method according to claim 18, wherein: Also includes: generating a plurality of third analog voltage signals according to the second gamma voltage signal inputted from the second gamma channel; generating a plurality of fourth analog voltage signals according to the Gray code control signal and one of the plurality of third analog voltage signals; An analog grayscale voltage signal is generated according to the multiple fourth analog voltage signals and outputted.

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