A charge sharing circuit for a display panel

Abstract

The present application relates to the field of display panel, disclose a kind of charge sharing circuit for display panel, additional charge sharing circuit is increased in far away from source chip far end or between each row of pixel unit, the charge sharing unit of charge sharing circuit is not connected with storage capacitor, liquid crystal process, charge sharing unit is directly connected as switch display panel common voltage VCOM, and TP1 signal is converted by potential conversion circuit, the low voltage of TP1 signal is pulled to the range of voltage VGL to voltage VGH, so as to control the switch of charge sharing.Electric charge sharing circuit can be used as remote electric charge sharing switch to achieve the goal of fast charging.In addition, the present application also proposes a scheme for fast electric charge sharing on large electrode plate, which can greatly improve the charging speed.

Description

Technical Field

[0001] The present invention relates to the field of display panels, and in particular to a charge sharing circuit for a display panel. Background Art

[0002] Panel display resolutions are increasing, from Full HD to 4K and even higher, 8K. With higher resolutions, the panel's charging time becomes shorter and the parasitic load on the panel becomes heavier. Insufficient charging capacity and reduced power consumption have become urgent issues to address.

[0003] Liquid crystal displays have been developed for decades. Since liquid crystals have positive and negative charging characteristics, charge redistribution technology is also widely used in liquid crystal displays to reduce power consumption and shorten charging time.

[0004] In order to further meet the charging requirements, various charging methods such as over-drive have been proposed, but these charging methods also have problems.

[0005] Figure 8 This is a more common display driver circuit. Generally, it is divided into a positive polarity voltage driver amplifier (AMPH) and a negative polarity driver amplifier (AMPL). When the polarity is switched, the positive and negative polarity panel loads are short-circuited to share charge (charge sharing), accelerating the charging speed of the next line and reducing unnecessary power consumption.

[0006] Figure 9 For common charging waveforms; such as Figure 10 As shown, when the LCD is overloaded, the remote end far from the driver chip may be insufficiently charged; TP1 is a control signal for controlling the display panel to share and charge the charge.

[0007] like Figure 11 As shown, at the near end closer to the source chip, the voltage quickly reaches the midpoint due to its proximity to the charge neutralization switch on the source chip. However, at the far end, it takes longer to approach the average potential of the positive and negative polarities. In addition, charging is slow, so there will be a difference in pixel voltage between the far and near ends. Summary of the Invention

[0008] In order to solve the above technical problems, the present invention provides a charge sharing circuit for a display panel.

[0009] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0010] A charge sharing circuit for a display panel includes a pixel array region and a source chip located at one end of the pixel array region. The pixel array region includes pixel units arranged in rows and columns, with each row of pixel units connected by a gate line and each column of pixel units connected by a source line. The end of the pixel array region away from the source chip is a distal end.

[0011] The charge sharing circuit includes a potential conversion circuit and N charge sharing units; N is the number of columns of pixel units in the pixel array area;

[0012] The charge sharing unit includes a MOS transistor SW; the drain of the MOS transistor SW is connected to the common voltage VCOM of the display panel, the source is connected to the source line shared by the column where the MOS transistor SW is located, and the gate is connected to the output end of the potential conversion circuit;

[0013] The potential conversion circuit is used to control the switch of the charge sharing unit;

[0014] The charge sharing circuit is located at the far end of the pixel array area, or between any two rows of pixel units in the pixel array area; that is, the connection point between each charge sharing unit and the source line in the charge sharing circuit is located at the far end of the pixel array area, or between any two rows of pixel units in the pixel array area.

[0015] Furthermore, the MOS transistor SW is an NMOS.

[0016] Furthermore, the potential conversion circuit includes a first potential conversion circuit and a second potential conversion circuit;

[0017] The potential conversion circuit 1 is a double-stage inverter circuit for converting the TP1 signal into a supply voltage VIN;

[0018] The TP1 signal is a control signal for controlling the display panel to perform charge sharing and charging;

[0019] The second potential conversion circuit includes: MOS tubes N3, N4, N5, N6, P3, P4, P5, and P6; MOS tubes N3, N4, N5, and N6 are NMOS; MOS tubes P3, P4, P5, and P6 are PMOS;

[0020] The gate of MOS transistor N3 is connected to the power supply voltage VIN, the drain of MOS transistor N3 is connected to the voltage VOUT1B, the source of MOS transistor P3, and the gate of MOS transistor P4, and the source of MOS transistor N3 is connected to the source of MOS transistor N4; the drain of MOS transistor P3 is connected to the drain of MOS transistor P4, and the gate of MOS transistor P3 is connected to the drain of MOS transistor N4; the source of MOS transistor P4 is connected to the voltage VOUT1 and the drain of MOS transistor N4; the gate of MOS transistor N4 outputs the voltage VINB;

[0021] The drain of MOS transistor N5 is connected to the source of MOS transistor P5 and the gate of MOS transistor N6. The gate of MOS transistor N5 is connected to the source of MOS transistor P6, voltage VCTRL, and the drain of MOS transistor N6. The source of MOS transistor N5 is connected to the source of MOS transistor N6. The gate of MOS transistor P5 is connected to voltage VOUT1. The drain of MOS transistor P5 is connected to the drain of MOS transistor P6. The gate of MOS transistor P6 is connected to voltage VOUT1B.

[0022] The voltage VCTRL is the output of the potential conversion circuit and is connected to the gate of the MOS transistor SW in the charge sharing unit;

[0023] The voltage VCTRL is between the display panel turn-on voltage VGH and the display panel turn-off voltage VGL.

[0024] Furthermore, the display panel common voltage VCOM is provided by a whole electrode plate or multiple electrode plates.

[0025] Compared with the prior art, the beneficial technical effects of the present invention are:

[0026] An additional charge sharing circuit is added at the far end of the source chip or between pixel units in each row. The charge sharing unit of the charge sharing circuit is not connected to the storage capacitor C ST 、LCD Process C LC The charge sharing unit is connected directly to the display panel common voltage VCOM as a switch, and the TP1 signal is pulled through a potential conversion circuit to a range from VGL to VGH, thereby controlling the charge sharing switch. The charge sharing circuit can be used as a remote charge sharing switch to achieve the goal of fast charging.

[0027] In addition, the present invention also proposes a solution for rapid charge sharing on the large electrode plate, which will greatly increase the charging speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Schematic diagram of the structure of the charge sharing circuit of the present invention;

[0029] Figure 2 Schematic diagram of the structure of the charge sharing circuit of the present invention;

[0030] Figure 3 Schematic diagram of the structure of the charge sharing circuit of the present invention;

[0031] Figure 4 Schematic diagram of the structure of the potential conversion circuit in Example 1;

[0032] Figure 5 Schematic diagram of the structure of the potential conversion circuit in Example 2;

[0033] Figure 6 Schematic diagram of the structure of the potential conversion circuit in Example 3;

[0034] Figure 7 Schematic diagram of the structure of the potential conversion circuit in Example 4;

[0035] Figure 8 A schematic diagram of charge sharing in a display driving circuit commonly used in the prior art;

[0036] Figure 9 This is a charging waveform diagram of a common display driving circuit in the prior art;

[0037] Figure 10 A schematic diagram of insufficient charging caused by charge sharing in the prior art;

[0038] Figure 11 FIG. 1 is a schematic diagram showing a difference in voltage between pixel units at the near end and the far end of a display driving circuit in the prior art. DETAILED DESCRIPTION

[0039] A preferred embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

[0040] Example 1

[0041] In the present invention, TP1 is the control signal for controlling the display panel to perform charge sharing and charging. The central control board, source chip, and gate chip are the main chips for controlling the display panel. Among them, the central control board (Timing Controller Chip, TCON) is used to control the timing of the source chip (Source IC, S-IC) and gate chip (Gate IC, G-IC) of the display panel.

[0042] like Figure 1 As shown, each source chip is connected to a column of pixel units through a source line; each gate chip is connected to a row of pixel units through a gate line.

[0043] like Figure 1 As shown, in this embodiment, the charge sharing unit includes a MOS transistor SW; the drain of the MOS transistor SW is connected to the common voltage VCOM of the display panel, the source is connected to the source line shared by the column where the MOS transistor SW is located, and the gate is connected to the output end of the potential conversion circuit (Level Shifter Circuit).

[0044] The dual-stage inverter circuit is a common circuit for generating a reverse signal, and the MOS tube used therein has a minimum channel width and a minimum channel length.

[0045] The difference between the charge sharing unit and the pixel unit is that the charge sharing unit is not connected to the storage capacitor C ST 、LCD Process C LC , the charge sharing unit is directly connected to the display panel common voltage VCOM as a switch; therefore, the drain of the MOS tube SW in the pixel unit is first connected to the parallel storage capacitor C ST 、LCD Process C LC connected, and then connected to the display panel common voltage VCOM.

[0046] like Figure 2 and Figure 3 As shown in the figure, in large-size LCD panels, the display panel common voltage VCOM is provided by a single large electrode plate with very low resistance. Sharing charge through the display panel common voltage VCOM of the large electrode plate can significantly improve charge sharing efficiency. In small-size LCD panels, although the display panel common voltage VCOM is not provided by a single large electrode plate, its resistance is also very low, which can also improve charge sharing efficiency and enhance charging effects.

[0047] In the drawings of the present invention, DVDD represents a digital voltage, VSSD represents a digital ground, VSSA represents an analog negative operating voltage, HAVDD represents a half-value analog voltage, VDDA represents an analog voltage, R represents a resistor, and C represents a capacitor; OP AMP represents an operational amplifier, including a positive polarity voltage driver amplifier (AMPH) and a negative polarity driver amplifier (AMPL).

[0048] like Figure 4 As shown, in the first embodiment, the TP1 signal is transmitted from the source chip S-IC to the gate chip G-IC, and the potential conversion circuit is built into the gate chip, and the low voltage of the TP1 signal is pulled to between the voltage VGL and the voltage VGH through the potential conversion circuit.

[0049] Example 2

[0050] like Figure 5 As shown, the difference between Example 2 and Example 1 is that the TP1 signal is transmitted from the central control board TCON to the gate chip G-IC, and the potential conversion circuit is built into the gate chip, and the low voltage of the TP1 signal is pulled to between the voltage VGL and the voltage VGH through the potential conversion circuit.

[0051] Example 3

[0052] like Figure 6 As shown, the only difference between Example 3 and Example 1 is that the TP1 signal is transmitted from the source chip S-IC to the potential conversion circuit. The potential conversion circuit is an independent circuit and is not built into the gate chip. The low voltage of the TP1 signal is pulled to between the voltage VGL and the voltage VGH through the potential conversion circuit.

[0053] Example 4

[0054] like Figure 7 As shown, the only difference between Example 4 and Example 1 is that the TP1 signal is transmitted from the central control board TCON to the potential conversion circuit. The potential conversion circuit is an independent circuit and is not built into the gate chip. The low voltage of the TP1 signal is pulled to between the voltage VGL and the voltage VGH through the potential conversion circuit.

[0055] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. It is intended that all variations within the meaning and range of equivalents of the claims be embraced herein, and any reference signs in the claims should not be construed as limiting the claims to which they relate.

[0056] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A charge sharing circuit for a display panel, the display panel comprising a pixel array region and a source chip located at one end of the pixel array region, the pixel array region comprising pixel units arranged in rows and columns, each row of pixel units being connected by a gate line, and each column of pixel units being connected by a source line; the end of the pixel array region remote from the source chip being a distal end; Its characteristics are: The charge sharing circuit includes a potential conversion circuit and N charge sharing units; N is the number of columns of pixel units in the pixel array area; The charge sharing unit includes a MOS transistor SW; the drain of the MOS transistor SW is connected to the common voltage VCOM of the display panel, the source is connected to the source line shared by the column where the MOS transistor SW is located, and the gate is connected to the output end of the potential conversion circuit; The potential conversion circuit is used to control the switch of the charge sharing unit; The charge sharing circuit is located at a far end of the pixel array area, or between any two rows of pixel units in the pixel array area; The potential conversion circuit includes a potential conversion circuit 1 and a potential conversion circuit 2; The potential conversion circuit 1 is a double-stage inverter circuit for converting the TP1 signal into a supply voltage VIN; The TP1 signal is a control signal for controlling the display panel to perform charge sharing and charging; The second potential conversion circuit includes: MOS tubes N3, N4, N5, N6, P3, P4, P5, and P6; MOS tubes N3, N4, N5, and N6 are NMOS; MOS tubes P3, P4, P5, and P6 are PMOS; The gate of MOS transistor N3 is connected to the power supply voltage VIN, the drain of MOS transistor N3 is connected to the voltage VOUT1B, the source of MOS transistor P3, and the gate of MOS transistor P4, and the source of MOS transistor N3 is connected to the source of MOS transistor N4; the drain of MOS transistor P3 is connected to the drain of MOS transistor P4, and the gate of MOS transistor P3 is connected to the drain of MOS transistor N4; the source of MOS transistor P4 is connected to the voltage VOUT1 and the drain of MOS transistor N4; the gate of MOS transistor N4 outputs the voltage VINB; The drain of MOS transistor N5 is connected to the source of MOS transistor P5 and the gate of MOS transistor N6. The gate of MOS transistor N5 is connected to the source of MOS transistor P6, voltage VCTRL, and the drain of MOS transistor N6. The source of MOS transistor N5 is connected to the source of MOS transistor N6. The gate of MOS transistor P5 is connected to voltage VOUT1. The drain of MOS transistor P5 is connected to the drain of MOS transistor P6. The gate of MOS transistor P6 is connected to voltage VOUT1B. The voltage VCTRL is the output of the potential conversion circuit and is connected to the gate of the MOS transistor SW in the charge sharing unit; The voltage VCTRL is between the display panel turn-on voltage VGH and the display panel turn-off voltage VGL.

2. The charge sharing circuit for a display panel according to claim 1, wherein: The MOS tube SW is an NMOS.

3. The charge sharing circuit for a display panel according to claim 1, wherein: The display panel common voltage VCOM is provided by a whole electrode plate or multiple electrode plates.

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