Memory and sense amplifier device therefor

Abstract

The present application provides a memory and a sensing amplifier device thereof. The sensing amplifier device includes a bit line bias adjuster and a sensing amplifier circuit. The bit line bias adjuster receives a supply voltage as an operating voltage. The bit line bias adjuster includes a first amplifier, a first transistor, and a first current source. The first amplifier generates an adjusted reference bit line voltage based on the supply voltage according to a reference bit line voltage and a feedback voltage. The first transistor receives the adjusted reference bit line voltage and generates the feedback voltage. The sensing amplifier circuit receives the supply voltage as an operating voltage to generate a sensing result according to the adjusted reference bit line voltage.

Description

TECHNICAL FIELD

[0001] The present application relates to a memory and a sensing amplifier device thereof, and more particularly to a memory and a sensing amplifier device thereof capable of operating normally under low power supply voltage. BACKGROUND

[0002] In low power supply applications of electronic devices, extremely low power consumption is an important feature to effectively prolong the use time of a battery. In integrated circuits, most of the power consumption occurs in the voltage conversion action of a voltage pump circuit. Therefore, how to effectively reduce the use amount of the voltage pump circuit is an important key to reduce power consumption.

[0003] In the read action of a conventional memory, in order to effectively perform the adjustment action of the reference bit line voltage, the bit line adjuster in the sensing amplifier device will have a condition of insufficient high voltage value of the power supply voltage under the working condition of low power supply voltage. Therefore, in the conventional technology, a charge pump circuit is usually used to increase the voltage value of the power supply voltage in the read action, so that the bit line adjuster can maintain normal action. However, the voltage conversion action performed by the charge pump circuit causes excessive power consumption.

[0004] SUMMARY

[0005] The present application provides a memory and a sensing amplifier device thereof. The sensing amplifier device can operate normally under low power supply voltage.

[0006] The sensing amplifier device of the present application comprises a bit line bias adjuster and a sensing amplifier circuit. The bit line bias adjuster receives a power supply voltage as an operating voltage. The bit line bias adjuster comprises a first amplifier, a first transistor and a first current source. The first amplifier receives a reference bit line voltage and a feedback voltage, and generates an adjusted reference bit line voltage based on the power supply voltage according to the reference bit line voltage and the feedback voltage. The first transistor has a first end receiving the power supply voltage. The second end of the first transistor generates the feedback voltage. The control end of the first transistor receives the adjusted reference bit line voltage. The first current source is coupled between the second end of the first transistor and a reference ground end. The sensing amplifier circuit receives the power supply voltage as an operating voltage, and generates a sensing result according to the adjusted reference bit line voltage.

[0007] The memory of the present application comprises a memory cell array and the sensing amplifier device as described above. The sensing amplifier device is coupled to the memory cell array, and is used to sense the memory cell current of a selected memory cell in the memory cell array to generate a sensing result.

[0008] Based on the above, the sensing amplification device of the present application, by setting the first transistor with low threshold voltage in the bit line bias adjuster, so that the bit line bias adjuster can generate effective adjusted reference bit line voltage based on the power supply voltage which is not boosted, and the sensing amplification circuit can generate correct sensing result according to the adjusted reference bit line voltage. In this way, the sensing amplification device can operate based on low power supply voltage, achieving the requirement of saving power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 A schematic diagram of a sensing amplification device of an embodiment of the present application is shown.

[0010] Figure 2 A schematic diagram of a sensing amplification device of another embodiment of the present application is shown.

[0011] Figure 3 A schematic diagram of another implementation of a sensing amplification circuit in a sensing amplification device of an embodiment of the present application is shown.

[0012] Figure 4 A schematic diagram of a partial cross-sectional structure of a sensing amplification circuit of an embodiment of the present application is shown.

[0013] Figure 5 A schematic diagram of a sensing amplification device of another embodiment of the present application is shown.

[0014] Figure 6 A schematic diagram of an implementation of a memory of an embodiment of the present application is shown.

[0015] REFERENCE NUMERALS

[0016] 100, 200, 500, 630: sensing amplification device

[0017] 110, 210, 510: bit line bias adjuster

[0018] 120, 220, 300, 520: sensing amplification circuit

[0019] 121, 122, 221, 222, 321, 322: current-voltage converter

[0020] 411, 412, 413, 414: doped region

[0021] 600: memory

[0022] 610: memory cell array

[0023] 620: multiplexer

[0024] CME: common end

[0025] DE1, DE2: differential end

[0026] G1, G2: gate structure

[0027] HVPW: well region

[0028] IREF1, ICELL, IREF2, IBIAS: current source

[0029] MNR, MNO~MN3, MT0, MT1, MPA, MPB, MNA, MNB, MT0A, MT1A: transistor

[0030] OP1, OP2, 511: amplifier

[0031] OX1, OX2: oxide layer

[0032] R0, R1: resistance

[0033] SR: sensing result

[0034] VB1, VBH: bias voltage

[0035] VBL: reference bit line voltage

[0036] VBL': adjusted reference bit line voltage

[0037] VDD: power supply voltage

[0038] VFB: feedback voltage

[0039] VS1: selection voltage

[0040] VSS: reference ground terminal DETAILED DESCRIPTION

[0041] Please refer to Figure 1 , Figure 1A schematic diagram of a sensing amplifier device is shown. The sensing amplifier device 100 includes a bit line bias adjuster 110 and a sensing amplifier circuit 120. The bit line bias adjuster 110 receives a supply voltage VDD as an operating voltage. The bit line bias adjuster 110 includes an amplifier OP1, a transistor MNR, and a current source IREF1. The amplifier OP1 receives a reference bit line voltage VBL and a feedback voltage VFB. The amplifier OP1 receives the supply voltage VDD as an operating voltage. The amplifier OP1 generates an adjusted reference bit line voltage VBL' based on the supply voltage VDD according to the reference bit line voltage VBL and the feedback voltage VFB. In detail, the amplifier OP1 can have a positive input terminal to receive the reference bit line voltage VBL and a negative input terminal to receive the feedback voltage VFB. The transistor MNR has a first terminal to receive the supply voltage VDD, a second terminal to generate the feedback voltage VFB, and a control terminal to receive the adjusted reference bit line voltage VBL', wherein the threshold voltage of the transistor MNR is less than the threshold voltage of a general transistor (equal to a reference value), for example, the transistor MNR can be a native transistor. The current source IREF1 is coupled between the second terminal of the transistor MNR and a reference ground terminal VSS.

[0042] In addition, the sensing amplifier circuit 120 also receives the supply voltage VDD as an operating voltage to generate a sensing result SR according to the adjusted reference bit line voltage VBL'. In this embodiment, the sensing amplifier circuit 120 includes current-voltage converters 121, 122, an amplifier OP2, transistors MN0-MN3, and current sources ICELL, IREF2. One terminal of the current-voltage converter 121 receives the supply voltage VDD, and the other terminal of the current-voltage converter 121 is coupled to a first terminal of the transistor MN0. One terminal of the current-voltage converter 122 receives the supply voltage VDD, and the other terminal of the current-voltage converter 122 is coupled to a first terminal of the transistor MN1. The transistor MN0, the transistor MN2, and the current source ICELL are sequentially connected between the current-voltage converter 121 and the reference ground terminal VSS. In which, a control terminal of the transistor MN0 receives the adjusted reference bit line voltage VBL', and the transistor MN2 is a selection switch and is turned on according to a selection voltage VS1. In addition, the transistor MN1, the transistor MN3, and the current source IREF2 are sequentially connected between the current-voltage converter 122 and the reference ground terminal VSS. In which, a control terminal of the transistor MN1 receives the adjusted reference bit line voltage VBL', and the transistor MN3 is a selection switch and is turned on according to the selection voltage VS1. In this embodiment, the current sources ICELL and IREF2 provide a storage cell current and a reference current, respectively.

[0043] The current-voltage converters 121 and 122 can be respectively constructed by transistors MT0 and MT1. The first end of the transistor MT0 receives the power supply voltage VDD, the second end of the transistor MT0 is coupled to the first end of the transistor MN0, and the control end of the transistor MT0 receives the bias voltage VB1. The first end of the transistor MT1 receives the power supply voltage VDD, the second end of the transistor MT1 is coupled to the first end of the transistor MN1, and the control end of the transistor MT1 receives the bias voltage VB1. In the embodiment, the transistors MT0 and MT1 can all work in the linear region.

[0044] In the embodiment, when the transistors MN2 and MN3 are turned on according to the selection voltage VS1 (at this time, the selection voltage VS1 can be equal to the power supply voltage VDD), the current-voltage converters 121 and 122 respectively generate the first voltage and the second voltage according to the storage unit current and the reference current. The first voltage and the second voltage are respectively provided to the positive input end and the negative input end of the amplifier OP2, and the amplifier OP2 generates the sensing result SR according to the comparison of the first voltage and the second voltage.

[0045] It is worth noting that the threshold voltages of the transistors MN0 and MN1 in the embodiment can be less than the threshold voltage of a general transistor (equal to a reference value). For example, the transistors MNR, MNO and MN1 can all be original transistors, and have a relatively low threshold voltage Vth relative to other transistors. In this way, the adjusted reference bit line voltage VBL' can be equal to the reference bit line voltage VBL+Vth. Therefore, in the embodiment, the sensing amplification device 100 can work under the power supply voltage VDD with a low voltage value, and does not need to increase the voltage value of the power supply voltage VDD by additionally setting a charge pump circuit, so that the circuit cost and power consumption can be effectively reduced. That is, the power supply voltage VDD in the embodiment can be directly provided by a power supply that is not a charge pump circuit.

[0046] The following please refer to Figure 2 , Figure 2A schematic diagram of a sensing amplifier device is shown. The sensing amplifier device 200 includes a bit line bias adjuster 210 and a sensing amplifier circuit 220. The bit line bias adjuster 210 includes an amplifier formed by transistors MPA, MPB, MNA, MNB and a current source IBIAS, a transistor MNR and a current source IREF1. In detail, the transistors MNA, MNB form a differential pair and the transistors MPA, MPB form an active load. The control terminals of the transistors MNA, MNB receive a reference bit line voltage VBL and a feedback voltage VFB respectively and generate a first current and a second current according to the reference bit line voltage VBL and the feedback voltage VFB respectively. The active load formed by the transistors MPA, MPB is coupled to the differential ends DE1, DE2 of the differential pair, wherein the active load generates an adjusted reference bit line voltage VBL' on the differential end DE2 according to the second current. The current source IBIAS is coupled to the common end CME of the differential pair. The current source IBIAS is used to provide a common current, wherein the sum of the first current and the second current is equal to the common current provided by the current source IBIAS.

[0047] In this embodiment, the sensing amplifier circuit 220 includes current-voltage converters 221, 222, an amplifier OP2, transistors MNO-MN3 and current sources ICELL, IREF2. Among them, the current-voltage converters 221, 222 are resistors RO and R1 respectively. Figure 1 In this embodiment, the current-voltage converters 221, 222 are resistors RO and R1 respectively, which are different from the embodiments. The resistors RO and R1 can be formed by any material that can be used to form resistors in an integrated circuit, such as polysilicon, N-type or P-type doped regions, etc., without any specific limitation.

[0048] It is worth mentioning that in this embodiment, the transistors MPA, MPB, MNA, MNB and the transistor MNR included in the bit line bias adjuster 210 all work in the saturation region, and can reduce the voltage difference between the two ends of each of the transistors MPA, MPB, MNA, MNB, and reduce the voltage value required by the power supply voltage VDD. For example, the coupling end point of the transistors MN2 and MN0 is equal to 0.7 volts, the turn-on voltage Vth of the transistor MN0 is equal to 0.2 volts, and the voltage difference between the first end and the second end of the transistor MPB is equal to 0.1 volts, the power supply voltage VDD can be slightly greater than 1 volt to make the bit line bias adjuster 210 work normally. Moreover, the amplifier in the bit line bias adjuster 210 can also be constructed by different circuits, but the amplifier circuit is well known to those skilled in the art, without any specific limitation. For example, the amplifier in the bit line bias adjuster 210 can also be constructed by a complementary type of the circuit formed by the transistors MPA, MPB, MNA, MNB and the current source IBIAS. Figure 2 In this embodiment, the transistors MPA, MPB, MNA, MNB and the current source IBIAS form a complementary type of the circuit.

[0049] The sensing amplifier circuit 220 is similar to the sensing amplifier circuit 120 in the embodiment, and thus is not described in detail. Figure 1 The sensing amplifier circuit 120 in the embodiment is similar to the sensing amplifier circuit 220, and thus is not described in detail.

[0050] The sensing amplifier circuit 300 in the sensing amplifier device of the embodiment of the present application is shown in the following. Figure 3 , Figure 3 The sensing amplifier circuit 300 in the sensing amplifier device of the embodiment of the present application is shown in the following. Figure 2 The difference between the sensing amplifier circuit 220 and the sensing amplifier circuit 300 is that the current-voltage converters 321 and 322 in the embodiment are respectively constructed by the transistors MTOA and MT1A. The voltage tolerance of the transistors MTOA and MT1A is higher than that of the transistors MT0 and MT1 in the sensing amplifier circuit 220. In addition, the transistors MTOA and MT1A in the embodiment are controlled by the bias voltage VBH. The bias voltage VBH received by the transistors MTOA and MT1A can be greater than the bias voltage VB1 received by the transistors MT0 and MT1.

[0051] It is worth mentioning that in the embodiment, the transistors MTOA and MT1A and the transistors MN0 and MN1 can be disposed in the same well region. Please refer to the following Figure 4 , Figure 4 The partial cross-sectional structure of the sensing amplifier circuit in the embodiment of the present application is shown in the following. Figure 4 In the embodiment, the transistors MN0 and MTOA are disposed in the well region HVPW. Taking the well region HVPW as a P-type well region as an example, the well region HVPW can be provided with the doped regions 411, 412, 413 and 414. The gate structure G1 and the oxide layer OX1 are respectively covered between the doped regions 411 and 412, and form the transistor MN0. The gate structure G2 and the oxide layer OX2 are respectively covered between the doped regions 413 and 414, and form the transistor MTOA. The doped region 411 can be the source (or the drain) of the transistor MN0, and the doped region 412 can be the drain (or the source) of the transistor MN0. The doped region 413 can be the source (or the drain) of the transistor MTOA, and the doped region 414 can be the drain (or the source) of the transistor MTOA.

[0052] In the embodiment, the thickness of the oxide layer OX2 can be greater than that of the oxide layer OX1. In the embodiment of the present application, by disposing the transistors MTOA and MT1A and the transistors MN0 and MN1 in the same well region, the area required by the circuit layout can be effectively reduced.

[0053] The sensing amplifier circuit 300 in the sensing amplifier device of the embodiment of the present application is shown in the following. Figure 5 , Figure 5A schematic diagram of a sensing amplification device is shown. The sensing amplification device 500 includes a bit line bias adjuster 510 and a sensing amplification circuit 520. In this embodiment, the circuit architecture of the sensing amplification circuit 520 is the same as that of the sensing amplification circuit 220 in Figure 2 , and thus is not described again. The bit line bias adjuster 510 in this embodiment includes an amplifier 511, a transistor MNR, and a current source IREF1. The amplifier 511 includes transistors MNA and MNB. The first end of the transistor MNA receives a power supply voltage VDD, the control end of the transistor MNA receives a bias voltage VBIAS, and the second end of the transistor MNA is coupled to the first end of the transistor MNB and generates an adjusted reference bit line voltage VBL’. The second end of the transistor MNB is coupled to a reference ground voltage VSS, and the control end of the transistor MNB receives a feedback voltage. In this embodiment, the bias voltage VBIAS is related to the reference bit line voltage.

[0054] The adjusted reference bit line voltage VBL’ is provided to the control end of the transistor MNR. The first end of the transistor MNR receives the power supply voltage VDD, and the current source IREF1 is connected in series between the second end of the transistor MNR and the reference ground voltage VSS.

[0055] In this embodiment, the transistor MNR can be a native transistor, in which the threshold voltage of the transistor MNR can be lower than the threshold voltages of the transistors MNA and MNB.

[0056] Please refer to Figure 6 , Figure 6 A schematic diagram of an embodiment of a memory is shown. The memory 600 includes a memory cell array 610, a multiplexer 620, and a sensing amplification device 630. The memory cell array 610 is coupled to the sensing amplification device 630 through the multiplexer 620. The sensing amplification device 630 can be implemented by using the sensing amplification devices 100, 200, or 500 of the foregoing embodiments. The memory cell array 610 can be a static random access memory cell array, a dynamic random access memory cell array, a flash memory cell array, a resistive random-access memory (ReRAM) cell array, a phase change random-access memory (PCRAM) cell array, or a magnetoresistive random-access memory (MRAM) cell array.

[0057] The sensing amplifier device 630 of the embodiment of the present application can directly receive the power voltage provided by the power supply generator of the non-voltage pump circuit as the operating voltage, and correctly senses the readout information of the memory cell array 610, so as to effectively reduce the required power consumption.

[0058] In summary, the present application provides a bit line bias adjuster constructed by using transistors with low threshold voltage. The bit line bias adjuster can receive the power voltage without boosting as the operating voltage, and effectively generates the adjusted reference bit line voltage. The sensing amplifier circuit can perform the sensing operation of the memory cell current according to the adjusted reference bit line voltage, and generate the sensing result. In this way, the sensing amplifier device can normally operate under the condition of low power voltage, and effectively reduce the required power consumption.

Claims

1. A sense amplification device, comprising: The bit line bias adjuster receives a supply voltage as an operating voltage, and includes: a first amplifier receiving a reference bit line voltage and a feedback voltage, and generating an adjusted reference bit line voltage based on the supply voltage, the reference bit line voltage, and the feedback voltage; a first transistor having a first end receiving the supply voltage, a second end generating the feedback voltage, and a control end receiving the adjusted reference bit line voltage; and a first current source coupled between the second end of the first transistor and a reference ground end; and a sense amplifier circuit receiving the supply voltage as an operating voltage, and generating a sensing result based on the adjusted reference bit line voltage. The sense amplifier circuit includes: a first current voltage converter having a first end receiving the supply voltage; a second current voltage converter having a first end receiving the supply voltage; a second transistor coupled between a second end of the first current voltage converter and the reference ground end, and controlled by the adjusted reference bit line voltage; a third transistor coupled between a second end of the second current voltage converter and the reference ground end, and controlled by the adjusted reference bit line voltage; a first selection switch coupled between the second transistor and the reference ground end, and controlled by a selection voltage; a second selection switch coupled between the third transistor and the reference ground end, and controlled by the selection voltage; a second current source coupled between the first selection switch and the reference ground end, and providing a storage cell current; a third current source coupled between the second selection switch and the reference ground end, and providing a reference current; and a second amplifier having two input ends coupled to the second end of the first current voltage converter and the second end of the second current voltage converter, respectively, and generating the sensing result at an output end thereof. The first amplifier includes:

2. The sense amplifier device of claim 1, wherein, a differential pair receiving the reference bit line voltage and the feedback voltage, and generating a first current and a second current based on the reference bit line voltage and the feedback voltage, respectively; an active load coupled to two differential ends of the differential pair, and generating the adjusted reference bit line voltage based on the second current; and a fourth current source coupled to a common end of the differential pair, and providing a common current, wherein a sum of the first current and the second current is equal to the common current. The differential pair includes:

3. The sense amplifier device of claim 2, wherein, a fourth transistor having a first end coupled to a first differential end, a second end coupled to the common end, and a control end receiving the reference bit line voltage; and a fifth transistor having a first end coupled to a second differential end, a second end coupled to the common end, and a control end receiving the feedback voltage. The active load includes:

4. The sense amplifier device of claim 3, wherein, a sixth transistor having a first end receiving the supply voltage, a second end, and a control end coupled to the first differential end; and a seventh transistor having a first end receiving the supply voltage, a second end, and a control end coupled to the second differential end. A seventh transistor has a first terminal receiving the power supply voltage, a second terminal coupled to the second differential terminal, and a control terminal coupled to a control terminal of the sixth transistor.

5. The sense amplifier device of claim 4, wherein, The fourth to seventh transistors operate in a saturation region.

6. The sense amplifier device of claim 1, wherein, The threshold voltages of the second and third transistors are less than a reference value equal to a threshold voltage of a general transistor.

7. The sense amplifier device of claim 1, wherein, The first and second current-voltage converters are a first resistor and a second resistor, respectively.

8. The sense amplifier device of claim 1, wherein, The first and second current-voltage converters are a fourth transistor and a fifth transistor, respectively, wherein the fourth transistor has a first terminal receiving the power supply voltage, a second terminal coupled to a first terminal of the second transistor, and a control terminal receiving a bias voltage, and the fifth transistor has a first terminal receiving the power supply voltage, a second terminal coupled to a first terminal of the third transistor, and a control terminal receiving the bias voltage.

9. The sense amplifier device of claim 8, wherein, The fourth and fifth transistors operate in a linear region.

10. The sense amplifier device of claim 8, wherein, The second to fifth transistors are disposed in a same well region.

11. The sense amplifier device of claim 8, wherein, The gate oxide layers of the second and third transistors have a thickness less than that of the gate oxide layers of the fourth and fifth transistors.

12. The sense amplifier device of claim 1, wherein, The first amplifier includes: a fourth transistor having a first terminal receiving the power supply voltage, a second terminal generating the adjusted reference bit line voltage, and a control terminal receiving a bias voltage related to the reference bit line voltage; and a fifth transistor having a first terminal coupled to the second terminal of the fourth transistor, a second terminal coupled to the reference ground terminal, and a control terminal receiving the feedback voltage.

13. The sense amplifier device of claim 1, wherein, Further comprising: a power supply, wherein the power supply is a non-charge-pump voltage generator.

14. The sense amplifier device of claim 1, wherein, The threshold voltage of the first transistor is less than a reference value equal to a threshold voltage of a general transistor.

15. A memory, comprising: Comprising: a memory cell array; a multiplexer; and The sensing amplifier device of claim 1, coupled to the memory cell array through the multiplexer to sense a memory cell current of a selected memory cell in the memory cell array to generate the sensing result.

16. The memory of claim 15, wherein, The memory cell array is a static random access memory cell array, a dynamic random access memory cell array, a flash memory cell array, a resistive memory cell array, a phase change memory cell array, or a magnetoresistive random access memory cell array.

Images