A wafer acceptance test structure and manufacturing method

Abstract

The present invention provides a wafer acceptance test structure and a manufacturing method thereof. The method includes: providing a semiconductor layer, the semiconductor layer including an isolation layer and an active region; forming a gate oxide layer on the active region around the isolation layer; forming polysilicon gates arranged in the X direction and polysilicon gates arranged in the Y direction on the gate oxide layer; forming an interlayer dielectric layer on the substrate; forming contact vias in the interlayer dielectric layer, with a first part of the contact vias connected to the active region and a second part of the contact vias connected to the polysilicon gates. By forming polysilicon gates arranged in the X direction and polysilicon gates arranged in the Y direction on the active region and measuring the capacitance between the polysilicon gates and the active region to obtain the alignment offset in the X direction or the Y direction, the present invention can quickly test all wafers; moreover, the deviation of the pattern dimensions of each layer in the process has no influence on the test result, and the rotation in the pattern lithography process has no influence on the test; meanwhile, the process of this structure is compatible with all platforms with CMOS processes.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor production and manufacturing, and relates to a wafer acceptance test structure and a manufacturing method. Background Art

[0002] The semiconductor manufacturing process is a collection of processes such as photolithography / etching / ion implantation using different mask layers, and film coating / thermal oxidation / heat treatment / planarization / metallization. For the photolithography process, the pattern transfer of the prepared mask is performed using a photolithography machine, and the pattern on the mask is replicated on the wafer. Different mask layers need to be aligned. Even the most advanced photolithography machine cannot achieve complete alignment, and there will be offsets (i.e., registration offsets). In the semiconductor manufacturing process, the registration offset (OVL) is measured after each photolithography step, that is, the alignment pattern prepared in advance on the mask is used to measure its overlay error. However, the measurement process takes a certain amount of time, and only a few wafers can be selected for each layer to measure individual discrete points. This measurement method in the manufacturing process can roughly monitor the stability of the process and the level of registration offset, but it cannot guarantee the offset of each wafer. For some key layers, it is more desirable to quickly and comprehensively measure the registration offset in production, and conduct a more comprehensive investigation of possible problems, rather than selecting wafers for discrete point measurement.

[0003] Therefore, how to provide a new wafer acceptance test structure and manufacturing method to improve the detection efficiency and enable rapid and comprehensive overlay offset measurement of all wafers has become a technical problem that needs to be urgently solved by technical personnel in this field. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a wafer acceptance test structure and a manufacturing method for solving the problems in the prior art of slow efficiency in measuring offset errors using alignment patterns and incomplete troubleshooting of problems using wafer selection measurements.

[0005] To achieve the above-mentioned and other related purposes, the present invention provides a method for manufacturing a wafer acceptance test structure, comprising the following steps:

[0006] Providing a semiconductor layer, the semiconductor layer comprising a substrate, a well region and an isolation layer, the well region is located in the substrate, and the isolation layer is located in the well region to isolate an active region in the well region;

[0007] forming a gate oxide layer on the active area around the isolation layer;

[0008] A first polysilicon gate, a second polysilicon gate, a third polysilicon gate, and a fourth polysilicon gate are formed on the gate oxide layer. The first polysilicon gate and the second polysilicon gate are arranged at opposite sides of the isolation layer at intervals in the X direction. The third polysilicon gate and the fourth polysilicon gate are arranged at opposite sides of the isolation layer at intervals in the Y direction. One ends of the first polysilicon gate, the second polysilicon gate, the third polysilicon gate, and the fourth polysilicon gate facing the isolation layer all extend above the isolation layer;

[0009] An interlayer dielectric layer is formed on the substrate, and the interlayer dielectric layer covers the first polysilicon gate, the second polysilicon gate, the third polysilicon gate, the fourth polysilicon gate, the active region, and the isolation layer;

[0010] A plurality of contact vias are formed in the interlayer dielectric layer, and the contact vias penetrate the interlayer dielectric layer in the vertical direction. Among them, the plurality of contact vias include a first contact via connected to the active region and at least four second contact vias arranged at intervals and respectively connected to the first polysilicon gate, the second polysilicon gate, the third polysilicon gate, and the fourth polysilicon gate.

[0011] Optionally, before forming the interlayer dielectric layer, it further includes the step of forming a first-conductivity-type heavily doped or second-conductivity-type heavily doped contact layer on the surfaces of the first polysilicon gate, the second polysilicon gate, the third polysilicon gate, the fourth polysilicon gate, and the active region. The first contact via is connected to the active region through the contact layer, and the second contact vias are respectively connected to the first polysilicon gate, the second polysilicon gate, the third polysilicon gate, and the fourth polysilicon gate through the contact layer.

[0012] Optionally, the number of the first contact vias is not less than four, and the plurality of first contact vias are arranged at intervals.

[0013] Optionally, in the aligned state, the first polysilicon gate and the second polysilicon gate are symmetrically distributed based on the isolation layer, and the third polysilicon gate and the fourth polysilicon gate are symmetrically distributed based on the isolation layer.

[0014] Optionally, the interval distance between the first polysilicon gate and the second polysilicon gate in the X direction is greater than the width of the third polysilicon gate and the fourth polysilicon gate, and the interval distance between the third polysilicon gate and the fourth polysilicon gate in the Y direction is greater than the width of the first polysilicon gate and the second polysilicon gate.

[0015] The present invention also provides a wafer acceptance test structure, including:

[0016] A semiconductor layer, the semiconductor layer including a substrate, a well region, and an isolation layer, the well region being located in the substrate, and the isolation layer being located in the well region to isolate an active region in the well region;

[0017] A gate oxide layer, located on the active region around the isolation layer;

[0018] A first polysilicon gate, a second polysilicon gate, a third polysilicon gate, and a fourth polysilicon gate, the first polysilicon gate, the second polysilicon gate, the third polysilicon gate, and the fourth polysilicon gate all being located on the gate oxide layer, the first polysilicon gate and the second polysilicon gate being arranged at intervals in the X direction on opposite sides of the isolation layer, the third polysilicon gate and the fourth polysilicon gate being arranged at intervals in the Y direction on opposite sides of the isolation layer, and one ends of the first polysilicon gate, the second polysilicon gate, the third polysilicon gate, and the fourth polysilicon gate facing the isolation layer all extending above the isolation layer;

[0019] An interlayer dielectric layer, located on the substrate, the interlayer dielectric layer covering the first polysilicon gate, the second polysilicon gate, the third polysilicon gate, the fourth polysilicon gate, the active region, and the isolation layer;

[0020] A plurality of contact vias, located in the interlayer dielectric layer and penetrating the interlayer dielectric layer in the vertical direction, wherein the plurality of contact vias include a first contact via connected to the active region and at least four second contact vias arranged at intervals and respectively connected to the first polysilicon gate, the second polysilicon gate, the third polysilicon gate, and the fourth polysilicon gate.

[0021] Optionally, further including a contact layer doped with a first conductivity type or a second conductivity type, the contact layer being located on upper surfaces of the first polysilicon gate, the second polysilicon gate, the third polysilicon gate, the fourth polysilicon gate, and the active region, the first contact via being connected to the active region through the contact layer, and the second contact vias being respectively connected to the first polysilicon gate, the second polysilicon gate, the third polysilicon gate, and the fourth polysilicon gate through the contact layer.

[0022] Optionally, the number of the first contact vias is not less than four, and the plurality of first contact vias are arranged at intervals.

[0023] Optionally, in an aligned state, the first polysilicon gate and the second polysilicon gate are symmetrically distributed based on the isolation layer, and the third polysilicon gate and the fourth polysilicon gate are symmetrically distributed based on the isolation layer.

[0024] Optionally, the spacing distance between the first polysilicon gate and the second polysilicon gate in the X direction is greater than the width of the third polysilicon gate and the fourth polysilicon gate, and the spacing distance between the third polysilicon gate and the fourth polysilicon gate in the Y direction is greater than the width of the first polysilicon gate and the second polysilicon gate.

[0025] As described above, in the wafer acceptance test structure and manufacturing method of the present invention, by forming polysilicon gates arranged in the X direction and polysilicon gates arranged in the Y direction on the active region, and measuring the capacitance between the polysilicon gates and the active region to obtain the alignment offset in the X direction or the Y direction, all wafers can be quickly tested instead of selected wafer testing; moreover, the deviation of the pattern sizes of each layer in the process has no influence on the test results, and the rotation during the pattern overlay process has no influence on the test; at the same time, this structure has good process compatibility and is compatible with all platforms containing CMOS processes, and this structure can be tested together with other electrical test parameters during the wafer acceptance test process without adding additional test steps. Brief Description of the Drawings

[0026] Figure 1 It shows a flowchart of a manufacturing method of a wafer acceptance test structure provided in Embodiment 1 of the present invention.

[0027] Figure 2 It shows a schematic diagram of a semiconductor layer provided in Embodiment 1 of the present invention.

[0028] Figure 3 It shows a schematic diagram of forming a gate oxide layer on the active region around the isolation layer in Embodiment 1 of the present invention.

[0029] Figure 4 It shows a schematic diagram of forming a polysilicon gate on the gate oxide layer in Embodiment 1 of the present invention.

[0030] Figure 5 It shows a schematic diagram of forming an interlayer dielectric layer on the substrate in Embodiment 1 of the present invention.

[0031] Figure 6 It shows a schematic diagram of forming a contact via in the interlayer dielectric layer in Embodiment 1 of the present invention.

[0032] Figure 7 It shows a schematic diagram of the polysilicon gates arranged in the X direction and the Y direction in Embodiment 1 of the present invention.

[0033] Figure 8 It shows a schematic diagram of the alignment error of the polysilicon gate by the active region with an offset of a in the X direction in Embodiment 1 of the present invention.

[0034] Description of Component Labels

[0035] 1 Substrate

[0036] 2 Isolation layer

[0037] 3 Well region

[0038] 4 Gate oxide layer

[0039] 5 First polysilicon gate

[0040] 6 Second polysilicon gate

[0041] 7 Third polysilicon gate

[0042] 8 Fourth polysilicon gate

[0043] 9 Contact layer

[0044] 10 Interlayer dielectric layer

[0045] 11 First contact via

[0046] 12 Second contact via

[0047] 13 Third contact via

[0048] 14 Fourth contact via

[0049] 15 Fifth contact via

[0050] Lengths of L, LP, SL, SW

[0051] Width W

[0052] Spacing distance SP

[0053] Offset a

[0054] Steps S1 to S5 Detailed implementation manners

[0055] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0056] Please refer to Figures 1 to 8 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0057] Embodiment 1

[0058] This embodiment provides a method for manufacturing a wafer acceptance test structure. Please refer to Figure 1 , which shows a flowchart of this manufacturing method, including the following steps:

[0059] S1: Provide a semiconductor layer, which includes a substrate, a well region, and an isolation layer. The well region is located in the substrate, and the isolation layer is located in the well region to isolate an active region in the well region;

[0060] S2: Form a gate oxide layer on the active region around the isolation layer;

[0061] S3: Form a first polysilicon gate, a second polysilicon gate, a third polysilicon gate, and a fourth polysilicon gate on the gate oxide layer. The first polysilicon gate and the second polysilicon gate are arranged at intervals in the X direction on opposite sides of the isolation layer, the third polysilicon gate and the fourth polysilicon gate are arranged at intervals in the Y direction on opposite sides of the isolation layer, and one ends of the first polysilicon gate, the second polysilicon gate, the third polysilicon gate, and the fourth polysilicon gate facing the isolation layer all extend above the isolation layer;

[0062] S4: Form an interlayer dielectric layer on the substrate, and the interlayer dielectric layer covers the first polysilicon gate, the second polysilicon gate, the third polysilicon gate, the fourth polysilicon gate, the active region, and the isolation layer;

[0063] S5: Form a plurality of contact vias in the interlayer dielectric layer, and the contact vias penetrate the interlayer dielectric layer in the vertical direction. Among them, the plurality of contact vias include a first contact via connected to the active region and at least four second contact vias arranged at intervals and respectively connected to the first polysilicon gate, the second polysilicon gate, the third polysilicon gate, and the fourth polysilicon gate.

[0064] First, please refer to Figure 2 , and perform step S1: Provide a semiconductor layer, which includes a substrate 1, a well region 3, and an isolation layer 2. The well region 3 is located in the substrate 1, and the isolation layer 2 is located in the well region 3 to isolate an active region in the well region 3.

[0065] As an example, the substrate 1 has no specific limitation and can be a silicon substrate, a germanium substrate, silicon on insulator, or germanium on insulator, etc., and can also be silicon germanide, gallium arsenide, etc.

[0066] As an example, the isolation layer 2 is formed by using a shallow trench isolation (STI) process, and the isolation layer 2 is located on one side of the upper surface of the substrate 1.

[0067] As an example, after forming the isolation layer 2, the well region 3 doped with the first conductive type is formed by photolithography and implantation.

[0068] Next, refer to Figure 3 , and perform step S2: form a gate oxide layer 4 on the active region around the isolation layer 2.

[0069] As an example, a gate oxide material layer is formed on the substrate 1 by a deposition process, and the gate oxide material layer is etched, and the gate oxide material layer in the region where the polysilicon gate is to be formed subsequently is retained to form the gate oxide layer 4.

[0070] Next, refer to Figure 4 and Figure 7 , and perform step S3: form a first polysilicon gate 5, a second polysilicon gate 6, a third polysilicon gate 7, and a fourth polysilicon gate 8 on the gate oxide layer 4. The first polysilicon gate 5 and the second polysilicon gate 6 are arranged at intervals in the X direction on opposite sides of the isolation layer 2, the third polysilicon gate 7 and the fourth polysilicon gate 8 are arranged at intervals in the Y direction on opposite sides of the isolation layer 2, and one end of each of the first polysilicon gate 5, the second polysilicon gate 6, the third polysilicon gate 7, and the fourth polysilicon gate 8 extending toward the isolation layer 2 extends above the isolation layer 2; wherein, Figure 4 shows a schematic cross-sectional structure presented after performing this step, Figure 7 shows a planar layout diagram of the test structure to be fabricated in this embodiment.

[0071] As an example, a polysilicon layer is formed on the substrate 1, the polysilicon layer covers the active region, the gate oxide layer 4, and the isolation layer 2, and then a preset position of the polysilicon layer is etched to form the first polysilicon gate 5, the second polysilicon gate 6, the third polysilicon gate 7, and the fourth polysilicon gate 8. A part of each individual polysilicon gate is located on the gate oxide layer 4, and the other part is located on the isolation layer 2.

[0072] As an example, in the aligned state, the first polysilicon gate 5 and the second polysilicon gate 6 are symmetrically distributed based on the isolation layer 2, the third polysilicon gate 7 and the fourth polysilicon gate 8 are symmetrically distributed based on the isolation layer 2, and the shapes of the active region and the polysilicon gate are rectangular or rectangular rings, ensuring the parallelism of the active region and the polysilicon gate in the direction where offset may occur.

[0073] As an example, each polysilicon gate has a certain length in the non-test dimension to avoid the problem of non-uniform formation of narrow patterns in the manufacturing process due to the narrow shape of the polysilicon gate, and the size in the test dimension should meet the test / calculation requirements and be able to accommodate the influence of registration error and critical dimension offset of the pattern.

[0074] As an example, such as Figure 8 shown, taking the first polysilicon gate 5 and the second polysilicon gate 6 arranged in the X direction as an example, the range of the width W of the polysilicon gate is 10 to 20 micrometers (μm), and the range of the length L of the part of the polysilicon gate located above the active region (i.e., the length of the overlapping surface between the polysilicon gate and the active region) is 10 to 100 μm.

[0075] As an example, the length SL by which the active region protrudes from the polysilicon gate in the X direction is not less than 2 μm, the length SW by which the active region protrudes from the polysilicon gate in the Y direction is not less than 2 μm, and the length LP by which the polysilicon gate protrudes from the active region in the X direction is not less than 2 μm to avoid the influence of edge effects.

[0076] As an example, the distance interval SP between the first polysilicon gate 5 and the second polysilicon gate 6 in the X direction is greater than the widths of the third polysilicon gate 7 and the fourth polysilicon gate 8. Similarly, the distance interval between the third polysilicon gate 7 and the fourth polysilicon gate 8 in the Y direction is greater than the widths of the first polysilicon gate 5 and the second polysilicon gate 6 to avoid the overlapping of the X direction and the Y direction during offset due to insufficient distance interval between the polysilicon gates, which affects the capacitance test.

[0077] As an example, after forming the first polysilicon gate 5, the second polysilicon gate 6, the third polysilicon gate 7, and the fourth polysilicon gate 8, it further includes the step of forming a protective layer (not shown) on the sidewalls of the first polysilicon gate 5, the second polysilicon gate 6, the third polysilicon gate 7, and the fourth polysilicon gate 8, and the protective layer includes but is not limited to a silicon dioxide layer.

[0078] It should be noted that in this embodiment, only the case where the first polysilicon gate 5, the second polysilicon gate 6, the third polysilicon gate 7, and the fourth polysilicon gate 8 are each one is listed, and this embodiment is not restrictive. The number of polysilicon gates can be set to less than 4 or more than 4 according to actual needs.

[0079] Next, please refer to Figure 5 , perform step S4: form an interlayer dielectric layer 10 on the substrate 1, and the interlayer dielectric layer 10 covers the first polysilicon gate 5, the second polysilicon gate 6, the third polysilicon gate 7, the fourth polysilicon gate 8, the active region, and the isolation layer 2.

[0080] As an example, before forming the interlayer dielectric layer 10, it further includes a step of forming a first-conductivity-type heavily doped or second-conductivity-type heavily doped contact layer 9 on the surfaces of the first polysilicon gate 5, the second polysilicon gate 6, the third polysilicon gate 7, the fourth polysilicon gate 8, and the active region. The heavily doped contact layer 9 is used to form an ohmic contact subsequently. Preferably, the contact layer 9 is formed by ion implantation of the first conductivity type that is the same as the conductivity type of the well region 3. Of course, it can also be formed by ion implantation of the second conductivity type. Since the capacitance is mainly concentrated in the gate oxide layer 4 region, the conductivity type of the contact layer 9 has little influence on the capacitance test.

[0081] In this embodiment, the first conductivity type is N-type and the second conductivity type is P-type; in other embodiments, the first conductivity type can also be P-type and the second conductivity type can be N-type.

[0082] As an example, the interlayer dielectric layer 10 is formed by a deposition process, and the material of the interlayer dielectric layer 10 includes insulating dielectrics such as an oxide layer or a nitride.

[0083] Next, please refer to Figure 6 and Figure 7 , and perform step S5: forming a plurality of contact vias in the interlayer dielectric layer 10, the contact vias penetrating the interlayer dielectric layer 10 in the vertical direction. Among them, the plurality of contact vias include a first contact via connected to the active region and at least four second contact vias arranged at intervals and respectively connected to the first polysilicon gate 5, the second polysilicon gate 6, the third polysilicon gate 7, and the fourth polysilicon gate 8.

[0084] As an example, the second contact vias include a first contact via 11, a second contact via 12, a third contact via 13, and a fourth contact via 14. The first contact via 11 is connected to the first polysilicon gate 5 through the contact layer 9, the second contact via 12 is connected to the second polysilicon gate 6 through the contact layer 9, the third contact via 13 is connected to the third polysilicon gate 7 through the contact layer 9, and the fourth contact via 14 is connected to the fourth polysilicon gate 8 through the contact layer 9; the first contact via includes a fifth contact via 15, and the fifth contact via 15 is connected to the active region through the contact layer 9.

[0085] As an example, a certain distance is provided between the boundary of each contact via and the boundary of the active region and the polysilicon gate to avoid errors in capacitance testing. Preferably, the distance between the boundary of the contact via and the boundary of the active region and the polysilicon gate is greater than 1 μm.

[0086] It should be noted that the dimensions of each embodiment in this example are recommended dimensions based on the 180nm process. In actual production and manufacturing, the dimensions of other process platforms can be adjusted accordingly on this basis, and other design dimensions that meet the requirements also fall within the scope of the present invention.

[0087] As an example, the number of the fifth contact vias 15 is preferably four or more. During the alignment offset test, the capacitances between the first polysilicon gate 5, the second polysilicon gate 6, the third polysilicon gate 7, the fourth polysilicon gate 8 and the active region can be measured simultaneously, and the alignment errors in the X direction and the Y direction can be measured simultaneously, improving the test efficiency. Of course, the test structures in the X direction or the Y direction can be independently set without affecting the test results.

[0088] As an example, the numbers of the first contact via 11, the second contact via 12, the third contact via 13, the fourth contact via 14 and the fifth contact via 15 are set according to actual requirements and are not limited by this embodiment.

[0089] As an example, a metal wiring layer is formed at each contact via. Figure 6 and Figure 7 The specific manner of the metal wiring layer is not shown in the figure. These metal connection layers are connected to the test pins of the electrical test machine during the test. During actual metal wiring, the contact vias will be connected to the corresponding test pin metal plates (PADs), and there will be no situation where the contact vias are floating.

[0090] As an example, the test process includes the following steps:

[0091] (1) Test the capacitances at both ends of the first polysilicon gate 5 and the active region, the second polysilicon gate 6 and the active region, the third polysilicon gate 7 and the active region, and the fourth polysilicon gate 8 and the active region to obtain capacitance values C1, C2, C3 and C4;

[0092] (2) Subtract C2 from C1 to get DC1, subtract C4 from C3 to get DC2, add C1 and C2 to get MC1, add C3 and C4 to get MC2, and the ratio of DC to MC corresponds to its offset in the X direction or the Y direction.

[0093] As an example, as Figure 8 shown, taking the X-direction offset as an example, assuming that in the case of zero offset, the length of the overlapping surface between the polysilicon gate and the active region is L, C1 = C0, C2 = C0, at this time DC1 = 0, MC1 = 2C0, and the output value is 0, indicating that the X-direction offset is 0 and there is no alignment error; when the rightward offset is a, C1 = C0*(L - a) / L, C2 = C0*(L + a) / L, at this time DC1 = C0*(-2a / L), MC1 = 2C0, and the output value is -a / L, that is, the alignment error is a / L times the L length to the right.

[0094] As an example, arithmetic operations can be performed on the data inside the electrical testing machine tool, so that the output value is the registration error value. Taking the X direction as an example: W = 10000 nm, L = 10000 nm. When the X direction offset is 50 nm to the left, the initial output value is 50 / 100000 = 0.0005. Multiply this output value by L, and at this time the output is 50, which is the value of the offset itself.

[0095] As an example, the registration offset test process can be tested together with other electrical testing parameters without adding additional testing steps.

[0096] It should be noted that during the process of the lithography machine transferring the pattern on the pre-prepared photomask and replicating the pattern on the photomask to the wafer, there may not only be an offset in position, but also a situation where the pattern size replicated on the wafer is larger or smaller than the photomask pattern. For the symmetric design structure in the X direction or Y direction, the deviation of the pattern size that is larger or smaller has no influence on the test result of the offset error, that is, the deviation of the pattern size of each layer in the process has no influence on the test result.

[0097] In summary, in the manufacturing method of the wafer acceptance test structure provided in this embodiment, by forming polysilicon gates arranged in the X direction and polysilicon gates arranged in the Y direction on the active region, and measuring the capacitance between the polysilicon gates and the active region to obtain the registration offset in the X direction or Y direction, all wafer pieces can be quickly tested instead of selected wafer testing; and the deviation of the pattern size of each layer in the process has no influence on the test result, and the rotation during the pattern overlay process has no influence on the test; at the same time, this process has good compatibility and is compatible with all platforms containing CMOS processes.

[0098] Embodiment 2

[0099] Please refer to Figures 6 to 8 , this embodiment provides a wafer acceptance test structure, and the wafer acceptance test structure can be manufactured by the manufacturing method described in Embodiment 1, but is not limited to the manufacturing method described in Embodiment 1.

[0100] The wafer acceptance structure includes a semiconductor layer, a gate oxide layer 4, a first polysilicon gate 5, a second polysilicon gate 6, a third polysilicon gate 7, a fourth polysilicon gate 8, an interlayer dielectric layer 10, and a plurality of contact vias. Among them, the semiconductor layer includes a substrate 1, a well region 3, and an isolation layer 2. The well region 3 is located in the substrate 1, and the isolation layer 2 is located in the well region 3 to isolate active regions in the well region 3; the gate oxide layer 4 is located on the active regions around the isolation layer 2; the first polysilicon gate 5, the second polysilicon gate 6, the third polysilicon gate 7, and the fourth polysilicon gate 8 are all located on the gate oxide layer 4. The first polysilicon gate 5 and the second polysilicon gate 6 are arranged at intervals in the X direction on opposite sides of the isolation layer 2, the third polysilicon gate 7 and the fourth polysilicon gate 8 are arranged at intervals in the Y direction on opposite sides of the isolation layer 2, and one ends of the first polysilicon gate 5, the second polysilicon gate 6, the third polysilicon gate 7, and the fourth polysilicon gate 8 facing the isolation layer 2 all extend above the isolation layer 2; the interlayer dielectric layer 10 is located on the substrate, and the interlayer dielectric layer 10 covers the first polysilicon gate 5, the second polysilicon gate 6, the third polysilicon gate 7, the fourth polysilicon gate 8, the active regions, and the isolation layer 2; the plurality of contact vias are located in the interlayer dielectric layer 10 and penetrate the interlayer dielectric layer 10 in the vertical direction. Among them, the plurality of contact vias include a first contact via connected to the active region and at least four second contact vias arranged at intervals and respectively connected to the first polysilicon gate 5, the second polysilicon gate 6, the third polysilicon gate 7, and the fourth polysilicon gate 8.

[0101] As an example, the well region 3 is of the first conductivity type.

[0102] As an example, as Figure 7 shown, the first polysilicon gate 5 and the second polysilicon gate 6 are symmetrically distributed based on the isolation layer 2, the third polysilicon gate 7 and the fourth polysilicon gate 8 are symmetrically distributed based on the isolation layer 2, and the shapes of the active regions and the polysilicon gates are rectangular or rectangular rings to ensure the parallelism of the active regions and the polysilicon gates in the direction where offset may occur.

[0103] As an example, each polysilicon gate has a certain length in the non-test dimension to avoid the problem of uneven formation of narrow patterns in the manufacturing process due to the narrow shape of the polysilicon gate. The size in the test dimension should meet the test / calculation requirements and be able to accommodate the effects of registration errors and critical dimension offsets of the patterns.

[0104] As an example, as Figure 8As shown, taking the first polysilicon gate 5 and the second polysilicon gate 6 arranged in the X direction as an example, the width W of the polysilicon gate ranges from 10 to 20 micrometers (μm), and the length L of the part of the polysilicon gate above the active region (i.e., the length of the overlapping surface of the polysilicon gate and the active region) ranges from 10 to 100 μm.

[0105] As an example, the length SL by which the active region protrudes from the polysilicon gate in the X direction is not less than 2 μm, and the length SW by which the active region protrudes from the polysilicon gate in the Y direction is not less than 2 μm. The length LP by which the polysilicon gate protrudes from the active region in the X direction is not less than 2 μm to avoid the influence of edge effects.

[0106] As an example, the distance interval SP between the first polysilicon gate 5 and the second polysilicon gate 6 in the X direction is greater than the width of the third polysilicon gate 7 and the fourth polysilicon gate 8. Similarly, the distance interval between the third polysilicon gate 7 and the fourth polysilicon gate 8 in the Y direction is greater than the width of the first polysilicon gate 5 and the second polysilicon gate 6, avoiding the influence of insufficient distance interval between polysilicon gates on the capacitance test during offset in the X and Y directions.

[0107] As an example, steps of providing protective layers (not shown) on the sidewalls of the first polysilicon gate 5, the second polysilicon gate 6, the third polysilicon gate 7, and the fourth polysilicon gate 8 are provided. The protective layer includes but is not limited to a silicon dioxide layer.

[0108] It should be noted that in this embodiment, only the case where the first polysilicon gate 5, the second polysilicon gate 6, the third polysilicon gate 7, and the fourth polysilicon gate 8 are each one is listed, and this embodiment is not restrictive. Less than 4 or more than 4 polysilicon gates can be set according to actual needs.

[0109] As an example, a contact layer 9 doped with a first conductivity type or a second conductivity type is provided between the first polysilicon gate 5, the second polysilicon gate 6, the third polysilicon gate 7, the fourth polysilicon gate 8, and the active region and the interlayer dielectric layer 10. The heavily doped contact layer 9 is used to form an ohmic contact with the contact via. Preferably, the contact layer 9 is formed by ion implantation of the first conductivity type having the same conductivity type as the well region 3. Of course, it can also be formed by ion implantation of the second conductivity type. Since the capacitance is mainly concentrated in the gate oxide layer 4 region, the conductivity type of the contact layer 9 has little influence on the capacitance test.

[0110] In this embodiment, the first conductivity type is N type and the second conductivity type is P type; in other embodiments, the first conductivity type can also be P type and the second conductivity type can be N type.

[0111] As an example, the second contact via holes include a first contact via hole 11, a second contact via hole 12, a third contact via hole 13, and a fourth contact via hole 14. The first contact via hole 11 is connected to the first polysilicon gate 5 through the contact layer 9. The second contact via hole 12 is connected to the second polysilicon gate 6 through the contact layer 9. The third contact via hole 13 is connected to the third polysilicon gate 7 through the contact layer 9. The fourth contact via hole 14 is connected to the fourth polysilicon gate 8 through the contact layer 9. The first contact via hole includes a fifth contact via hole 15, and the fifth contact via hole 15 is connected to the active region through the contact layer 9.

[0112] As an example, a certain distance is provided between the boundary of each contact via hole and the boundary of the active region and the polysilicon gate to avoid errors in capacitance testing. Preferably, the distance between the contact via hole and the boundary of the active region and the polysilicon gate is greater than 1 μm.

[0113] It should be noted that the dimensions of each embodiment herein are recommended dimensions based on the 180 nm process. In actual production and manufacturing, the dimensions of other process platforms can be adjusted accordingly on this basis, and other design dimensions that meet the requirements also fall within the scope of the present invention.

[0114] As an example, the number of the fifth contact via holes 15 is preferably four or more. During the alignment offset test process, the capacitance between the first polysilicon gate 5, the second polysilicon gate 6, the third polysilicon gate 7, the fourth polysilicon gate 8 and the active region can be measured simultaneously, and the alignment errors in the X direction and the Y direction can be measured simultaneously, improving the test efficiency. Of course, the test structures in the X direction or the Y direction can be independently set without affecting the test results.

[0115] As an example, the numbers of the first contact via hole 11, the second contact via hole 12, the third contact via hole 13, the fourth contact via hole 14, and the fifth contact via hole 15 are set according to actual needs and are not limited to this embodiment.

[0116] As an example, a metal wiring layer is provided at each contact via hole. Figure 6 and Figure 7 The specific manner of the metal wiring layer is not shown in the figure. These metal connection layers are connected to the test pins of the electrical test machine during the test process. During actual metal wiring, the contact via holes will be connected to the corresponding test pin metal plates (PADs), and there will be no situation where the contact via holes are floating.

[0117] As an example, the wafer acceptance test structure is formed in the scribe line of the wafer without occupying the area of the integrated chip.

[0118] In summary, in the wafer acceptance test structure and manufacturing method of the present invention, by forming polysilicon gates arranged in the X direction and polysilicon gates arranged in the Y direction on the active region, and measuring the capacitance between the polysilicon gates and the active region to obtain the alignment offset in the X direction or the Y direction, all wafers can be quickly tested instead of selective testing; moreover, the deviation of the pattern dimensions of each layer in the process has no influence on the test results, and the rotation in the pattern overlay process has no influence on the test; at the same time, this structure has good process compatibility, is compatible with all platforms with CMOS processes, and the wafer acceptability test process can be tested together with other electrical test parameters without adding additional test steps. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0119] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A manufacturing method of a wafer acceptance test structure, characterized in that Comprising the following steps: Providing a semiconductor layer, the semiconductor layer comprising a substrate, a well region and an isolation layer, the well region being located in the substrate, and the isolation layer being located in the well region to isolate an active region in the well region; Forming a gate oxide layer on the active region around the isolation layer; Forming a first polysilicon gate, a second polysilicon gate, a third polysilicon gate and a fourth polysilicon gate on the gate oxide layer, the first polysilicon gate and the second polysilicon gate being arranged at intervals in the X direction on opposite sides of the isolation layer, the third polysilicon gate and the fourth polysilicon gate being arranged at intervals in the Y direction on opposite sides of the isolation layer, one ends of the first polysilicon gate, the second polysilicon gate, the third polysilicon gate and the fourth polysilicon gate facing the isolation layer all extending above the isolation layer, in an aligned state, the first polysilicon gate and the second polysilicon gate being symmetrically distributed based on the isolation layer, the third polysilicon gate and the fourth polysilicon gate being symmetrically distributed based on the isolation layer, a spacing distance between the first polysilicon gate and the second polysilicon gate in the X direction being greater than widths of the third polysilicon gate and the fourth polysilicon gate, and a spacing distance between the third polysilicon gate and the fourth polysilicon gate in the Y direction being greater than widths of the first polysilicon gate and the second polysilicon gate; Forming an interlayer dielectric layer on the substrate, the interlayer dielectric layer covering the first polysilicon gate, the second polysilicon gate, the third polysilicon gate, the fourth polysilicon gate, the active region and the isolation layer; Forming a plurality of contact vias in the interlayer dielectric layer, the contact vias penetrating the interlayer dielectric layer in a vertical direction, wherein the plurality of contact vias includes a first contact via connected to the active region and at least four second contact vias arranged at intervals and respectively connected to the first polysilicon gate, the second polysilicon gate, the third polysilicon gate and the fourth polysilicon gate; 2. The manufacturing method of the wafer acceptance test structure according to claim 1, wherein: Before forming the interlayer dielectric layer, further comprising the step of forming a first conductivity type heavily doped or second conductivity type heavily doped contact layer on surfaces of the first polysilicon gate, the second polysilicon gate, the third polysilicon gate, the fourth polysilicon gate and the active region, the first contact via being connected to the active region through the contact layer, and the second contact vias being respectively connected to the first polysilicon gate, the second polysilicon gate, the third polysilicon gate and the fourth polysilicon gate through the contact layer; 3. The manufacturing method of the wafer acceptance test structure according to claim 1, wherein: The number of the first contact vias is not less than four, and the plurality of first contact vias are arranged at intervals; 4. A wafer acceptance test structure, characterized in that, Comprising: A semiconductor layer, the semiconductor layer comprising a substrate, a well region and an isolation layer, the well region being located in the substrate, and the isolation layer being located in the well region to isolate an active region in the well region; A gate oxide layer, located on the active region around the isolation layer; The first polysilicon gate, the second polysilicon gate, the third polysilicon gate, and the fourth polysilicon gate, where the first polysilicon gate, the second polysilicon gate, the third polysilicon gate, and the fourth polysilicon gate are all located on the gate oxide layer. The first polysilicon gate and the second polysilicon gate are arranged at intervals on opposite sides of the isolation layer in the X direction, the third polysilicon gate and the fourth polysilicon gate are arranged at intervals on opposite sides of the isolation layer in the Y direction, and one end of the first polysilicon gate, the second polysilicon gate, the third polysilicon gate, and the fourth polysilicon gate facing the isolation layer extends above the isolation layer; The interlayer dielectric layer is located on the substrate, and the interlayer dielectric layer covers the first polysilicon gate, the second polysilicon gate, the third polysilicon gate, the fourth polysilicon gate, the active region, and the isolation layer; A plurality of contact vias are located in the interlayer dielectric layer and penetrate the interlayer dielectric layer in the vertical direction. Among them, the plurality of contact vias include a first contact via connected to the active region and at least four second contact vias arranged at intervals and respectively connected to the first polysilicon gate, the second polysilicon gate, the third polysilicon gate, and the fourth polysilicon gate; In the alignment state, the first polysilicon gate and the second polysilicon gate are symmetrically distributed based on the isolation layer, the third polysilicon gate and the fourth polysilicon gate are symmetrically distributed based on the isolation layer. In the X direction, the spacing distance between the first polysilicon gate and the second polysilicon gate is greater than the widths of the third polysilicon gate and the fourth polysilicon gate. In the Y direction, the spacing distance between the third polysilicon gate and the fourth polysilicon gate is greater than the widths of the first polysilicon gate and the second polysilicon gate.

5. The wafer acceptance test structure according to claim 4, characterized in that: It further includes a contact layer doped with a first conductivity type or a second conductivity type. The contact layer is located on the upper surfaces of the first polysilicon gate, the second polysilicon gate, the third polysilicon gate, the fourth polysilicon gate, and the active region. The first contact via is connected to the active region through the contact layer, and the second contact vias are respectively connected to the first polysilicon gate, the second polysilicon gate, the third polysilicon gate, and the fourth polysilicon gate through the contact layer.

6. The wafer acceptance test structure according to claim 4, wherein: The number of the first contact vias is not less than four, and the plurality of first contact vias are arranged at intervals.

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