Layout structure for simultaneously monitoring critical dimension and etch roughness and method of use

Abstract

The present application provides a layout structure for monitoring critical dimension and etching roughness simultaneously, which comprises a mandrel pattern, the mandrel pattern is used to define the position of the mandrel structure formed on the semiconductor substrate, the mandrel structure is used to define the position of the side wall formed, the side wall is used as a mask for forming the semiconductor structure on the semiconductor substrate during etching; a cutting pattern, the cutting pattern is used to cut the semiconductor structure on the semiconductor substrate; a first mask pattern, the first mask pattern is used to define the first and second measurement areas on the semiconductor substrate, the mandrel structure is formed on the first measurement area, and the mandrel structure is not formed on the second measurement area, and the mandrel structure is formed on the sacrificial layer; a second mask pattern, the second mask pattern is used to define the position of the protective layer formed on the second measurement area after the sacrificial layer is removed. The present application can monitor the critical dimension and etching roughness after etching.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a layout structure and method of using it that simultaneously monitors critical dimensions and etching roughness. Background Technology

[0002] During the development of the 14nm FinFET (Fin Field-Effect Transistor) semiconductor structure process, we encountered a problem in the semiconductor structure (Fin) cutting. The active region of the Fin Field-Effect Transistor is different from the previous planar process; it is three-dimensional.

[0003] Please see Figure 1 In semiconductor structure manufacturing, in addition to forming a global semiconductor structure pattern 101 on the semiconductor substrate, it is also necessary to truncate the semiconductor structure, that is, to remove the semiconductor structure in the area where no device is to be formed. The truncation pattern is usually a fine truncation pattern 103 and a coarse truncation pattern 102.

[0004] Semiconductor structure truncation is divided into Fin Fine Cut (FFC) and Fin Coarse Cut (FCC) processes. FFC is precise enough to cut a single semiconductor structure, while FCC can cut multiple semiconductor structures, including lateral cuts parallel to the semiconductor structure and longitudinal cuts perpendicular to it. Typically, FFC is performed first, followed by FCC. This presents a problem: taking FFC as an example, the semiconductor structure is cut away during FFC, making it impossible to monitor the size of the Etching Entity Critical Dimension (AEICD) online. Furthermore, it's impossible to monitor the etching roughness. Currently, monitoring is limited to the number of defects in the semiconductor structure, which is neither intuitive nor timely.

[0005] To address the aforementioned issues, a novel layout structure and its application method that simultaneously monitors critical dimensions and etching roughness are required. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a layout structure and method for simultaneously monitoring critical dimensions and etching roughness, which solves the problem in the prior art semiconductor structure cutting process that it is impossible to monitor the size of critical dimensions after etching online, nor can the etching roughness be monitored, and can only be monitored to a certain extent by the number of defects in the semiconductor structure.

[0007] To achieve the above and other related objectives, the present invention provides a layout structure for simultaneously monitoring critical dimensions and etching roughness, comprising:

[0008] The mandrel pattern is used to define the location where the mandrel structure is formed on the semiconductor substrate, and the mandrel structure is used to define the location where the sidewall is formed. The sidewall is used as a mask during etching to form a semiconductor structure on the semiconductor substrate.

[0009] A cutting pattern, the cutting pattern being used to truncate a portion of a semiconductor structure on the semiconductor substrate;

[0010] A first photomask pattern is used to define a first and a second measurement region on the semiconductor substrate. A core structure is formed on the first measurement region, but the core structure is not formed on the second measurement region. The core structure is formed on the sacrificial layer.

[0011] The second photomask pattern is used to define the location where the protective layer is formed on the second measurement area after the sacrificial layer is removed.

[0012] Preferably, the cutting pattern is a coarse cutting pattern, which is used to cut off multiple semiconductor structures on the semiconductor substrate.

[0013] Preferably, the coarse cutting pattern is used to truncate the two sides of multiple semiconductor structures.

[0014] Preferably, the semiconductor structures are distributed sequentially at equal intervals.

[0015] Preferably, the cutting pattern is a fine cutting pattern, which is used to cut off a single semiconductor structure on the semiconductor substrate.

[0016] Preferably, the precision-cut pattern has at least two different lengths.

[0017] Preferably, the protective layer is a photoresist layer.

[0018] Preferably, the protective layer covers an area on at least one side of the sidewall structure.

[0019] A method for using a layout structure that simultaneously monitors critical dimensions and etching roughness includes:

[0020] Step 1: Provide a substrate on which a stack of layers is formed;

[0021] Step 2: A sacrificial layer is formed on the stacked layers. Then, the etching area of ​​the sacrificial layer is defined by photolithography using the first photomask pattern, so that the core structure is formed on the sacrificial layer in the first measurement area, and the core structure is not formed on the sacrificial layer in the second measurement area. Then, the remaining first photoresist layer is removed, and the sidewall structure is formed on both sides of each core structure. Then, the core structure and the sacrificial layer are removed. The sidewall structure is used as a mask to etch the stacked layers and the substrate below to form the semiconductor structure.

[0022] Step 3: Form a first photoresist layer covering the first and second measurement areas, and pattern the second photoresist layer using a photomask pattern including the second photomask pattern, so that the second photoresist layer on the second measurement area is retained, and the second photoresist layer on the first measurement area is removed, so that the sidewall structure and the stack below are exposed.

[0023] Step 4: Using the sidewall structure as a mask, etch the exposed stack and the substrate to form the semiconductor structure. The semiconductor structure is not formed on the stack and the substrate in the second measurement region.

[0024] Step 5: Remove the remaining second photoresist layer and the sidewall structure;

[0025] Step 6: Form a third photoresist layer covering the sidewall structure and the remaining stacked layers. Use a photomask containing the cutting pattern to open the third photoresist layer to define the etching area. Then etch the semiconductor structure and the stacked layers to cut off part of the semiconductor structure. Form measurement grooves on the stacked layers where the semiconductor structure is not formed, on the substrate below it, and on the semiconductor structure.

[0026] Step 7: Use the measurement groove to obtain the key dimensions and etching roughness after etching.

[0027] Preferably, the substrate in step one is a silicon substrate.

[0028] Preferably, the stack in step one consists of a first oxide layer, a nitrided layer, and a second oxide layer stacked sequentially from bottom to top.

[0029] Preferably, the material of the sidewall structure in step two is silicon dioxide or silicon nitride.

[0030] Preferably, in step six, the multiple semiconductor structures on the semiconductor substrate are truncated.

[0031] Preferably, in step six, a single semiconductor structure on the semiconductor substrate is truncated.

[0032] Preferably, in step seven, the etching process of the semiconductor structure and the measurement groove is measured using a critical size scanning electron microscope to obtain the critical dimensions after etching and the etching roughness.

[0033] As described above, the layout structure for simultaneously monitoring critical dimensions and etching roughness, and its usage method, of the present invention have the following beneficial effects:

[0034] By adding a photomask to cover part of the sidewall structure on the semiconductor substrate, during the subsequent etching process using the sidewall as a mask, no semiconductor structure is formed on the semiconductor substrate and hard mask layer in the covered area. When the semiconductor structure is cut off, an etching pattern will be formed on the semiconductor substrate and hard mask layer in the area where no semiconductor structure is formed, so the critical dimensions and etching roughness after etching can be monitored. Attached Figure Description

[0035] Figure 1 The diagram shown is a cut-off layout of a semiconductor structure in the prior art.

[0036] Figure 2 The diagram shown is a schematic diagram of the truncated semiconductor structure layout of the present invention.

[0037] Figure 3 The diagram shows a schematic representation of the present invention in which the first photoresist layer is retained on the sidewall structure in a certain region.

[0038] Figure 4 The diagram shows the stacked layers under the retained first photoresist layer of the present invention and a schematic diagram of the substrate on which no semiconductor structure is formed.

[0039] Figure 5 The diagram shown illustrates the formation of the measurement groove according to the present invention.

[0040] Figure 6 The diagram illustrates a method for using the layout structure of the present invention, which simultaneously monitors critical dimensions and etching roughness. Detailed Implementation

[0041] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0042] Please see Figure 2 This invention provides a layout structure for simultaneously monitoring critical dimensions and etching roughness, comprising:

[0043] The mandrel pattern is used to define the location where the mandrel structure is formed on the semiconductor substrate 301. The mandrel structure is used to define the location where the sidewall 303 is formed. The sidewall 303 is used as a mask during etching to form a semiconductor structure 305 on the semiconductor substrate 301. The semiconductor structure 305 is fin-shaped.

[0044] Cutting pattern, the cutting pattern is used to cut the semiconductor structure 305 on the semiconductor substrate 301;

[0045] In an optional embodiment of the present invention, the cutting pattern is a coarse cutting pattern 202. The coarse cutting pattern 202 is used to cut multiple semiconductor structures 305 on the semiconductor substrate 301. It is used for the FinCoarse Cut (FCC) process of semiconductor structure 305. The FCC process can cut multiple semiconductor structures 305, including lateral cuts parallel to the semiconductor structure 305 and longitudinal cuts perpendicular to the semiconductor structure 305. Usually, the FCC process is performed first, followed by the FCC process.

[0046] In one optional embodiment of the present invention, the coarse cutting pattern 202 is used to truncate the two sides of the multiple semiconductor structures 305.

[0047] In an optional embodiment of the present invention, the cutting pattern is a fine cutting pattern 203, which is used to cut a single semiconductor structure 305 on the semiconductor substrate 301. It is used for the Fin Fine Cut (FFC) process of semiconductor structure 305, which is fine enough to cut a single semiconductor structure 305.

[0048] In one optional embodiment of the present invention, the finely cut pattern 203 has at least two different lengths, that is, different lengths are cut off on the semiconductor structure 305.

[0049] In one optional embodiment of the present invention, the FFC process is typically performed first, followed by the FCC process.

[0050] In one optional embodiment of the present invention, the semiconductor structures 305 are distributed sequentially at equal intervals.

[0051] The first photomask pattern is used to define the first and second measurement regions on the semiconductor substrate 301. A core structure is formed on the first measurement region A1, and no core structure is formed on the second measurement region A2. The core structure is formed on the sacrificial layer.

[0052] The second photomask pattern is used to define the location of the protective layer formation on the second measurement area A2 after the sacrificial layer is removed.

[0053] In one optional embodiment of the present invention, the protective layer is a photoresist layer.

[0054] In one optional embodiment of the present invention, the protective layer covers at least one side of the sidewall structure 303, specifically, the protective layer may be formed to cover a portion of the edge of one side of the sidewall structure 303.

[0055] This invention also provides a method for using a layout structure that simultaneously monitors critical dimensions and etching roughness, comprising:

[0056] Step 1: Provide a substrate 301, on which a stack 302 is formed;

[0057] In an optional embodiment of the present invention, the substrate 301 in step one is a silicon substrate.

[0058] In an optional embodiment of the present invention, the stack 302 in step one is composed of a first oxide layer, a nitride layer and a second oxide layer stacked sequentially from bottom to top. The material of the first oxide layer is usually silicon dioxide, the material of the nitride layer is usually silicon nitride, and the material of the second oxide layer is usually silicon dioxide.

[0059] In one optional embodiment of the present invention, the material of the sacrificial layer in step one is amorphous silicon.

[0060] Step 2: A sacrificial layer is formed on the stacked layer 302. Then, the etching area of ​​the sacrificial layer is defined by photolithography using the first photomask pattern, so that a core structure is formed on the sacrificial layer in the first measurement area A1, and no core structure is formed on the sacrificial layer in the second measurement area. Then, the remaining first photoresist layer is removed, and sidewall 303 structures are formed on both sides of each core structure. Then, the core structure and the sacrificial layer are removed. The sidewall 303 structure is used as a mask to etch the stacked layer 302 and the substrate below it to form a semiconductor structure 305.

[0061] In an optional embodiment of the present invention, the material of the sidewall structure 303 in step two is silicon dioxide or silicon nitride.

[0062] Step 3: Form a first photoresist layer covering the first and second measurement areas, and pattern the second photoresist layer using a photomask pattern including the second photomask pattern, so that the second photoresist layer on the second measurement area A2 is retained, and the second photoresist layer on the first measurement area A1 is removed, so that the sidewall 303 structure and the stack 302 below it are exposed.

[0063] Step 4: Using the sidewall 303 structure as a mask, etch the exposed stacked layer 302 and substrate 301 in the first measurement region A1 to form a semiconductor structure 305. In the second measurement region A2, no semiconductor structure 305 is formed on the stacked layer 302 and substrate 301.

[0064] Step 5: Remove the remaining second photoresist layer and sidewall 303 structure;

[0065] Step 6: Form a third photoresist layer covering the sidewall 303 structure and the remaining stack 302. Use a photomask containing the cutting pattern to open the third photoresist layer to define the etching area. Then etch the semiconductor structure 305 and the stack 306 to cut off part of the semiconductor structure 305. Form measurement grooves 307 on the stack 306 where the semiconductor structure 305 is not formed and on the substrate 301 (second measurement area A2) below it, as well as on the semiconductor structure 305 (first measurement area A1).

[0066] In an optional embodiment of the present invention, in step six, multiple semiconductor structures 305 on the semiconductor substrate 301 are truncated.

[0067] In an optional embodiment of the present invention, step six involves truncating a single semiconductor structure 305 on the semiconductor substrate 301.

[0068] In one optional embodiment of the present invention, the FFC process is usually performed first, followed by the FCC process. That is, after multiple semiconductor structures 305 on the semiconductor substrate 301 are cut off, a single semiconductor structure 305 on the semiconductor substrate 301 is then cut off.

[0069] Step 7: Use the measuring groove 307 to obtain the critical dimensions and etching roughness after etching.

[0070] In an optional embodiment of the present invention, in step seven, the etching process of the semiconductor structure 305 and the measurement groove 307 is measured using a critical size scanning electron microscope to obtain the critical dimensions and etching roughness after etching.

[0071] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0072] In summary, this invention covers part of the sidewall structure on a semiconductor substrate by adding a photomask. During subsequent etching using the sidewalls as a mask, no semiconductor structure forms on the covered area of ​​the semiconductor substrate and the hard mask layer. When the semiconductor structure is cut off, an etching pattern is formed on the semiconductor substrate and the hard mask layer in the area where the semiconductor structure was not formed, allowing for monitoring of critical dimensions and etching roughness after etching. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0073] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for using a layout structure that simultaneously monitors critical dimensions and etching roughness, characterized in that, include: Step 1: Provide a substrate on which a stack of layers is formed; Step 2: A sacrificial layer is formed on the stacked layers, and a first photoresist layer is formed on the sacrificial layer. Then, the first photoresist layer is patterned using a first photomask pattern through a photolithography process to define the etching region of the sacrificial layer, so that a core structure is formed on the sacrificial layer in the first measurement region, and no core structure is formed on the sacrificial layer in the second measurement region. Then, the remaining first photoresist layer is removed, and sidewalls are formed on both sides of each core structure. Then, the core structure and the sacrificial layer are removed. The sidewalls are used as masks to etch the stacked layers and the substrate below to form a semiconductor structure. Step 3: Form a second photoresist layer covering the first and second measurement areas. Pattern the second photoresist layer using a photomask pattern including the second photomask pattern, so that the second photoresist layer on the second measurement area is retained, and the second photoresist layer on the first measurement area is removed, so that the sidewalls and the stack below are exposed. Step 4: Using the sidewall as a mask, etch the exposed stack and the substrate to form the semiconductor structure. The semiconductor structure is not formed on the stack and the substrate in the second measurement region. Step 5: Remove the remaining second photoresist layer and the sidewalls; Step 6: Form a third photoresist layer covering the remaining stacked layers. Use a photomask containing a cutting pattern to open the third photoresist layer to define the etching area. Then etch the semiconductor structure and the stacked layers to cut off a portion of the semiconductor structure. Form measurement grooves on the stacked layers where the semiconductor structure is not formed, on the substrate below them, and on the semiconductor structure. Step 7: Use the measurement groove to obtain the key dimensions and etching roughness after etching.

2. The method for using a layout structure that simultaneously monitors critical dimensions and etching roughness according to claim 1, characterized in that: The substrate mentioned in step one is a silicon substrate.

3. The method for using a layout structure that simultaneously monitors critical dimensions and etching roughness according to claim 1, characterized in that: The stacked layers in step one consist of a first oxide layer, a nitrided layer, and a second oxide layer stacked sequentially from bottom to top.

4. The method for using a layout structure that simultaneously monitors critical dimensions and etching roughness according to claim 1, characterized in that: The sidewall material in step two is silicon dioxide or silicon nitride.

5. The method for using a layout structure that simultaneously monitors critical dimensions and etching roughness according to claim 1, characterized in that: In step six, the multiple semiconductor structures on the substrate are truncated.

6. The method for using a layout structure that simultaneously monitors critical dimensions and etching roughness according to claim 1, characterized in that: In step six, the single semiconductor structure on the substrate is truncated.

7. The method for using a layout structure that simultaneously monitors critical dimensions and etching roughness according to claim 1, characterized in that: In step seven, the etching process of the semiconductor structure and the measurement groove is measured using a critical size scanning electron microscope to obtain the critical dimensions and the etching roughness after etching.

8. A layout structure for simultaneously monitoring critical dimensions and etching roughness, used in the method of use as described in any one of claims 1-7, characterized in that, include: The mandrel pattern is used to define the location where the mandrel structure is formed on the substrate, and the mandrel structure is used to define the location where the sidewall is formed. The sidewall is used as a mask during etching to form a semiconductor structure on the substrate. A cutting pattern, the cutting pattern being used to truncate a portion of the semiconductor structure on the substrate; A first photomask pattern is used to define a first and a second measurement region on the substrate. A mandrel structure is formed on the first measurement region, but the mandrel structure is not formed on the second measurement region. The mandrel structure is formed on a sacrificial layer. The second photomask pattern is used to define the location where the protective layer is formed on the second measurement area after the sacrificial layer is removed.

9. The layout structure for simultaneously monitoring critical dimensions and etching roughness according to claim 8, characterized in that: The cutting pattern is a coarse cutting pattern, which is used to cut off multiple semiconductor structures on the substrate.

10. The layout structure for simultaneously monitoring critical dimensions and etching roughness according to claim 9, characterized in that: The coarse cutting pattern is used to truncate the two sides of multiple semiconductor structures.

11. The layout structure for simultaneously monitoring critical dimensions and etching roughness according to claim 8, characterized in that: The semiconductor structures are distributed sequentially at equal intervals.

12. The layout structure for simultaneously monitoring critical dimensions and etching roughness according to claim 8, characterized in that: The cutting pattern is a fine cutting pattern, which is used to cut off a single semiconductor structure portion on the substrate.

13. The layout structure for simultaneously monitoring critical dimensions and etching roughness according to claim 12, characterized in that: The precision-cut pattern has at least two different lengths.

14. The layout structure for simultaneously monitoring critical dimensions and etching roughness according to claim 8, characterized in that: The protective layer is a photoresist layer.

15. The layout structure for simultaneously monitoring critical dimensions and etching roughness according to claim 8, characterized in that: The protective layer covers an area on at least one side of the sidewall.

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