Semiconductor structure and preparation method thereof
By forming a groove between the second isolation layer and the active area and using a barrier layer with a low etching rate, the problem of leakage current caused by the easy loss of the shallow trench isolation structure is solved, and the performance of the semiconductor structure is improved.
Patent Information
- Application Number
- CN202110833194.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-07-22
- Publication Date
- 2025-09-19
- Estimated Expiration
- 2041-07-22
AI Technical Summary
In the prior art, shallow trench isolation structures between adjacent active regions are easily missing, which increases the risk of leakage current and reduces the performance of the semiconductor structure.
A groove is formed between the second isolation layer and the active area, and a barrier layer with a low etching rate is formed in the groove. The low etching rate of the barrier layer is used to prevent the isolation structure from being damaged during subsequent etching processes, thereby avoiding leakage current between adjacent active areas.
This effectively avoids leakage current between adjacent active areas, improves the performance of the semiconductor structure, and prevents the isolation structure from being lost during the etching process.
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Figure CN115692306B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art
[0002] Shallow trench isolation (STI) is widely used in semiconductor structures to isolate adjacent active regions.
[0003] In the related art, a trench is usually formed in a substrate first, and then an isolation dielectric is filled in the trench using a deposition process to form a shallow trench isolation structure.
[0004] However, when other devices are subsequently fabricated on the substrate, the isolation dielectric in the contact area with the active area may be lost, resulting in a gap between the active area and the semiconductor structure. This gap may increase the risk of leakage between adjacent active areas and reduce the performance of the semiconductor structure. Summary of the Invention
[0005] In view of the above problems, embodiments of the present application provide a semiconductor structure and a method for manufacturing the same, which are used to avoid leakage current between adjacent active regions and improve the performance of the semiconductor structure.
[0006] In order to achieve the above objectives, the embodiments of the present application provide the following technical solutions:
[0007] A first aspect of an embodiment of the present application provides a method for preparing a semiconductor structure, comprising the following steps:
[0008] Providing a substrate, wherein the substrate has a groove therein, and the area of the substrate excluding the groove constitutes a plurality of active areas arranged at intervals;
[0009] forming a first isolation layer and a second isolation layer stacked in sequence on an inner wall of the trench, wherein a top surface of the first isolation layer is lower than a top surface of the second isolation layer, so that a groove is formed between the second isolation layer and the active area, and the second isolation layer forms an intermediate trench in the trench;
[0010] forming a barrier layer in the groove, wherein an etching rate of the barrier layer is lower than an etching rate of the first isolation layer;
[0011] A third isolation layer is formed in the middle trench, and the third isolation layer completely fills the middle trench. The first isolation layer, the second isolation layer, the third isolation layer and the barrier layer constitute an isolation structure.
[0012] In the method for preparing the semiconductor structure as described above, the barrier layer further has an extension portion, and the extension portion is located between the second isolation layer and the third isolation layer.
[0013] In the method for preparing the semiconductor structure as described above, the material of the barrier layer includes at least one of silicon carbonitride, silicon oxycarbide and silicon boronitride.
[0014] In the method for preparing the semiconductor structure as described above, the depth of the groove is 60 nm to 80 nm.
[0015] The method for manufacturing the semiconductor structure as described above, wherein the step of forming a first isolation layer and a second isolation layer stacked in sequence on the inner wall of the trench comprises:
[0016] forming a first initial isolation layer on the inner wall of the trench, wherein the first initial isolation layer covers the top surface of the substrate;
[0017] forming a second initial isolation layer on the first initial isolation layer;
[0018] The first initial isolation layer on the top surface of the substrate and a portion of the first initial isolation layer on the side wall of the groove are removed, and the second initial isolation layer on the top surface of the substrate is removed. The retained first initial isolation layer constitutes a first isolation layer, and the retained second initial isolation layer constitutes a second isolation layer.
[0019] The method for preparing the semiconductor structure as described above, wherein the steps of removing the first initial isolation layer located on the top surface of the substrate and a portion of the first initial isolation layer located on the sidewalls of the trench, and removing the second initial isolation layer located on the top surface of the substrate, further include:
[0020] A portion of the thickness of the active area is removed, and a filling area is formed between the remaining active area and the barrier layer.
[0021] In the method for preparing the semiconductor structure as described above, the step of forming a barrier layer in the groove comprises:
[0022] forming an initial barrier layer in the groove, wherein the initial barrier layer extends outside the groove and covers the top surface of the active region and the inner wall of the second isolation layer;
[0023] The initial barrier layer on the top surface of the active region is removed, the initial barrier layer remaining in the groove constitutes a barrier layer, and the initial barrier layer remaining on the inner wall of the second isolation layer constitutes an extension portion.
[0024] In the method for manufacturing the semiconductor structure as described above, the step of forming the third isolation layer in the middle trench comprises:
[0025] forming a third initial isolation layer in the middle trench, wherein the third initial isolation layer extends outside the middle trench and covers the top surfaces of the second isolation layer and the barrier layer and the filling region;
[0026] The third initial isolation layer is planarized so that the third initial isolation layer located in the middle trench constitutes a third isolation layer, the third initial isolation layer located in the filling region constitutes a gate oxide layer, and the top surface of the gate oxide layer is flush with the top surface of the barrier layer.
[0027] The method for preparing the semiconductor structure as described above, wherein, after the step of planarizing the third initial isolation layer, the method further comprises:
[0028] A gate structure and an insulating layer are formed on the gate oxide layer and are stacked in sequence.
[0029] A second aspect of the embodiments of the present application provides a semiconductor structure comprising: a substrate having a trench therein, wherein a region of the substrate excluding the trench constitutes a plurality of active regions spaced apart;
[0030] a first isolation layer, the first isolation layer being disposed on an inner wall of the trench;
[0031] a second isolation layer, the second isolation layer being disposed on the first isolation layer, and a top surface of the second isolation layer being higher than a top surface of the first isolation layer, so that the second isolation layer and the substrate form a groove;
[0032] a barrier layer, the barrier layer being disposed in the groove and having an etching rate lower than an etching rate of the first isolation layer;
[0033] A third isolation layer is provided on the inner wall of the second isolation layer, and the third isolation layer completely fills the area surrounded by the second isolation layer.
[0034] In the semiconductor structure as described above, the material of the barrier layer includes at least one of silicon carbonitride, silicon oxycarbide and silicon boronitride.
[0035] In the semiconductor structure as described above, the barrier layer includes an extension portion, and the extension portion is located between the second isolation layer and the third isolation layer.
[0036] In the semiconductor structure described above, the top surface of the barrier layer is higher than the top surface of the active area; and a gate oxide layer is provided in the area enclosed by the barrier layer and the active area.
[0037] The semiconductor structure as described above further includes a gate structure and an insulating layer. The gate structure includes a first conductive layer and a second conductive layer stacked in sequence. The first conductive layer is arranged on the gate oxide layer, and the insulating layer is arranged on the second conductive layer.
[0038] In the semiconductor structure described above, the material of the first isolation layer and the material of the third isolation layer both include silicon oxide, and the material of the second isolation layer includes silicon nitride.
[0039] In the semiconductor structure and preparation method provided in the embodiments of the present application, a groove is formed between the second isolation layer and the active area, and a barrier layer is formed in the groove. The etching rate of the barrier layer is lower than the etching rate of the first isolation layer. When other film layers located on the substrate are subsequently etched and removed, the barrier layer will not be over-etched, and the isolation structure will not be lost. This can avoid leakage current between adjacent active areas and improve the performance of the semiconductor structure.
[0040] In addition to the technical problems solved by the embodiments of the present application, the technical features that constitute the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the semiconductor structure and the preparation method thereof provided by the embodiments of the present application, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS
[0041] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0042] Figure 1 Schematic diagram of the structure of the substrate in the related art;
[0043] Figure 2 It is a schematic diagram of the structure of forming a dielectric layer in the related art;
[0044] Figure 3 A schematic diagram of a structure in which a dielectric layer is removed in the related art;
[0045] Figure 4 A process flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present application;
[0046] Figure 5 A schematic diagram of a structure for forming a trench in a method for preparing a semiconductor structure provided in an embodiment of the present application;
[0047] Figure 6 A schematic structural diagram of forming a first initial isolation layer in a method for preparing a semiconductor structure provided in an embodiment of the present application;
[0048] Figure 7 A schematic structural diagram of forming a second initial isolation layer in the method for preparing a semiconductor structure provided in an embodiment of the present application;
[0049] Figure 8 This is a process diagram of forming a first isolation layer and a second isolation layer in a method for preparing a semiconductor structure provided by an embodiment of the present application;
[0050] Figure 9 A schematic structural diagram of forming a first isolation layer and a second isolation layer in a method for preparing a semiconductor structure provided in an embodiment of the present application;
[0051] Figure 10 A schematic diagram of the structure of forming an initial barrier layer in the method for preparing a semiconductor structure provided in an embodiment of the present application;
[0052] Figure 11 A schematic diagram of a structure for forming a barrier layer and an extension portion in a method for preparing a semiconductor structure provided in an embodiment of the present application;
[0053] Figure 12 A schematic structural diagram of forming a third initial isolation layer in the method for preparing a semiconductor structure provided in an embodiment of the present application;
[0054] Figure 13 A schematic structural diagram of forming a third isolation layer and a gate oxide layer in the method for preparing a semiconductor structure provided in an embodiment of the present application;
[0055] Figure 14 A schematic diagram of the structure of forming a dielectric layer in the method for preparing a semiconductor structure provided in an embodiment of the present application;
[0056] Figure 15 A schematic structural diagram of forming a gate structure and an insulating layer in a method for preparing a semiconductor structure provided in an embodiment of the present application.
[0057] Reference numerals:
[0058] 10: substrate; 11: active area; 12: shallow trench isolation structure; 13: trench; 20: isolation structure; 21: first isolation layer; 211: first initial isolation layer; 22: second isolation layer; 221: second initial isolation layer; 23: barrier layer; 231: extension; 232: initial barrier layer; 24: third isolation layer; 241: third initial isolation layer; 30: middle trench; 40: groove; 50: filling region; 60: gate oxide layer; 70: dielectric layer; 80: gate structure; 81: first conductive layer; 82: second conductive layer; 90: insulating layer. DETAILED DESCRIPTION
[0059] As described in the background technology, current leakage will occur between adjacent active areas of the semiconductor structure in the related technology. The reason for this problem is that the shallow trench isolation structure between adjacent active areas is prone to missing, and the voltage applied to a certain active area may be applied to the adjacent active area, causing leakage current between adjacent active areas.
[0060] The inventors have found that the shallow trench isolation structure between adjacent active areas is easily missing because: the semiconductor structure generally includes an array area and a peripheral circuit area connected to the array area, such as Figures 1 to 3 As shown, the array area and the peripheral circuit area both include a substrate 10 and a shallow trench isolation structure 12 arranged in the substrate 10. When bit lines and isolation sidewalls arranged on both sides of the bit lines are formed on the array area, the film layer of the isolation sidewalls will also be formed on the peripheral circuit area. When the control circuit is formed on the peripheral circuit area, the dielectric layer 70 on the substrate 10 in the peripheral circuit area needs to be removed. However, in the process of removing the dielectric layer 70, the shallow trench isolation structure 12 in the peripheral circuit area is easily over-etched, resulting in the loss of the shallow trench isolation structure 12, which is likely to cause leakage current between adjacent active areas 11.
[0061] In response to the above-mentioned technical problems, in an embodiment of the present application, a groove is formed between the second isolation layer and the active area, and a barrier layer is formed in the groove. The etching rate of the barrier layer is lower than the etching rate of the first isolation layer. When other film layers located on the substrate are subsequently etched and removed, the barrier layer will not be over-etched, and the isolation structure will not be lost. This can avoid leakage current between adjacent active areas and improve the performance of the semiconductor structure.
[0062] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.
[0063] Figure 4 This is a flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present application. Figure 4-Figure 15 The schematic diagram of each stage of the semiconductor structure preparation method is shown below. Figure 4-Figure 15 The preparation method of semiconductor structure is introduced in detail.
[0064] This embodiment does not limit the semiconductor structure. The semiconductor structure will be described below using a dynamic random access memory (DRAM) as an example, but this embodiment is not limited thereto. The semiconductor structure in this embodiment may also be other structures.
[0065] like Figure 4 As shown, the method for preparing a semiconductor structure provided in an embodiment of the present application includes the following steps:
[0066] Step S100: providing a substrate, wherein a trench is formed in the substrate, and a plurality of active regions are formed in the substrate except for the trench.
[0067] For example, Figure 5 As shown, the substrate 10 serves as a supporting component of the dynamic random access memory, and is used to support other components arranged thereon, wherein the substrate 10 can be made of a semiconductor material, and the semiconductor material can be one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbon compounds.
[0068] The substrate 10 has a groove 13 therein. The groove 13 is used to separate the substrate 10 into a plurality of independent active regions 11 . The plurality of active regions 11 may be arranged in an array in the substrate 10 .
[0069] The active area 11 can be used to form semiconductor devices. For example, the active area 11 formed in the array area is used to form semiconductor devices such as transistors or capacitors. For another example, the active area 11 formed in the peripheral circuit area is used to form a control circuit, such as a logic transistor.
[0070] It should be noted that Figure 5 Only the active area in the peripheral circuit area is shown, and the active area 11 in the array area is not shown.
[0071] Step S200: forming a first isolation layer and a second isolation layer stacked in sequence on the inner wall of the trench, wherein the top surface of the first isolation layer is lower than the top surface of the second isolation layer, so that a groove is formed between the second isolation layer and the active area, and the second isolation layer forms a middle trench in the trench.
[0072] For example, Figure 6 As shown, a first initial isolation layer 211 may be formed on the inner wall of the trench 13 by using an atomic layer deposition process. The first initial isolation layer 211 covers the top surface of the substrate 10 .
[0073] like Figure 7 As shown, after the first initial isolation layer 211 is formed, the second initial isolation layer 221 may be formed on the first initial isolation layer 211 by continuously using an atomic layer deposition process.
[0074] Afterwards, the first initial isolation layer 211 located on the top surface of the substrate 10 and part of the first initial isolation layer 211 located on the side wall of the groove are removed, and the second initial isolation layer 221 located on the top surface of the substrate is removed. The retained first initial isolation layer 211 constitutes the first isolation layer 21, and the retained second initial isolation layer 221 constitutes the second isolation layer 22, and the second isolation layer 22 forms an intermediate groove 30 in the groove 13.
[0075] Specifically, such as Figure 8 As shown, the second initial isolation layer 221 on the top surface of the substrate 10 can be removed by etching gas or etching liquid to expose the first initial isolation layer 211 on the substrate 10 , and the retained second initial isolation layer 221 constitutes the second isolation layer 22 .
[0076] After the second isolation layer 22 is formed, Figure 9 As shown, the first initial isolation layer 211 on the top surface of the substrate 10 and a portion of the first initial isolation layer 211 on the sidewall of the trench are removed by etching gas or etching liquid, so that a groove 40 is formed between the second isolation layer 22 and the substrate 10.
[0077] If the depth of the groove is less than 60nm, the thickness of the barrier layer subsequently formed in the groove is too small to prevent the first isolation layer from being over-etched. If the depth of the groove is greater than 80nm, the depth of the groove is too large, and the second isolation layer is etched during the process of forming the groove, affecting the performance of the semiconductor structure. Therefore, this embodiment sets the depth of the groove to 60nm~80nm, which can prevent the first isolation layer from being over-etched and ensure the performance of the semiconductor structure.
[0078] In this embodiment, the material of the first isolation layer includes silicon oxide, and the material of the second isolation layer includes silicon nitride.
[0079] Step S300: forming a barrier layer in the groove, wherein the etching rate of the barrier layer is lower than the etching rate of the first isolation layer.
[0080] For example, Figure 10 As shown, an initial barrier layer 232 is formed in the groove 40 . The initial barrier layer 232 extends out of the groove 40 and covers the top surface of the active region 11 and the inner wall of the second isolation layer 22 .
[0081] like Figure 11 As shown, the initial barrier layer 232 located on the top surface of the active area 11 is removed, and the initial barrier layer 232 remaining in the groove 40 constitutes the barrier layer 23, and the initial barrier layer 232 remaining on the inner wall of the second isolation layer 22 constitutes the extension portion 231, that is, the extension portion 231 is located between the second isolation layer 22 and the third isolation layer.
[0082] This embodiment utilizes that the etching rate of the barrier layer 23 is lower than that of the first isolation layer 21 , that is, under the same etching conditions, the barrier layer 23 will not be etched, thereby preventing the first isolation layer from being etched.
[0083] In addition, this embodiment can reduce the thickness of the third isolation layer 24 by setting the extension portion 231. By replacing part of the third isolation layer 24 with the extension portion 231 with a lower etching rate, the damage to the isolation structure 20 when other film layers located on the substrate are subsequently removed can be minimized, leakage current between adjacent active areas can be avoided, and the performance of the semiconductor structure can be improved.
[0084] It should be noted that the extension portion in this embodiment may also be provided only on the side wall of the middle groove, or only on the bottom wall of the middle groove, or the extension portion may be provided on both the side wall and the bottom wall of the middle groove.
[0085] The material of the barrier layer 23 includes at least one of silicon carbonitride, silicon oxycarbide and silicon boronitride. That is, the material of the barrier layer 23 can be one or more of the above three materials.
[0086] Step S400: forming a third isolation layer in the middle trench, wherein the third isolation layer completely fills the middle trench. The first isolation layer, the second isolation layer, the third isolation layer and the barrier layer constitute an isolation structure.
[0087] For example, Figure 13 As shown, a third isolation layer 24 can be formed in the middle trench 30 using a physical vapor deposition process or a chemical vapor deposition process. The third isolation layer 24 fills the middle trench 30. The first isolation layer 21, the second isolation layer 22, the third isolation layer 24 and the barrier layer 23 constitute the isolation structure 20.
[0088] In some embodiments, continue to refer to Figure 9 and Figure 11 When removing the first initial isolation layer 211 located on the top surface of the substrate 10 and a portion of the first initial isolation layer 211 located on the side wall of the trench 13, and removing the second initial isolation layer 221 located on the top surface of the substrate 10, a portion of the thickness of the active area 11 will also be removed, and a filling area 50 will be formed between the retained active area 11 and the barrier layer 23.
[0089] When forming the third isolation layer, the third isolation layer is also formed in the filling region 50. For example, Figure 12 As shown, a third initial isolation layer 241 is formed in the middle trench 30 . The third initial isolation layer 241 extends outside the middle trench 30 and covers the second isolation layer 22 , the barrier layer 23 and the filling region 50 .
[0090] like Figure 13 As shown, the third initial isolation layer is planarized using a chemical mechanical polishing process, so that the third initial isolation layer 241 located in the middle trench 30 constitutes the third isolation layer 24, and the third initial isolation layer 241 located in the filling area 50 constitutes the gate oxide layer 60, and the top surface of the gate oxide layer 60 is flush with the top surface of the barrier layer 23.
[0091] In this embodiment, by using the third isolation layer formed in the filling region as the gate oxide layer, it is possible to avoid the subsequent formation of a gate oxide layer on the active region, thereby simplifying the manufacturing process of the semiconductor structure.
[0092] When the bit lines and the isolation sidewalls on both sides of the bit lines are formed on the array area, the film layer of the isolation sidewalls is also formed on the peripheral circuit area, so as to form the dielectric layer 70 on the substrate 10 in the peripheral circuit area. Figure 14 As shown, when forming a control circuit on the peripheral circuit area, it is necessary to remove the dielectric layer 70 on the substrate 10 located in the peripheral circuit area. In this embodiment, an etching gas is used to remove the dielectric layer 70. Since the isolation structure in this embodiment includes a barrier layer 23 with a low etching rate, when removing the dielectric layer 70, the barrier layer 23 will not be over-etched, and thus the isolation structure 20 will not be over-etched, thereby avoiding the phenomenon of leakage current between adjacent active areas 11 and improving the performance of the semiconductor structure.
[0093] In some embodiments, as Figure 15 As shown, after the step of planarizing the third initial isolation layer 241, the method for preparing the semiconductor structure further includes: forming a gate structure 80 and an insulating layer 90 stacked in sequence on the gate oxide layer 60, and the gate oxide layer 60, the gate structure 80 and the insulating layer 90 constitute a transistor.
[0094] Continue to refer Figure 15The embodiment of the present application further provides a semiconductor structure, including: a substrate 10, a first isolation layer 21, a second isolation layer 22, a barrier layer 23 and a third isolation layer 24.
[0095] The substrate 10 has a trench therein, and the area of the substrate 10 excluding the trench forms a plurality of spaced active areas. A first isolation layer 21 is disposed on the inner wall of the trench, and a second isolation layer 22 is disposed on the first isolation layer 21. The top surface of the second isolation layer 22 is higher than the top surface of the first isolation layer 21, so that the second isolation layer 22 and the substrate 10 form a groove.
[0096] The barrier layer 23 is disposed in the groove, and an etching rate of the barrier layer 23 is lower than an etching rate of the first isolation layer 21 .
[0097] The third isolation layer 24 is disposed on the inner wall of the second isolation layer 22 , and the third isolation layer 24 completely fills the area surrounded by the second isolation layer 22 .
[0098] That is to say, the isolation structure 20 includes a first isolation layer 21, a second isolation layer 22, a barrier layer 23 and a third isolation layer 24. The first isolation layer 21, the second isolation layer 22 and the third isolation layer 23 are stacked in sequence, and the top surface of the first isolation layer 21 is lower than the top surface of the substrate 10. A groove is formed between the second isolation layer 22 and the substrate 10. The barrier layer 23 is arranged in the groove and fills the groove. The etching rate of the barrier layer 23 is lower than the etching rate of the first isolation layer 21.
[0099] The material of the barrier layer 23 includes at least one of silicon carbonitride, silicon oxycarbide and silicon boronitride. That is, the material of the barrier layer 23 can be one or more of the above three materials.
[0100] The material of the first isolation layer 21 and the material of the third isolation layer 24 may both include silicon oxide, and the material of the second isolation layer 22 may include silicon nitride.
[0101] In this embodiment, the etching rate of the barrier layer 23 is lower than the etching rate of the first isolation layer 21. In this way, when forming the isolation structure, the barrier layer will not be damaged, and the isolation structure will not be damaged, thereby avoiding leakage current between adjacent active areas and improving the performance of the semiconductor structure.
[0102] In some embodiments, the barrier layer 23 further includes an extension portion 231 , and the extension portion 231 is located between the second isolation layer 22 and the third isolation layer 24 .
[0103] This embodiment can also reduce the thickness of the third isolation layer 24 by setting the extension portion 231. By replacing part of the third isolation layer 24 with the extension portion 231 with a lower etching rate, damage to the isolation structure 20 when other film layers located on the substrate are subsequently removed can be minimized, leakage current between adjacent active areas can be avoided, and the performance of the semiconductor structure can be improved.
[0104] In some embodiments, a top surface of the barrier layer 23 is higher than a top surface of the active region 11 , and a gate oxide layer 60 is disposed in the region enclosed by the barrier layer 23 and the active region 11 .
[0105] In this embodiment, by forming the gate oxide layer simultaneously with the formation of the third isolation layer, it is possible to avoid the need to re-form the gate oxide layer on the active region, thereby simplifying the manufacturing process of the semiconductor structure.
[0106] The gate oxide layer 60 is also provided with a gate structure 80 and an insulating layer 90, wherein the gate structure 80 may include a first conductive layer 81 and a second conductive layer 82 stacked in sequence, the first conductive layer 81 is provided on the gate oxide layer 60, and the insulating layer 90 is provided on the second conductive layer 82. The gate oxide layer 60, the gate structure 80 and the insulating layer 90 constitute a transistor, which is used to control the semiconductor device located in the array area.
[0107] The material of the first conductive layer 81 may include polysilicon, the material of the second conductive layer 82 may include tungsten, and the material of the insulating layer 90 may include silicon nitride.
[0108] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.
[0109] In the description of this specification, reference to terms such as "one embodiment", "some embodiments", "illustrative embodiment", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application.
[0110] In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any suitable manner in any one or more embodiments or examples.
[0111] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A method for preparing a semiconductor structure, characterized in that: The steps include: Providing a substrate, wherein the substrate has a groove therein, and the area of the substrate excluding the groove constitutes a plurality of active areas arranged at intervals; forming a first isolation layer and a second isolation layer stacked in sequence on an inner wall of the trench, wherein a top surface of the first isolation layer is lower than a top surface of the second isolation layer, so that a groove is formed between the second isolation layer and the active area, and the second isolation layer forms an intermediate trench in the trench; forming a barrier layer in the groove, wherein an etching rate of the barrier layer is lower than an etching rate of the first isolation layer; A third isolation layer is formed in the middle trench, and the third isolation layer completely fills the middle trench. The first isolation layer, the second isolation layer, the third isolation layer and the barrier layer constitute an isolation structure.
2. The method for preparing a semiconductor structure according to claim 1, wherein: The barrier layer further has an extension portion, and the extension portion is located between the second isolation layer and the third isolation layer.
3. The method for preparing a semiconductor structure according to claim 2, wherein: The material of the barrier layer includes at least one of silicon carbonitride, silicon oxycarbide and silicon boronitride.
4. The method for preparing a semiconductor structure according to any one of claims 1 to 3, wherein: The depth of the groove is 60nm to 80nm.
5. The method for preparing a semiconductor structure according to claim 4, wherein: The step of forming a first isolation layer and a second isolation layer stacked in sequence on the inner wall of the trench comprises: forming a first initial isolation layer on the inner wall of the trench, wherein the first initial isolation layer covers the top surface of the substrate; forming a second initial isolation layer on the first initial isolation layer; The first initial isolation layer on the top surface of the substrate and a portion of the first initial isolation layer on the side wall of the groove are removed, and the second initial isolation layer on the top surface of the substrate is removed. The retained first initial isolation layer constitutes a first isolation layer, and the retained second initial isolation layer constitutes a second isolation layer.
6. The method for preparing a semiconductor structure according to claim 5, wherein: The steps of removing the first initial isolation layer on the top surface of the substrate and a portion of the first initial isolation layer on the sidewalls of the trench, and removing the second initial isolation layer on the top surface of the substrate further include: A portion of the thickness of the active area is removed, and a filling area is formed between the remaining active area and the barrier layer.
7. The method for preparing a semiconductor structure according to claim 6, wherein: The step of forming a barrier layer in the groove comprises: forming an initial barrier layer in the groove, wherein the initial barrier layer extends outside the groove and covers the top surface of the active region and the inner wall of the second isolation layer; The initial barrier layer on the top surface of the active region is removed, the initial barrier layer remaining in the groove constitutes a barrier layer, and the initial barrier layer remaining on the inner wall of the second isolation layer constitutes an extension portion.
8. The method for preparing a semiconductor structure according to claim 7, wherein: The step of forming a third isolation layer in the middle trench comprises: forming a third initial isolation layer in the middle trench, wherein the third initial isolation layer extends outside the middle trench and covers the top surfaces of the second isolation layer and the barrier layer and the filling region; The third initial isolation layer is planarized so that the third initial isolation layer located in the middle trench constitutes a third isolation layer, the third initial isolation layer located in the filling region constitutes a gate oxide layer, and the top surface of the gate oxide layer is flush with the top surface of the barrier layer.
9. The method for preparing a semiconductor structure according to claim 8, wherein: After the step of planarizing the third initial isolation layer, the preparation method further comprises: A gate structure and an insulating layer are formed on the gate oxide layer and are stacked in sequence.
10. A semiconductor structure, characterized in that include: A substrate having a groove therein, wherein the region of the substrate excluding the groove constitutes a plurality of active regions spaced apart from each other; a first isolation layer, the first isolation layer being disposed on an inner wall of the groove; a second isolation layer, the second isolation layer being disposed on the first isolation layer, and a top surface of the second isolation layer being higher than a top surface of the first isolation layer, so that the second isolation layer and the substrate form a groove; a barrier layer, the barrier layer being disposed in the groove and having an etching rate lower than an etching rate of the first isolation layer; A third isolation layer is provided on the inner wall of the second isolation layer, and the third isolation layer completely fills the area surrounded by the second isolation layer.
11. The semiconductor structure according to claim 10, wherein: The material of the barrier layer includes at least one of silicon carbonitride, silicon oxycarbide and silicon boronitride.
12. The semiconductor structure according to claim 10, wherein: The barrier layer includes an extension portion located between the second isolation layer and the third isolation layer.
13. The semiconductor structure according to claim 12, wherein: The top surface of the barrier layer is higher than the top surface of the active area; and a gate oxide layer is provided in the area enclosed by the barrier layer and the active area.
14. The semiconductor structure according to claim 13, wherein: It also includes a gate structure and an insulating layer. The gate structure includes a first conductive layer and a second conductive layer stacked in sequence. The first conductive layer is arranged on the gate oxide layer, and the insulating layer is arranged on the second conductive layer.
15. The semiconductor structure according to any one of claims 10 to 14, characterized in that: The material of the first isolation layer and the material of the third isolation layer both include silicon oxide, and the material of the second isolation layer includes silicon nitride.
Citation Information
Patent Citations
Trench isolation structure and forming method thereof
CN102468215A
Shallow trench isolation structure and preparation method thereof
CN110911342A