Power module and electronic device

Abstract

Embodiments of the present application relate to the technical field of semiconductor, and provide a power module and an electronic device. The power module comprises an insulating substrate and a half-bridge structure on the insulating substrate. The half-bridge structure comprises an upper half-bridge arm chip set, a lower half-bridge arm chip set, a plurality of positive direct current terminals, a plurality of negative direct current terminals and a plurality of alternating current terminals. The plurality of positive direct current terminals are electrically connected to the upper half-bridge arm chip set, the plurality of negative direct current terminals are electrically connected to the lower half-bridge arm chip set, and the plurality of alternating current terminals are respectively electrically connected to the upper half-bridge arm chip set and the lower half-bridge arm chip set. In a first direction, opposite sides of the upper half-bridge arm chip set are defined as a first side and a second side, the plurality of positive direct current terminals and the plurality of negative direct current terminals are located on the first side, and the plurality of alternating current terminals are located on the second side. In the first direction, the lower half-bridge arm chip set is located between the negative direct current terminal and the plurality of alternating current terminals.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a power module and an electronic device. Background Technology

[0002] Traditional power modules contain excessively high stray inductance, which can cause switching oscillations and power losses, thereby reducing the reliability of the power module. Summary of the Invention

[0003] A first aspect of this application provides a power module, the power module including an insulating substrate and a half-bridge structure located on the insulating substrate, the half-bridge structure including:

[0004] An upper half-bridge arm chipset and a lower half-bridge arm chipset, each comprising at least one switching transistor chip; and

[0005] Multiple positive DC terminals, multiple negative DC terminals, and multiple AC terminals;

[0006] The plurality of positive DC terminals are electrically connected to the upper half-bridge arm chipset, the plurality of negative DC terminals are electrically connected to the lower half-bridge arm chipset, and the plurality of AC terminals are electrically connected to the upper half-bridge arm chipset and the lower half-bridge arm chipset, respectively. Along a first direction, the opposite sides of the upper half-bridge arm chipset are defined as a first side and a second side, respectively. The plurality of positive DC terminals and the plurality of negative DC terminals are both located on the first side, and the plurality of AC terminals are located on the second side. Along the first direction, the lower half-bridge arm chipset is located between the negative DC terminals and the plurality of AC terminals.

[0007] The aforementioned power module provides multiple parallel commutation loops by incorporating multiple positive DC terminals, multiple negative DC terminals, and multiple AC terminals. The current in each loop is smaller compared to a half-bridge structure with only one positive DC terminal, one negative DC terminal, and one AC terminal, resulting in a smaller inductance. Furthermore, the power module features a structure where current flows in opposite directions within each commutation loop, using mutual inductance to offset some of the stray inductance in the loops, thereby reducing power module losses and improving reliability.

[0008] A second aspect of this application provides an electronic device that includes the power module described in the first aspect. Since this electronic device includes the aforementioned power module, it therefore possesses at least the same advantages as the power module, which will not be elaborated further here. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of the structure of a power module according to an embodiment of this application.

[0010] Figure 2 for Figure 1 The diagram shows the distribution of the conductive layer of the power module on the insulating substrate.

[0011] Figure 3 for Figure 1 The diagram shows the equivalent circuit of the power module.

[0012] Figure 4 This is a schematic diagram of the stray inductance simulation results of a power module according to an embodiment of this application.

[0013] Explanation of key component symbols:

[0014] Power Module 100

[0015] Insulating substrate 10

[0016] Half-bridge structure 20

[0017] First half-bridge structure 20a

[0018] Second half-bridge structure 20b

[0019] Third half-bridge structure 20c

[0020] Upper half-bridge chip 21

[0021] Lower half-bridge chip 22

[0022] Switching transistor chips C1, C2, C3, C4

[0023] Positive DC terminal 231

[0024] First source extreme component 232

[0025] AC terminal 233

[0026] First gate terminal 234

[0027] Second source extreme 235

[0028] Second gate terminal 236

[0029] Negative DC terminal 237

[0030] Thermistor terminal 238

[0031] Auxiliary terminal 239

[0032] DC positive conductive layer 31

[0033] First source conductive layer 32

[0034] AC conductive layer 33

[0035] First gate conductive layer 34

[0036] Second source conductive layer 35

[0037] Second gate conductive layer 36

[0038] DC negative electrode conductive layer 37

[0039] Thermistor conductive layer 38

[0040] First direction X

[0041] Second direction Y Detailed Implementation

[0042] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0043] Figure 1 This is a schematic diagram of the structure of a power module according to an embodiment of this application. Figure 1 As shown, the power module 100 includes an insulating substrate 10 and three half-bridge structures 20 spaced apart on the insulating substrate 10. The three half-bridge structures 20 are spaced apart along a second direction Y that intersects the first direction X. Figure 1 In the illustrated embodiment, the first direction X is perpendicular to the second direction Y. The three half-bridge structures 20 are a first half-bridge structure 20a, a second half-bridge structure 20b, and a third half-bridge structure 20c. The equivalent circuits of the first half-bridge structure 20a, the second half-bridge structure 20b, and the third half-bridge structure 20c are shown below. Figure 1 The first half-bridge structure 20a, the second half-bridge structure 20b, and the third half-bridge structure 20c have completely identical numbers and layouts of conductive layers, chips, and terminals. The following description uses the first half-bridge structure 20a as an example.

[0044] The first half-bridge structure 20a includes an upper half-bridge chip group 21, a lower half-bridge chip group 22, multiple positive DC terminals 231, multiple negative DC terminals 237, and multiple AC terminals 233. Both the upper half-bridge chip group 21 and the lower half-bridge chip group 22 include at least one switching transistor chip. The multiple positive DC terminals 231 are electrically connected to the upper half-bridge chip group 21. The multiple negative DC terminals 237 are electrically connected to the lower half-bridge chip group 22. The multiple AC terminals 233 are electrically connected to both the upper half-bridge chip group 21 and the lower half-bridge chip group 22. Along the first direction X, the two opposite sides of the upper half-bridge chip group 21 are defined as a first side and a second side, respectively. The multiple positive DC terminals 231 and the multiple negative DC terminals 237 are located on the first side, and the multiple AC terminals 233 are located on the second side. Along the first direction X, the lower half-bridge chip group 22 is located between the negative DC terminals 237 and the multiple AC terminals 233.

[0045] In this embodiment, the half-bridge structure 20 includes multiple positive DC terminals 231, multiple negative DC terminals 237, and multiple AC terminals 233, so that the switching transistor chips in the upper half-bridge chip group 21 and the lower half-bridge chip group 22 each have multiple parallel current loops. The current in each current loop is smaller than the current in the case where the half-bridge structure only includes one positive DC terminal, one negative DC terminal, and one AC terminal, and thus the inductance caused by the current is also smaller. Furthermore, in this embodiment, the current flow in the half-bridge structure 20 is from multiple positive DC terminals 231, the switching transistor chip in the upper half-bridge chip group 21, multiple AC terminals 233, the switching transistor chip in the lower half-bridge chip group 22, to multiple negative DC terminals 237. Due to the arrangement of the upper half-bridge chip group 21, lower half-bridge chip group 22, multiple positive DC terminals 231, multiple negative DC terminals 237, and multiple AC terminals 233 on the insulating substrate 10, the current flow in the half-bridge structure 20 is U-shaped (e.g., ...). Figure 1 As shown by the dashed line, the current flowing from the multiple positive DC terminals 231 to the upper half-bridge chip group 21 is in the first direction X negative direction, and the current flowing from the multiple AC terminals 233 and the switching transistor chip in the lower half-bridge chip group 22 to the multiple negative DC terminals 237 is in the first direction X positive direction. In this way, the inductance caused by the current in the first direction X negative direction and the current in the first direction X positive direction is canceled out, reducing the inductance in the equivalent power circuit, thereby reducing the loss of the power module 100.

[0046] Figure 1 In the embodiment shown, the plurality of positive DC terminals 231 are further away from the upper half-bridge chip group 21 than the plurality of negative DC terminals 237.

[0047] In some embodiments, the number of positive DC terminals 231, the number of negative DC terminals 237, and the number of AC terminals 233 are equal. This ensures that the current flowing through each terminal (including positive DC terminal 231, negative DC terminal 237, and AC terminal 233) is consistent or substantially the same.

[0048] In some embodiments, the number of each of the plurality of positive DC terminals 231, the plurality of negative DC terminals 237, and the plurality of AC terminals 233 is greater than or equal to 3 and less than or equal to 8. For example, the number of each of the three is 3, 4, 5, 6, 7, or 8. Specifically, Figure 1 In this embodiment, the number of positive DC terminals 231, negative DC terminals 237, and AC terminals 233 are all four. When the number of these three terminals is two, the effect of reducing stray inductance is not significant. Considering that the multiple terminals (including positive DC terminals 231, negative DC terminals 237, and AC terminals 233) are soldered to the conductive layer on the insulating substrate 10, and taking into account the size of the soldering nozzle, the area of ​​the conductive layer, and the distance between adjacent terminals, the number of each of the multiple positive DC terminals 231, multiple negative DC terminals 237, and multiple AC terminals 233 is no more than eight.

[0049] In some embodiments, the spacing between two adjacent positive DC terminals 231, the spacing between two adjacent negative DC terminals 237, and the spacing between two adjacent AC terminals 233 are all greater than or equal to 1 mm and less than or equal to 5 mm. Smaller spacing between adjacent positive DC terminals 231, adjacent negative DC terminals 237, and adjacent AC terminals 233 is more conducive to reducing stray inductance. However, the denser the terminal arrangement, the more difficult the packaging process of the package module becomes. Therefore, the spacing between at least two adjacent terminals is between 1 mm and 5 mm. For example, the spacing between two adjacent terminals is 1 mm, 2 mm, 2.5 mm, 3 mm, 3.5 mm, 4 mm, 4.5 mm, or 5 mm.

[0050] Figure 2 for Figure 1 The diagram shows the distribution of the conductive layer of the power module on the insulating substrate. Please refer to the attached diagram. Figure 1 and Figure 2 Each half-bridge structure 20 includes a DC positive conductive layer 31, a first source conductive layer 32, an AC conductive layer 33, a first gate conductive layer 34, a second source conductive layer 35, a second gate conductive layer 36, and a DC negative conductive layer 37, which are spaced apart on the surface of the insulating substrate 10.

[0051] In some embodiments, the insulating substrate 10 is a direct bond copper (DBC) ceramic substrate (e.g., a silicon nitride ceramic substrate). Both opposing surfaces of the insulating substrate 10 are copper layers. On one surface, the copper layer forms a DC positive conductive layer 31, a first source conductive layer 32, an AC conductive layer 33, a first gate conductive layer 34, a second source conductive layer 35, a second gate conductive layer 36, and a DC negative conductive layer 37. The copper layer on the other surface is used to electrically connect the insulating substrate 10 to other components (e.g., a heat sink) and to prevent warping of the ceramic substrate due to uneven stress on the opposing surfaces. The dimensions of the insulating substrate 10 are, for example, 48 mm × 54.5 mm, and its thickness is, for example, 0.32 mm. The thickness of the copper layers on the opposing surfaces of the insulating substrate 10 is, for example, 0.3 mm, but is not limited to these dimensions.

[0052] Specifically, the DC positive conductive layer 31 is approximately L-shaped. Multiple positive DC terminals 231 are located on the DC positive conductive layer 31 and are electrically connected to the DC positive conductive layer 31. Figure 1 In this configuration, four positive DC terminals 231 are arranged in an array of two rows and four columns at equal intervals, and are symmetrically distributed. Along the first direction X and the second direction Y, the distance between two adjacent positive DC terminals 231 is 3 mm. In other embodiments, the number, arrangement, and spacing of the positive DC terminals 231 are not limited to this.

[0053] The first source conductive layer 32 is located in the negative direction of the first direction X of the DC positive conductive layer 31 and is approximately L-shaped. The first source conductive layer 32 can be electrically connected to the DC positive conductive layer 31 via bonding wires (not shown). The first gate conductive layer 34 is adjacent to the first source conductive layer 32 and is located in the positive direction of the second direction Y of the first source conductive layer 32. The half-bridge structure 20 also includes a first source terminal 232 located on and electrically connected to the first source conductive layer 32, and a first gate terminal 234 located on and electrically connected to the first gate conductive layer 34. The first source terminal 232 is electrically connected to the first source conductive layer 32, for example, via bonding wires, and the first gate terminal 234 is electrically connected to the first gate conductive layer 34, for example, via bonding wires. The upper half-bridge chip assembly 21 is located on the first source conductive layer 32.

[0054] At least one switching transistor chip in the upper bridge arm chipset 21 is a plurality of parallel metal-oxide-semiconductor field-effect transistor (MOSFET) chips. Each MOSFET chip is mounted on the insulating substrate 10. Specifically, in the upper bridge arm chipset 21, the drain of each MOSFET chip is electrically connected to a plurality of positive DC terminals 231, the power source of each MOSFET chip is electrically connected to a plurality of AC terminals 233, the drive source of each MOSFET chip is electrically connected to the first source terminal 232 through an electrical connection to the first source conductive layer 32, and the gate of each MOSFET chip is electrically connected to the first gate terminal 234 through an electrical connection to the first gate conductive layer 34.

[0055] The AC conductive layer 33 is located in the negative direction of the first direction X between the first source conductive layer 32 and the first gate conductive layer 34, and is approximately rectangular. A plurality of AC terminals 233 are located on the AC conductive layer 33 and are electrically connected to the AC conductive layer 33. Figure 1 In the illustrated embodiment, the four AC terminals 233 are arranged in two rows and two columns, and are symmetrically arranged. Along the first direction X and the second direction Y, the spacing between two adjacent AC terminals 233 is 3 mm. In other embodiments, the number, arrangement, and spacing of the AC terminals 233 are not limited to this.

[0056] The second source conductive layer 35 is located between the DC negative conductive layer 37 and the first source conductive layer 32, and is electrically connected to the DC negative conductive layer 37. The second source conductive layer 35 is L-shaped. The second source conductive layer 35 can be electrically connected to the DC negative conductive layer 37 via bonding wires. The second gate conductive layer 36 is adjacent to the second source conductive layer 35 and is located in the positive direction of the second direction Y of the second source conductive layer 35. The half-bridge structure 20 also includes a second source terminal 235 located on and electrically connected to the second source conductive layer 35, and a second gate terminal 236 located on and electrically connected to the second gate conductive layer 36. The second source terminal 235 is electrically connected to the second source conductive layer 35, for example, via bonding wires, and the second gate terminal 236 is electrically connected to the second gate conductive layer 36, for example, via bonding wires.

[0057] The lower half-bridge chip group 22 is located on the second source conductive layer 35. At least one switching transistor chip in the lower half-bridge chip group 22 is a plurality of MOSFET chips connected in parallel. Each MOSFET chip is mounted on the insulating substrate 10. Specifically, in the lower half-bridge chip group 22, the drain of each MOSFET chip is electrically connected to a plurality of AC terminals 233, the power source of each MOSFET chip is electrically connected to a plurality of negative DC terminals 237, the drive source of each MOSFET chip is electrically connected to the second source terminal 235 through an electrical connection to the second source conductive layer 35, and the gate of each MOSFET chip is electrically connected to the second gate terminal 236 through an electrical connection to the second gate conductive layer 36.

[0058] The DC negative conductive layer 37 is located between the DC positive conductive layer 31 and the second source conductive layer 35, and is generally rectangular. A plurality of negative DC terminals 237 are located on the DC negative conductive layer 37 and are electrically connected to the DC negative conductive layer 37. Figure 1 In the illustrated embodiment, four negative DC terminals are provided. Along the first direction X and the second direction Y, the row or column spacing between two adjacent negative DC terminals 237 is 3 mm. In other embodiments, the number, arrangement, and spacing of the negative DC terminals 237 are not limited to this. Each half-bridge structure 20 also includes an auxiliary terminal 239, which is located on the DC negative conductive layer 37 and electrically connected to it.

[0059] Figure 1 In the illustrated embodiment, the upper bridge arm chipset 21 includes two MOSFET chips (i.e., switching chip C1 and switching chip C2). The lower bridge arm chipset 22 includes two MOSFET chips (i.e., switching chip C3 and switching chip C4). Each MOSFET chip is a silicon carbide (SiC) MOSFET chip. In other embodiments, the number of MOSFET chips in the upper bridge arm chipset 21 and the lower bridge arm chipset 22 is not limited to two. A higher number of MOSFET chips in the upper bridge arm chipset 21 and the lower bridge arm chipset 22 is more beneficial for improving the current carrying capacity of the power module 100. Furthermore, the switching chips in the upper bridge arm chipset 21 and the lower bridge arm chipset 22 are not limited to SiC MOSFET chips; for example, they can also be silicon-based MOSFET chips.

[0060] Specifically, SiC MOSFET chips possess superior characteristics compared to silicon devices, exhibiting outstanding performance such as high blocking voltage, high operating temperature, high switching speed, and low loss, contributing to improved power converter efficiency and power density. In particular, the size of an optical module is typically limited to tens of square millimeters. This restricts the current a single optical module can handle, thus necessitating multi-chip parallel power modules for high-power applications. Traditional power modules contain excessive stray inductance, limiting the switching speed and efficiency of SiC MOSFETs, causing switching oscillations and power losses. To reduce stray inductance in the power loop, various power module layouts have been proposed. For example, placing MOSFET chips and anti-parallel diodes close together reduces the current commutation path distance, lowering the power loop and improving the switching dynamics of the power module. Furthermore, planar packaged power modules can also reduce stray inductance by eliminating bond wires and offer double-sided cooling capabilities, enhancing thermal management and enabling the power module to handle higher currents and power. However, the manufacturing process of planar power modules is complex and time-consuming; for example, planar power modules require special metallization pads to handle double-sided soldering. In this embodiment, multiple positive DC terminals, multiple negative DC terminals, and multiple AC terminals are provided to offer multiple parallel commutation circuits. Furthermore, each commutation circuit has a structure with current flowing in opposite directions, which helps to offset some of the stray inductance in the circuit through mutual inductance, thereby reducing the power module's losses.

[0061] In addition, such as Figure 1 As shown in the embodiments of this application, the switching transistor chip and various terminals are arranged compactly, which helps to reduce the length of the commutation circuit and the parasitic inductance of the commutation circuit, thereby reducing turn-off voltage spikes and switching oscillations. Specifically, compared with conventional three-phase full-bridge modules, the equivalent power circuit stray inductance is reduced by 50% in the embodiments of this application, which helps to improve the power density of the power module and reduce the required heat sink size and the size of the gate driver board integrating the module. In addition, the maturity of this technology allows for good cost control.

[0062] Figure 3 for Figure 1 The diagram shows the equivalent circuit of the power module. Please refer to the attached diagram. Figure 1 and Figure 3 Three half-bridge structures (20 units) constitute a three-phase full-bridge module, used in motor drivers. Figure 1 The four positive DC terminals 231 of the first half-bridge structure 20a, the second half-bridge structure 20b, and the third half-bridge structure 20c correspond to respectively Figure 3The P1 node of the first half-bridge structure 20a, the P2 node of the second half-bridge structure 20b, and the P3 node of the third half-bridge structure 20c respectively constitute the U-phase positive DC terminal 231, V-phase positive DC terminal 231, and W-phase positive DC terminal 231 of the motor driver. Figure 1 The four negative DC terminals 237 of the first half-bridge structure 20a, the second half-bridge structure 20b, and the third half-bridge structure 20c correspond to respectively Figure 3 The N1 node of the first half-bridge structure 20a, the N2 node of the second half-bridge structure 20b, and the N3 node of the third half-bridge structure 20c respectively constitute the U-phase negative DC terminal 237, V-phase negative DC terminal 237, and W-phase negative DC terminal 237 of the motor driver. Figure 1 The four AC terminals 233 of the first half-bridge structure 20a, the second half-bridge structure 20b, and the third half-bridge structure 20c correspond to respectively Figure 3 The U-node of the first half-bridge structure 20a, the V-node of the second half-bridge structure 20b, and the W-node of the third half-bridge structure 20c respectively constitute the U-phase AC terminal 233, V-phase AC terminal 233, and W-phase AC terminal 233 of the motor driver.

[0063] Figure 3 For the upper half-bridge chip group 21 and the lower half-bridge chip group 22, only one MOSFET is shown for illustration. Figure 1 In the first half-bridge structure 20a, the first source terminal 232, the first gate terminal 234, the second source terminal 235, and the second gate terminal 236 respectively correspond to Figure 3 The S1, G1, S2, and G2 nodes of the first half-bridge structure 20a. Similarly, Figure 1 In the second half-bridge structure 20b, the first source terminal 232, the first gate terminal 234, the second source terminal 235, and the second gate terminal 236 respectively correspond to Figure 3 The S3, G3, S4 and G4 nodes of the third half-bridge structure 20c. Figure 1 In the third half-bridge structure 20c, the first source terminal 232, the first gate terminal 234, the second source terminal 235, and the second gate terminal 236 respectively correspond to Figure 3 The S5, G5, S6 and G6 nodes of the third half-bridge structure 20c.

[0064] In addition, such as Figure 1 As shown, the power module 100 also includes a thermistor conductive layer 38 located on the surface of the insulating substrate 10, and two thermistor terminals 238 located on and electrically connected to the thermistor conductive layer 38 (corresponding to...). Figure 3(T1 and T2 in the diagram). A thermistor is electrically connected between the two thermistor terminals 238, for example, to monitor the temperature of the power module 100.

[0065] It should be noted that in the above embodiments, the power module 100 includes three half-bridge structures 20 as an example. In other embodiments, the number of half-bridge structures 20 in the power module 100 is not limited; for example, the power module 100 may include one half-bridge structure 20. Figure 4 The power module 100 includes a half-bridge structure 20. The stray inductance generated by a single-phase flow through the converter circuit is illustrated in the Ansys Q3D simulation results. The measured stray inductance is 5.6nH, which significantly reduces the stray inductance of the equivalent power circuit (typically above 10nH, but reduced by more than 50% in this embodiment).

[0066] Furthermore, this application embodiment also provides an electronic device. The electronic device includes the power module 100 described above. Specifically, the electronic device is, for example, a motor driver, a photovoltaic inverter, or a boost converter; or, the electronic device is an inverter, a frequency converter, a refrigeration device, a metallurgical machinery device, an electric traction device, or other device with a motor, and the power module 100 is applied to the motor driver of the motor (e.g., a single-phase motor driver or a three-phase motor driver).

[0067] The above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to the above preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of this application should not depart from the spirit and scope of the technical solutions of this application.

Claims

1. A power module, characterized in that, The power module includes an insulating substrate and a half-bridge structure located on the insulating substrate, the half-bridge structure comprising: An upper half-bridge arm chipset and a lower half-bridge arm chipset, each comprising at least one switching transistor chip; and Multiple positive DC terminals, multiple negative DC terminals, and multiple AC terminals; The plurality of positive DC terminals are electrically connected to the upper half-bridge chip group, the plurality of negative DC terminals are electrically connected to the lower half-bridge chip group, and the plurality of AC terminals are electrically connected to the upper half-bridge chip group and the lower half-bridge chip group, respectively. Along a first direction, the opposite sides of the upper half-bridge chip group are defined as a first side and a second side, respectively. The plurality of positive DC terminals and the plurality of negative DC terminals are both located on the first side, and the plurality of AC terminals are located on the second side. Along the first direction, the lower half-bridge chip group is located between the negative DC terminals and the plurality of AC terminals. The current flow direction in the half-bridge structure is from the plurality of positive DC terminals, the at least one switching chip in the upper half-bridge chip group, the plurality of AC terminals, the at least one switching chip in the lower half-bridge chip group, to the plurality of negative DC terminals, and the current flow direction from the plurality of positive DC terminals to the at least one switching chip in the upper half-bridge chip group is opposite to the current flow direction from the plurality of AC terminals, the at least one switching chip in the lower half-bridge chip group, to the plurality of negative DC terminals.

2. The power module according to claim 1, characterized in that, The number of the plurality of positive DC terminals, the plurality of negative DC terminals, and the plurality of AC terminals are equal.

3. The power module according to claim 1, characterized in that, The number of each of the plurality of positive DC terminals, the plurality of negative DC terminals, and the plurality of AC terminals is greater than or equal to 3 and less than or equal to 8.

4. The power module according to claim 1, characterized in that, The distance between two adjacent positive DC terminals, the distance between two adjacent negative DC terminals, and the distance between two adjacent AC terminals are all greater than or equal to 1 mm and less than or equal to 5 mm.

5. The power module according to claim 1, characterized in that, The half-bridge structure further includes a DC positive conductive layer, a DC negative conductive layer, and an AC conductive layer spaced apart on the surface of the insulating substrate; The plurality of positive DC terminals are electrically connected to the positive DC conductive layer, the plurality of negative DC terminals are electrically connected to the negative DC conductive layer, and the plurality of AC terminals are electrically connected to the AC conductive layer.

6. The power module according to claim 1, characterized in that, The at least one switching transistor chip is a plurality of MOSFET chips connected in parallel; In the upper half-bridge arm chipset, the drain of each MOSFET chip is electrically connected to the plurality of positive DC terminals, and the power source of each MOSFET chip is electrically connected to the plurality of AC terminals. In the lower half-bridge chip group, the drain of each MOSFET chip is electrically connected to the plurality of AC terminals, and the power source of each MOSFET chip is electrically connected to the plurality of negative DC terminals.

7. The power module according to claim 6, characterized in that, The half-bridge structure further includes a first source conductive layer, a first gate conductive layer, a second source conductive layer, and a second gate conductive layer spaced apart on the surface of the insulating substrate. In the upper half-bridge arm chip group, the driving source of each MOSFET chip is electrically connected to the first source conductive layer, and the gate of each MOSFET chip is electrically connected to the first gate conductive layer. In the lower half-bridge arm chipset, the driving source of each MOSFET chip is electrically connected to the second source conductive layer, and the gate of each MOSFET chip is electrically connected to the second gate conductive layer.

8. The power module according to claim 7, characterized in that, The half-bridge structure further includes a first source terminal, a first gate terminal, a second source terminal, and a second gate terminal; The first source terminal is electrically connected to the first source conductive layer, the first gate terminal is electrically connected to the first gate conductive layer, the second source terminal is electrically connected to the second source conductive layer, and the second gate terminal is electrically connected to the second gate conductive layer.

9. The power module according to any one of claims 1 to 8, characterized in that, The power module includes three half-bridge structures; wherein the three half-bridge structures are spaced apart along a second direction that intersects the first direction.

10. An electronic device, characterized in that, Includes the power module according to any one of claims 1 to 9.

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