Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and method for forming the same include: a substrate having a plurality of fins; a first gate structure located on the substrate; source / drain doped layers located on either side of the first gate structure; a dielectric structure located on the substrate, the dielectric structure being higher than the first gate structure; a first opening located within the dielectric structure; an isolation structure located within the first opening; a gate conductive opening located within the dielectric structure; and a gate conductive layer located within the gate conductive opening, the gate conductive layer being electrically connected to the first gate structure. The isolation structure is used as a self-aligned film layer for forming the gate conductive opening, effectively improving the accuracy of the gate conductive opening formation and reducing the occurrence of circuit shorting, thereby improving the performance of the resulting semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] The electronics industry has experienced a growing demand for smaller and faster electronic devices, which are able to simultaneously support a greater number of increasingly complex and sophisticated functions. Consequently, a continuing trend in the semiconductor industry is to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been largely achieved by scaling down semiconductor IC sizes (e.g., minimum feature sizes) and thereby increasing production efficiency and reducing associated costs. However, this scaling down also increases the complexity of semiconductor manufacturing processes. Consequently, continued advancements in semiconductor ICs and devices require similar advancements in semiconductor manufacturing processes and technology.

[0003] As part of the device, the gate's material significantly impacts its performance. Traditional polysilicon gate processes suffer from the "polysilicon depletion" effect, which affects device conduction, leading to the introduction of metal gates. To achieve better epitaxial stress, the metal gate is cut off when it exceeds the 5nm node. This process not only achieves a good profile but also allows for feature sizes exceeding 20nm to be reduced.

[0004] However, there are still many problems in the metal gate cutting process in the prior art. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can effectively improve the performance of the finally formed semiconductor structure.

[0006] To solve the above problems, the present invention provides a semiconductor structure, comprising: a substrate having a plurality of fins parallel to a first direction; an isolation layer located on the substrate, the isolation layer covering a portion of the sidewalls of the fins, and the top surface of the isolation layer being lower than the top surface of the fins; a first gate structure located on the isolation layer, the first gate structure spanning the plurality of fins along a second direction, the first direction being perpendicular to the second direction; sidewalls located on the sidewalls of the first gate structure; source-drain doped layers located within the fins on both sides of the first gate structure; a plurality of source-drain conductive layers, the source-drain conductive layers connecting the plurality of source-drain doped layers on one side of the first gate structure, the top surface of the first gate structure being higher than the top surface of the source-drain conductive layers; a dielectric structure located on the isolation layer, the dielectric structure covering the first gate structure and the source-drain conductive layer, and the top surface of the dielectric structure is higher than the top surfaces of the first gate structure and the source-drain conductive layer; a first opening located in the dielectric structure, the first opening penetrating the first gate structure along the first direction and exposing a portion of the isolation layer; a second opening located in the dielectric structure, the second opening exposing the top surface of the source-drain conductive layer; an isolation structure located in the first opening and the second opening, the material of the isolation structure being different from that of the dielectric structure; a gate conductive opening located in the dielectric structure and adjacent to the isolation structure, the gate conductive opening exposing a portion of the top surface of the first gate structure and a portion of the sidewall of the isolation structure; and a gate conductive layer located in the gate conductive opening, the gate conductive layer being electrically connected to the first gate structure.

[0007] Optionally, it also includes: a plurality of second gate structures located on the substrate, the second gate structures spanning the plurality of fins along the second direction, and the source-drain doping layer located between adjacent first gate structures and second gate structures, or between adjacent second gate structures.

[0008] Optionally, the dielectric structure includes: a first dielectric layer located on the isolation layer, the first dielectric layer covering the sidewalls of the first gate structure and exposing the top surface of the first gate structure; and a second dielectric layer located on the first dielectric layer.

[0009] Optionally, the material of the first dielectric layer is the same as the material of the second dielectric layer.

[0010] Optionally, the material of the isolation structure includes silicon carbide, dense silicon oxide, silicon carbon boron nitride or silicon oxynitride; the material of the first dielectric layer and the material of the second dielectric layer include silicon oxide, low-K dielectric material or ultra-low-K dielectric material.

[0011] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate having a plurality of fins parallel to a first direction; forming an isolation layer on the substrate, the isolation layer covering part of the sidewalls of the fins, and the top surface of the isolation layer being lower than the top surface of the fins; forming a dielectric structure, an initial first gate structure, a sidewall and a plurality of source-drain doped layers, the initial first gate structure being located on the isolation layer, and the initial first gate structure spans the plurality of fins along a second direction, the first direction being perpendicular to the second direction, the sidewall being located on the sidewall of the initial first gate structure, the source-drain doped layers being located in the fins on both sides of the initial first gate structure, the dielectric structure covering the initial first gate structure, and the top surface of the dielectric structure being higher than the top surface of the initial first gate structure; forming a plurality of initial source-drain conductive layers in the dielectric structure, each of the initial source-drain conductive layers being connected to the plurality of source-drain doped layers on one side of the first gate structure, and the top surface of the initial source-drain conductive layer being adjacent to the plurality of source-drain doped layers. The method comprises the steps of: removing a portion of the initial first gate structure and a portion of the initial source-drain conductive layer so that the initial first gate structure forms a first gate structure, and the initial source-drain conductive layer forms a source-drain conductive layer, wherein the top surface of the first gate structure is higher than the top surface of the source-drain conductive layer; forming a first opening and a second opening in the dielectric structure, wherein the first opening penetrates the first gate structure along the first direction and exposes a portion of the isolation layer, and the second opening exposes the top surface of the source-drain conductive layer; forming an isolation structure in the first opening and the second opening, wherein the top surface of the isolation structure is flush with the top surface of the dielectric structure, and the material of the isolation structure is different from that of the dielectric structure; forming a gate conductive opening adjacent to the isolation structure in the dielectric structure, wherein the gate conductive opening exposes a portion of the top surface of the first gate structure and a portion of the sidewall of the isolation structure; and forming a gate conductive layer in the gate conductive opening, wherein the gate conductive layer is electrically connected to the first gate structure.

[0012] Optionally, the initial source-drain conductive layer has a first size along the direction normal to the substrate surface; the initial first gate structure has a second size along the direction normal to the substrate surface, and the ratio of the first size to the second size is greater than 3:2.

[0013] Optionally, the method for forming the isolation structure includes: forming an isolation material layer in the first opening and the second opening, and on the top surface of the dielectric structure; and planarizing the isolation material layer until the top surface of the dielectric structure is exposed, thereby forming the isolation structure.

[0014] Optionally, the method for forming the gate conductive layer includes: forming a gate conductive material layer within the gate conductive opening and on the top surfaces of the dielectric structure and the isolation structure; and flattening the gate conductive material layer until the top surfaces of the dielectric structure and the isolation structure are exposed to form the gate conductive layer.

[0015] Optionally, in the process of forming the initial first gate structure, it also includes: forming a plurality of second gate structures on the substrate, and the source-drain doping layer is located between adjacent initial first gate structures and the second gate structures, or between adjacent second gate structures.

[0016] Optionally, the dielectric structure includes: a first dielectric layer located on the substrate, the first dielectric layer covering the sidewalls of the initial first gate structure and exposing the top surface of the initial first gate structure; and a second dielectric layer located on the first dielectric layer.

[0017] Optionally, the material of the first dielectric layer is the same as the material of the second dielectric layer.

[0018] Optionally, the material of the isolation structure includes silicon carbide, dense silicon oxide, silicon carbon boron nitride or silicon oxynitride; the material of the first dielectric layer and the material of the second dielectric layer include silicon oxide, low-K dielectric material or ultra-low-K dielectric material.

[0019] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0020] The structure of the present invention includes a gate conductive opening within the dielectric structure, exposing a portion of the top surface of the first gate structure and a portion of the sidewall of the isolation structure. Using the isolation structure as a self-aligned film layer for forming the gate conductive opening effectively improves the accuracy of the gate conductive opening formation, reduces the occurrence of circuit shorting, and thereby enhances the performance of the resulting semiconductor structure.

[0021] In the formation method of the technical solution of the present invention, an isolation structure is formed within the first opening. The top surface of the isolation structure is higher than the top surface of the first gate structure and is flush with the top surface of the subsequently formed gate conductive layer. The isolation structure is made of a different material than the dielectric structure. Using the isolation structure as a self-aligned film layer for the formed gate conductive opening effectively improves the accuracy of the gate conductive opening formation, reduces the occurrence of circuit shorting, and thereby enhances the performance of the resulting semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 and Figure 2It is a structural schematic diagram of the steps in the formation process of a semiconductor structure;

[0023] Figures 3 to 22 It is a schematic structural diagram of each step of another embodiment of the method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0024] As described in the background art, there are still many problems in the metal gate cutting process in the prior art, which will be described in detail below with reference to the accompanying drawings.

[0025] Figure 1 and Figure 2 It is a structural schematic diagram of the various steps in the process of forming a semiconductor structure.

[0026] Please refer to Figure 1 A substrate 100 is provided, having a plurality of mutually separated fins 101 thereon, the substrate 100 including an isolation region A1, a first device region B1, and a second device region B2, the isolation region A1 being located between the first device region B1 and the second device region B2, and the plurality of fins 101 being located in the first device region B1 and the second device region B2, respectively; a first dielectric layer 102, a gate structure 103, and a plurality of source-drain doped layers (not shown) are formed, the gate structure 103 being located on the substrate 100, the source-drain doped layers being located in the substrate 100 on both sides of the gate structure 103, the first dielectric layer 102 covering the sidewalls of the gate structure 103; the gate structure 103 located on the isolation region A1 is removed, and a first opening (not shown) is formed in the first dielectric layer 102; and an isolation structure 104 is formed in the first opening.

[0027] Please refer to Figure 2 , a second dielectric layer 105 is formed on the gate structure 103 and the isolation structure 104; a gate conductive opening (not labeled) is formed in the second dielectric layer 105, wherein the gate conductive opening exposes the top surface of the gate structure 103 located on the first device area B1; a gate conductive layer 106 is formed in the gate conductive opening, wherein the gate conductive layer 106 is electrically connected to the gate structure 103 located on the first device area B1.

[0028] In this embodiment, the gate structure 103 can be effectively isolated by forming the isolation structure 104 , so that the gate structure 103 can obtain a good outer profile and shrink the feature size.

[0029] However, in the process of forming the gate conductive opening in the second dielectric layer 105, since there is no self-aligned film layer as a reference, this places a high requirement on the alignment accuracy of the mask, so that the formed gate conductive opening is likely to also expose the top surface of the gate structure 103 located on the second device area B2 (such as Figure 2 As shown in part A in FIG, the gate conductive layer 106 is formed so as to electrically connect the gate structure 103 located on the first device region B1 and the gate structure 103 located on the second device region B2 at the same time, causing a short circuit in the circuit.

[0030] Based on this, the present invention provides a semiconductor structure and method for forming the same. This structure forms an isolation structure within the first opening. The isolation structure's top surface is higher than the top surface of the first gate structure and flush with the top surface of a subsequently formed gate conductive layer. The isolation structure is made of a different material than the dielectric structure. By using the isolation structure as a self-aligned film layer for forming the gate conductive opening, the accuracy of the gate conductive opening formation is effectively improved, the occurrence of circuit shorting is reduced, and the performance of the resulting semiconductor structure is thereby enhanced.

[0031] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0032] Figures 3 to 22 It is a structural schematic diagram of a formation process of a semiconductor structure according to an embodiment of the present invention.

[0033] Please refer to Figure 3 and Figure 4 , Figure 3 It is a top view of the semiconductor structure. Figure 4 yes Figure 3 In the cross-sectional view along line AA, a substrate 200 is provided, and a plurality of fins 201 parallel to a first direction X are formed on the substrate 200 .

[0034] In this embodiment, the method for forming the substrate 200 includes: providing an initial substrate (not shown), the initial substrate having a mask layer (not shown), the mask layer exposing a portion of the top surface of the initial substrate; etching the initial substrate using the mask layer as a mask to form the substrate 200.

[0035] In this embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.

[0036] In this embodiment, the material of the fin 201 is silicon; in other embodiments, the material of the fin may also be germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.

[0037] Please refer to Figure 5 and Figure 6 , Figure 5 It is a three-dimensional diagram of the semiconductor structure. Figure 6 yes Figure 5 In the cross-sectional view taken along line BB, an isolation layer 202 is formed on the substrate. The isolation layer 202 covers a portion of the sidewall of the fin 201 , and a top surface of the isolation layer 202 is lower than a top surface of the fin 201 .

[0038] In this embodiment, the method for forming the isolation layer 202 includes: forming an initial isolation layer (not shown) on the substrate; etching and removing a portion of the initial isolation layer to form the isolation layer 202, wherein the top surface of the isolation layer 202 is lower than the top surface of the fin 201.

[0039] The isolation layer 202 is made of an insulating material, which includes silicon oxide or silicon oxynitride. In this embodiment, the isolation layer 202 is made of silicon oxide.

[0040] In this embodiment, after forming the isolation layer 202, a dielectric structure, an initial first gate structure, sidewalls, and a plurality of source-drain doped layers are formed. The initial first gate structure is located on the isolation layer 202, and the initial first gate structure spans a plurality of the fins along the second direction. The first direction X is perpendicular to the second direction. The sidewalls are located on the sidewalls of the initial first gate structure. The source-drain doped layers are located in the fins 201 on both sides of the initial first gate structure. The dielectric structure covers the initial first gate structure, and the top surface of the dielectric structure is higher than the top surface of the initial first gate structure. For details, please refer to Figures 7 to 10 .

[0041] Please refer to Figure 7 , forming a first dummy gate structure 203 on the isolation layer.

[0042] In this embodiment, the process of forming the first dummy gate structure 203 further includes: forming a plurality of second dummy gate structures 204 on the isolation layer 202 .

[0043] In this embodiment, the first dummy gate structure 203 and the second dummy gate structure 204 respectively span over a plurality of the fins 201 along the second direction Y.

[0044] In this embodiment, the first dummy gate structure 203 and the second dummy gate structure 204 respectively include: a dummy gate dielectric layer and a dummy gate layer (not labeled) located on the dummy gate dielectric layer.

[0045] In this embodiment, the gate dielectric layer is made of silicon oxide; in other embodiments, the dummy gate dielectric layer may also be made of silicon oxynitride.

[0046] In this embodiment, the material of the dummy gate layer is polysilicon.

[0047] In this embodiment, please continue to refer to Figure 7 , further comprising: forming sidewalls (not shown) on the sidewalls of the initial first gate structure 203 and the second gate structure 204 .

[0048] In this embodiment, the sidewall spacer is made of silicon nitride.

[0049] Please refer to Figure 8 , a plurality of source-drain doped layers 205 are formed in the fin 201 , and the source-drain doped layers 205 are located between adjacent first dummy gate structures 203 and second dummy gate structures 204 , or between adjacent second dummy gate structures 204 .

[0050] In this embodiment, the method for forming the source-drain doped layer 205 includes: etching the fin 201 using the first dummy gate structure 203 and the second dummy gate structure 204 as a mask to form a plurality of source-drain openings (not marked) in the fin 201; and forming the source-drain doped layer 205 in the source-drain openings.

[0051] Please refer to Figure 9 After forming the source / drain doping layer 205 , a first dielectric layer 206 is formed on the isolation layer 202 .

[0052] In this embodiment, the first dielectric layer 206 covers the sidewalls of the first dummy gate structure 203 and the second dummy gate structure 204 , and exposes the top surfaces of the first dummy gate structure 203 and the second dummy gate structure 204 .

[0053] In this embodiment, the material of the first dielectric layer 206 is silicon oxide; in other embodiments, the material of the first dielectric layer can also be low-K dielectric material (referring to a dielectric material with a relative dielectric constant lower than 3.9) or ultra-low-K dielectric material (referring to a dielectric material with a relative dielectric constant lower than 2.5).

[0054] Please refer to Figure 10 After forming the first dielectric layer 206 , an initial first gate structure 207 is formed.

[0055] In this embodiment, the process of forming the initial first gate structure 207 further includes forming a plurality of second gate structures 208 .

[0056] In this embodiment, the method for forming the initial first gate structure 207 and the second gate structure 208 includes: removing the first dummy gate structure 203 and the second dummy gate structure 204, forming a first gate opening and a plurality of second gate openings (not marked) in the first dielectric layer 206; forming the first gate structure 207 in the first gate opening, and forming the second gate structure 208 in the second gate opening.

[0057] In this embodiment, the initial first gate structure 207 and the second gate structure 208 include a gate dielectric layer, a gate layer located on the gate dielectric layer, and a mask layer (not shown) located on the gate layer.

[0058] The gate layer is made of a metal, including tungsten, aluminum, copper, titanium, silver, gold, lead, or nickel. In this embodiment, the gate layer is made of tungsten.

[0059] Please refer to Figure 11 After forming the initial first gate structure 207 , a second dielectric layer 209 is formed on the first dielectric layer 206 and the initial first gate structure 207 .

[0060] In this embodiment, the first dielectric layer 206 and the second dielectric layer 209 constitute a dielectric structure.

[0061] In this embodiment, the material of the second dielectric layer 209 is silicon oxide; in other embodiments, the material of the second dielectric layer can also be low-K dielectric material (referring to a dielectric material with a relative dielectric constant lower than 3.9) or ultra-low-K dielectric material (referring to a dielectric material with a relative dielectric constant lower than 2.5).

[0062] Please refer to Figure 12 After forming the second dielectric layer 209, a plurality of initial source-drain conductive layers 210 are formed in the dielectric structure. Each of the initial source-drain conductive layers 210 is connected to the plurality of source-drain doped layers 205 on one side of the first gate structure 207, and the top surface of the initial source-drain conductive layer 210 is higher than the top surface of the first gate structure 207.

[0063] In this embodiment, the method for forming the initial source-drain conductive layer 210 includes: forming a plurality of source-drain conductive openings (not shown) in the dielectric structure, each of the source-drain conductive openings exposing a plurality of the source-drain doped layers 205 on one side of the initial first gate structure 207; and forming the initial source-drain conductive layer 210 in the source-drain conductive openings, the initial source-drain conductive layer 210 filling the source-drain conductive openings.

[0064] In this embodiment, the initial source-drain conductive layer 210 has a first size d1 along the direction normal to the substrate surface; the initial first gate structure 207 has a second size d2 along the direction normal to the substrate surface, and the ratio of the first size d1 to the second size d2 is greater than 3:2.

[0065] In this embodiment, after forming the initial source-drain conductive layer 210, the process further includes: removing a portion of the initial first gate structure 207 and a portion of the initial source-drain conductive layer 210, so that the initial first gate structure 207 forms a first gate structure, the initial source-drain conductive layer 210 forms a source-drain conductive layer, the top surface of the first gate structure is higher than the top surface of the source-drain conductive layer, and forming a first opening and a second opening in the dielectric structure, the first opening passing through the first gate structure along the first direction X to expose a portion of the isolation layer 202, and the second opening exposing the top surface of the source-drain conductive layer. For the specific formation process, please refer to Figures 13 to 17 .

[0066] Please refer to Figures 13 to 15 , Figure 13 It is a top view of the semiconductor structure. Figure 14 yes Figure 13 Schematic diagram of the cross section along the CC line, Figure 15 yes Figure 14 In the cross-sectional view along line DD, a portion of the initial first gate structure 207 is removed, and an initial first opening 211 is formed in the dielectric structure.

[0067] In this embodiment, the mask layer in the initial first gate structure 207 is removed. During the removal of the mask layer, the adjacent initial source / drain conductive layer 210 can be used as a self-aligned film layer, thereby effectively reducing the difficulty of the etching process.

[0068] Please refer to Figure 16 and Figure 17 , Figure 16 and Figure 14 The viewing direction is consistent with Figure 17 and Figure 15In accordance with the viewing direction, after the initial first opening 211 is formed, the gate layer exposed in the initial first gate structure 207 is removed until the top surface of the isolation layer 202 is exposed, so that the initial first gate structure 207 forms the first gate structure 216, and the initial first opening 211 forms the first opening 212.

[0069] In this embodiment, the process of removing the gate layer exposed in the initial first gate structure 207 also includes: removing part of the initial source-drain conductive layer 210 to form a source-drain conductive layer 213 and a second opening 214, wherein the second opening 214 is located on both sides of the first opening 212, and the second opening 214 exposes the top surface of the source-drain conductive layer 213, and the bottom surface of the second opening 214 is lower than the top surface of the first gate structure 207.

[0070] Please refer to Figure 18 and Figure 19 After forming the first opening 212 and the second opening 214, an isolation structure 215 is formed in the first opening 212 and the second opening 214, wherein the top surface of the isolation structure 215 is flush with the top surface of the dielectric structure, and the material of the isolation structure 215 is different from the material of the dielectric structure.

[0071] In this embodiment, an isolation structure 215 is formed within the first opening 212. The top surface of the isolation structure 215 is higher than the top surface of the first gate structure 216 and is flush with the top surface of the subsequently formed gate conductive layer. Furthermore, the material of the isolation structure 215 is different from that of the dielectric structure. Using the isolation structure 215 as a self-aligned film layer for the subsequently formed gate conductive opening effectively improves the accuracy of the gate conductive opening formation, reduces the occurrence of circuit shorting, and thereby enhances the performance of the resulting semiconductor structure.

[0072] In this embodiment, the method for forming the isolation structure 215 includes: forming an isolation material layer (not shown) in the first opening 212 and the second opening 214, and on the top surface of the dielectric structure; and planarizing the isolation material layer until the top surface of the dielectric structure is exposed, thereby forming the isolation structure 215.

[0073] The material of the isolation structure 215 includes silicon carbide, dense silicon oxide, silicon carbon boron nitride (SiBCN), or silicon oxynitride. In this embodiment, the material of the isolation structure 215 is silicon carbide.

[0074] Please refer to Figure 20 and Figure 21 , Figure 20It is a top view of the semiconductor structure. Figure 21 yes Figure 20 In the cross-sectional diagram along line EE, after the isolation structure 215 is formed, a gate conductive opening 217 adjacent to the isolation structure 215 is formed in the dielectric structure, and the gate conductive opening 217 exposes part of the top surface of the first gate structure 216 and part of the side wall of the isolation structure 215.

[0075] In this embodiment, the isolation structure 215 is used as a self-aligned film layer to form the gate conductive opening 217, which effectively improves the accuracy of forming the gate conductive opening 217 and reduces the occurrence of circuit short circuit problems, thereby improving the performance of the ultimately formed semiconductor structure.

[0076] Please refer to Figure 22 , Figure 22 and Figure 21 In the same viewing direction, a gate conductive layer 218 is formed in the gate conductive opening 217 , and the gate conductive layer 218 is electrically connected to the first gate structure 216 .

[0077] In this embodiment, the method for forming the gate conductive layer 218 includes: forming a gate conductive material layer (not shown) within the gate conductive opening 217 and on the top surface of the dielectric structure and the isolation structure 215; and flattening the gate conductive material layer until the top surface of the dielectric structure and the isolation structure 215 are exposed to form the gate conductive layer 218.

[0078] In this embodiment, the planarization process adopts a chemical mechanical polishing process.

[0079] Accordingly, an embodiment of the present invention further provides a semiconductor structure, please continue to refer to Figure 22, comprising: a substrate 200 having a plurality of fins 201 parallel to a first direction X; an isolation layer 202 located on the substrate 200, the isolation layer 202 covering a portion of the sidewalls of the fins 201, and a top surface of the isolation layer 202 being lower than the top surface of the fins 201; a first gate structure 216 located on the isolation layer 202, the first gate structure 216 spanning the plurality of fins 201 along a second direction Y, the first direction X being perpendicular to the second direction Y; sidewalls located on the sidewalls of the first gate structure 216; source-drain doped layers 205 located in the fins on both sides of the first gate structure 216; a plurality of source-drain conductive layers 213, the source-drain conductive layers 213 connecting the plurality of source-drain doped layers 205 on one side of the first gate structure 216, the top surface of the first gate structure 216 being higher than the top surface of the source-drain conductive layer 213; a dielectric structure located on the isolation layer 202, the dielectric structure covering the first gate structure 216 and the source-drain conductive layers 213. a conductive layer 213, wherein the top surface of the dielectric structure is higher than the top surfaces of the first gate structure 216 and the source-drain conductive layer 213; a first opening 212 located in the dielectric structure, the first opening 212 penetrating the first gate structure 216 along the first direction X and exposing a portion of the isolation layer 202; a second opening 214 located in the dielectric structure, the second opening 214 exposing the top surface of the source-drain conductive layer 213; an isolation structure 215 located within the first opening 212 and the second opening 214, the isolation structure 215 being made of a material different from that of the dielectric structure; gate conductive openings 217 located in the dielectric structure and adjacent to the isolation structures 215, the gate conductive openings 217 exposing a portion of the top surface of the first gate structure 216 and a portion of the sidewalls of the isolation structure 215; and a gate conductive layer 218 located within the gate conductive openings 217, the gate conductive layer 218 being electrically connected to the first gate structure 216.

[0080] In this embodiment, the gate conductive opening 217 exposes a portion of the top surface of the first gate structure 216 and a portion of the sidewall of the isolation structure 215. Utilizing the isolation structure 215 as a self-aligned film layer for forming the gate conductive opening 217 effectively improves the accuracy of forming the gate conductive opening 217, reduces the occurrence of circuit shorting problems, and thereby improves the performance of the resulting semiconductor structure.

[0081] In this embodiment, it also includes: a plurality of second gate structures 208 located on the substrate 200, the second gate structures 208 spanning the plurality of fins 201 along the second direction Y, and the source-drain doped layer 205 located between adjacent first gate structures 216 and second gate structures 208, or located between adjacent second gate structures 208.

[0082] In this embodiment, the dielectric structure includes: a first dielectric layer 206 located on the isolation layer 202 , the first dielectric layer 206 covers the sidewalls of the first gate structure 216 and exposes the top surface of the first gate structure 216 , and a second dielectric layer 209 located on the first dielectric layer 206 .

[0083] In this embodiment, the material of the first dielectric layer 206 and the material of the second dielectric layer 209 are the same.

[0084] In this embodiment, the material of the isolation structure 215 includes silicon carbide, dense silicon oxide, silicon carbon boron nitride or silicon oxynitride; the material of the first dielectric layer 206 and the material of the second dielectric layer 209 include silicon oxide, low-K dielectric material or ultra-low-K dielectric material.

[0085] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: a substrate having a plurality of fins parallel to a first direction; an isolation layer located on the substrate, wherein the isolation layer covers a portion of a sidewall of the fin, and a top surface of the isolation layer is lower than a top surface of the fin; a first gate structure located on the isolation layer, the first gate structure spanning across the plurality of fins along a second direction, the first direction being perpendicular to the second direction; a sidewall spacer located on a sidewall of the first gate structure; source-drain doped layers located in the fins on both sides of the first gate structure; a plurality of source-drain conductive layers, wherein the source-drain conductive layers are connected to the plurality of source-drain doped layers on one side of the first gate structure, and a top surface of the first gate structure is higher than a top surface of the source-drain conductive layers; a dielectric structure located on the isolation layer, the dielectric structure covering the first gate structure and the source-drain conductive layer, and a top surface of the dielectric structure being higher than top surfaces of the first gate structure and the source-drain conductive layer; a first opening located in the dielectric structure, the first opening penetrating the first gate structure along the first direction and exposing a portion of the isolation layer; a second opening located in the dielectric structure, wherein the second opening exposes a top surface of the source-drain conductive layer; an isolation structure located in the first opening and the second opening, wherein the material of the isolation structure is different from the material of the dielectric structure; gate conductive openings located in the dielectric structure and adjacent to the isolation structures, respectively, the gate conductive openings exposing a portion of the top surface of the first gate structure and a portion of the sidewall of the isolation structure; A gate conductive layer is located in the gate conductive opening, and the gate conductive layer is electrically connected to the first gate structure.

2. The semiconductor structure according to claim 1, wherein: Also includes: A plurality of second gate structures are located on the substrate, the second gate structures spanning the plurality of fins along the second direction, and the source-drain doped layer is located between adjacent first gate structures and second gate structures, or between adjacent second gate structures.

3. The semiconductor structure according to claim 1, wherein: The dielectric structure includes: a first dielectric layer located on the isolation layer, the first dielectric layer covers the sidewalls of the first gate structure and exposes the top surface of the first gate structure; and a second dielectric layer located on the first dielectric layer.

4. The semiconductor structure according to claim 3, wherein: The material of the first dielectric layer is the same as that of the second dielectric layer.

5. The semiconductor structure according to claim 3, wherein: The material of the isolation structure includes silicon carbide, dense silicon oxide, silicon carbon boron nitride or silicon oxynitride; the material of the first dielectric layer and the material of the second dielectric layer include silicon oxide, low-K dielectric material or ultra-low-K dielectric material.

6. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate having a plurality of fins parallel to a first direction; forming an isolation layer on the substrate, wherein the isolation layer covers a portion of the sidewall of the fin, and a top surface of the isolation layer is lower than a top surface of the fin; forming a dielectric structure, an initial first gate structure, sidewalls, and a plurality of source-drain doped layers, wherein the initial first gate structure is located on the isolation layer and spans across the plurality of fins along a second direction, the first direction being perpendicular to the second direction, the sidewalls being located on sidewalls of the initial first gate structure, the source-drain doped layers being located within the fins on both sides of the initial first gate structure, the dielectric structure covering the initial first gate structure, and a top surface of the dielectric structure being higher than a top surface of the initial first gate structure; forming a plurality of initial source-drain conductive layers in the dielectric structure, each of the initial source-drain conductive layers being connected to the plurality of source-drain doped layers on one side of the first gate structure, and having a top surface flush with a top surface of the dielectric structure; removing a portion of the initial first gate structure and a portion of the initial source-drain conductive layer so that the initial first gate structure forms a first gate structure, and the initial source-drain conductive layer forms a source-drain conductive layer, wherein a top surface of the first gate structure is higher than a top surface of the source-drain conductive layer, and forming a first opening and a second opening in the dielectric structure, wherein the first opening penetrates the first gate structure along the first direction to expose a portion of the isolation layer, and the second opening exposes a top surface of the source-drain conductive layer; forming an isolation structure in the first opening and the second opening, wherein a top surface of the isolation structure is flush with a top surface of the dielectric structure, and a material of the isolation structure is different from a material of the dielectric structure; forming a gate conductive opening adjacent to the isolation structure in the dielectric structure, the gate conductive opening exposing a portion of the top surface of the first gate structure and a portion of the sidewall of the isolation structure; A gate conductive layer is formed in the gate conductive opening, and the gate conductive layer is electrically connected to the first gate structure.

7. The method for forming a semiconductor structure according to claim 6, wherein: The initial source-drain conductive layer has a first size along the direction normal to the substrate surface; the initial first gate structure has a second size along the direction normal to the substrate surface, and the ratio of the first size to the second size is greater than 3:

2.

8. The method for forming a semiconductor structure according to claim 6, wherein: The method for forming the isolation structure includes: forming an isolation material layer in the first opening and the second opening and on the top surface of the dielectric structure; and planarizing the isolation material layer until the top surface of the dielectric structure is exposed to form the isolation structure.

9. The method for forming a semiconductor structure according to claim 6, wherein: The method for forming the gate conductive layer includes: forming a gate conductive material layer in the gate conductive opening and on the top surfaces of the dielectric structure and the isolation structure; and flattening the gate conductive material layer until the top surfaces of the dielectric structure and the isolation structure are exposed to form the gate conductive layer.

10. The method for forming a semiconductor structure according to claim 6, wherein: The process of forming the initial first gate structure also includes: forming a plurality of second gate structures on the substrate, and the source-drain doped layer is located between adjacent initial first gate structures and the second gate structures, or between adjacent second gate structures.

11. The method for forming a semiconductor structure according to claim 6, wherein: The dielectric structure includes: a first dielectric layer located on the substrate, the first dielectric layer covers the sidewalls of the initial first gate structure and exposes the top surface of the initial first gate structure; and a second dielectric layer located on the first dielectric layer.

12. The method for forming a semiconductor structure according to claim 11, wherein: The material of the first dielectric layer is the same as that of the second dielectric layer.

13. The method for forming a semiconductor structure according to claim 12, wherein: The material of the isolation structure includes silicon carbide, dense silicon oxide, silicon carbon boron nitride or silicon oxynitride; the material of the first dielectric layer and the material of the second dielectric layer include silicon oxide, low-K dielectric material or ultra-low-K dielectric material.

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