IGBT device structure and method of manufacturing the same
By employing a mesh-like true gate and dummy gate design in IGBT devices, the conductive channel is increased and the short-circuit withstand capability is improved. This solves the problem of balancing low on-state voltage drop and high short-circuit withstand capability in existing technologies, and achieves an overall performance improvement for the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XIAMEN XINERGY MICROELECTRONICS CO LTD
- Filing Date
- 2022-11-18
- Publication Date
- 2026-06-09
AI Technical Summary
Existing IGBT devices struggle to simultaneously achieve both low on-state voltage drop and high short-circuit withstand capability. Traditional methods, which involve setting a dummy gate between the gate trenches, cannot achieve both simultaneously.
A grid-like true grid structure is adopted, and a dummy grid is set in the grid area of the true grid to increase the conductive channel to reduce the on-state voltage drop and improve the short-circuit withstand capability.
This achieves a IGBT device structure that simultaneously possesses low on-state voltage drop and high short-circuit withstand capability, thereby improving the overall performance of the device.
Smart Images
Figure CN115692472B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor power device technology, and in particular to an IGBT device structure and its manufacturing method. Background Technology
[0002] An Insulated-Gate Bipolar Transistor (IGBT) is a composite, fully controllable, voltage-driven power semiconductor device composed of a BJT (Bipolar Junction Transistor) and a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). It combines the advantages of high input impedance and low on-state voltage drop. IGBT devices are widely used in AC motors, inverters, frequency converters, traction drives, and other converter systems with DC voltages of 600V and above.
[0003] In the aforementioned applications, IGBT devices are required to have low on-state voltage drop and high short-circuit withstand capability. Traditional IGBT devices are manufactured by shrinking the cell size, thereby increasing the conductive channel and reducing channel resistance, effectively lowering the on-state voltage drop. However, as channel density continues to increase to further reduce the on-state voltage drop, the saturation current density also increases, thus reducing the device's short-circuit withstand capability. In the process of developing this invention, the inventors discovered at least the following problems in the prior art: Figure 1 As shown, in order to improve the short-circuit withstand capability of IGBT devices, the current approach is to sacrifice one or more strip trenches between the gate trenches to connect to the emitter or floating setting to form a dummy gate. However, such IGBT devices cannot simultaneously have low on-state voltage drop and high short-circuit withstand capability.
[0004] Therefore, the main objective of this invention is to provide an IGBT device structure and its manufacturing method to solve the above-mentioned problems.
[0005] It should be noted that the information disclosed in this background section is intended only to enhance the understanding of the overall background of the present invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention
[0006] The present invention provides an IGBT device comprising a substrate, a P-type well layer, a true gate, and a dummy gate.
[0007] The substrate has a front side and a back side. A P-type well layer is disposed on the front side of the substrate. A true gate is disposed on the front side of the substrate and connected to the P-type well layer. A dummy gate is disposed on the front side of the substrate and connected to the P-type well layer. Specifically, when viewed from above the IGBT device structure towards the front side of the substrate, the true gate appears as a grid, with several grid regions, and at least one dummy gate is disposed in each grid region.
[0008] In some embodiments, the IGBT device structure further includes a true gate oxide layer and a dummy gate oxide layer. The true gate oxide layer covers the true gate, and the dummy gate oxide layer connects to the dummy gate. The dummy gate oxide layer has an opening to expose the dummy gate, so that the dummy gate can be connected to the emitter.
[0009] In some embodiments, the materials of the true gate oxide layer and the dummy gate oxide layer include silicon dioxide.
[0010] In some embodiments, a dummy gate refers to a gate that is connected to the emitter or is floating.
[0011] In some embodiments, the real grid has four grid regions, and two dummy grids are provided in each grid region.
[0012] In some embodiments, the IGBT device structure further includes a P+ layer and an N-type emitter layer, wherein the P+ layer is disposed on the front side of the P-type well layer, the N-type emitter layer is disposed on the front side of the P-type well layer, and the N-type emitter layer and the P+ layer are independent of each other.
[0013] In some embodiments, the IGBT device structure further includes a guard ring, a field oxide layer, a dielectric layer, an emitter, a metal gate, and a passivation layer. The guard ring is disposed on the front side of the substrate, the field oxide layer is disposed on the guard ring, the dielectric layer covers the N-type emitter layer, the true gate, the dummy gate, and the oxide layer, the dielectric layer has a connection hole, the emitter is disposed on the front side of the dielectric layer and is connected to the P+ layer, the N-type emitter layer, the P-type well layer, and the dummy gate through the connection hole, the metal gate is disposed on the front side of the dielectric layer, and the passivation layer is disposed on the front side of the emitter and the front side of the metal gate.
[0014] In some embodiments, the IGBT device structure further includes a cutoff layer, a P-type layer, and a collector. The cutoff layer is disposed on the back side of the substrate, the P-type layer is disposed on the back side of the cutoff layer, and the collector is disposed on the back side of the P-type layer.
[0015] The present invention also provides a method for manufacturing an IGBT device, the method comprising the following steps: providing a substrate having a front side and a back side opposite to each other; forming a protective ring on the front side of the substrate; disposing a field oxide layer on the protective ring; and disposing a true gate and a dummy gate on a portion of the front side of the substrate; wherein, viewed from above the substrate toward the front side of the substrate, the true gate is in the form of a grid, the true gate having a plurality of grid regions, and at least one dummy gate being disposed in each grid region.
[0016] In some embodiments, after completing the step of forming a true gate and a dummy gate on the front side of a portion of the substrate, the following steps are further included: forming a P-type well layer on the front side of the substrate; forming an N-type emitter layer on the front side of the P-type well layer; forming a dielectric layer on the front side of the N-type emitter layer, the true gate, the dummy gate, and the field oxide layer; forming a via in the dielectric layer and implanting P+ to form a P+ layer, wherein the N-type emitter layer and the P+ layer are independent of each other; forming an emitter on the front side of the dielectric layer; forming a metal gate on the front side of the dielectric layer; forming a passivation layer on the front side of the emitter and the front side of the metal gate; forming a cutoff layer on the back side of the substrate; forming a P-type layer on the back side of the cutoff layer; and forming a collector on the back side of the P-type layer.
[0017] The present invention provides an IGBT device structure and manufacturing method thereof. By using a grid-like true gate, the conductive channel can be increased to reduce the on-state voltage drop. Furthermore, a dummy gate is set in the grid area of the true gate to improve the short-circuit withstand capability of the IGBT device, so that the IGBT device structure can simultaneously have low on-state voltage drop and high short-circuit withstand capability.
[0018] Other features and beneficial effects of the invention will be set forth in the following description, and some of these features and beneficial effects may be apparent from the description or learned by practicing the invention. The objects of the invention and other beneficial effects may be realized and obtained through the structures specifically pointed out in the description and other contents. Attached Figure Description
[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, some of the drawings in the following description are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0020] Figure 1 This is a planar schematic diagram of a traditional IGBT device with a strip and a dummy gate.
[0021] Figure 2 This is a planar schematic diagram of the cell region of an IGBT device provided in an embodiment of the present invention;
[0022] Figure 3 It is along Figure 2 A schematic diagram of the longitudinal section cut by the intercept line AA;
[0023] Figure 4 This is a schematic diagram of the structure of an IGBT device provided in an embodiment of the present invention;
[0024] Figure 5 This is a planar schematic diagram of the cell region of an IGBT device provided in another embodiment of the present invention;
[0025] Figure 6 This is a schematic flowchart of a manufacturing method for an IGBT device provided in an embodiment of the present invention.
[0026] Figure label:
[0027] 12-Substrate; 13-P-type well layer; 14-Guard ring; 16-Field oxide layer; 18-P+ layer; 20-True gate; 201-True gate oxide layer; 202-Mesh region; 22-Dummy gate; 222-Dummy gate oxide layer; 24-N-type emitter layer; 26-Dielectric layer; 28-Emitter; 29-Metal gate; 30-Passivation layer; 32-Stop layer; 34-P-type layer; 36-Collector; 40-Opening; 42-Connection via; 46-Cell region; 48-Termination region. Detailed Implementation
[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. The technical features designed in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.
[0029] In the description of this invention, it should be understood that the terms "center," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more. Additionally, the term "comprising" and any variations thereof mean "at least comprising."
[0030] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integrally formed connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0031] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms “a” and “an” as used herein are also intended to include the plural. It should also be understood that the terms “comprising” and / or “including” as used herein specify the presence of the stated features, integers, steps, operations, units, and / or components, without excluding the presence or addition of one or more other features, integers, steps, operations, units, components, and / or combinations thereof.
[0032] Please see Figure 2 , Figure 3 and Figure 4 , Figure 2 This is a planar schematic diagram of the cell region 46 of an IGBT device provided in an embodiment of the present invention; Figure 3 It is along Figure 2 A schematic diagram of the longitudinal section cut by the intercept line AA;
[0033] Figure 4 This is a schematic diagram of the structure of an IGBT device provided in an embodiment of the present invention. To achieve at least one or more of the aforementioned advantages, an embodiment of the present invention provides an IGBT device. As shown in the figure, the IGBT device includes a substrate 12, a P-type well layer 13, a true gate 20, and a dummy gate 22.
[0034] Substrate 12 has a front side and a back side. In this embodiment, the upper surface of substrate 12 is the front side of substrate 12, and the lower surface of substrate 12 is the back side of substrate 12. P-type well layer 13 is disposed on the front side of substrate 12. True gate 20 is disposed on the front side of substrate 12 and connected to P-type well layer 13. Dummy gate 22 is disposed on the front side of substrate 12 and connected to P-type well layer 13. The dummy gate 22 refers to a gate that is connected to emitter 28 or is floating. A floating configuration means that the dummy gate 22 does not have a gate function.
[0035] Viewed from above the IGBT device structure towards the front of the substrate 12, i.e. Figure 2As shown, the true gate 20 is in the form of a grid, and the grid-shaped true gate 20 has several grid regions 202. At least one dummy gate 22 is provided in each grid region 202. By using a grid-shaped true gate 20, the conductive channel can be increased (traditional strip channels only have conductive channels on the left and right sides), thereby reducing the on-state voltage drop. Furthermore, by providing dummy gates 22 in the grid regions 202 of the true gate 20, the short-circuit withstand capability of the IGBT device can be improved.
[0036] The IGBT device structure may also include a true gate oxide layer 201 and a dummy gate oxide layer 222. The true gate oxide layer 201 covers the true gate 20. The dummy gate oxide layer 222 connects to the dummy gate 22, and the dummy gate oxide layer 222 has an opening 40 to expose the dummy gate 22, so as to facilitate connection to the emitter 28 to form the dummy gate 22. The material of the true gate oxide layer 201 and the dummy gate oxide layer 222 includes silicon dioxide.
[0037] The IGBT device structure may also include a P+ layer 18 and an N-type emitter layer 24. The P+ layer 18 is disposed on the front side of the P-type well layer 13, and the N-type emitter layer 24 is disposed on the front side of the P-type well layer 13. The N-type emitter layer 24 and the P+ layer 18 are independent of each other.
[0038] The IGBT device structure may further include a guard ring 14, a field oxide layer 16, a dielectric layer 26, an emitter 28, a metal gate 29, and a passivation layer 30. The guard ring 14 is disposed on the front side of the substrate 12. The field oxide layer 16 is disposed on the guard ring 14. The dielectric layer 26 covers the N-type emitter layer 24, the true gate 20, the dummy gate 22, and the oxide layer, and has a via 42. The emitter 28 is disposed on the front side of the dielectric layer 26 and connects to the P+ layer 18, the N-type emitter layer 24, the P-type well layer 13, and the dummy gate 22 via the via 42. The metal gate 29 is disposed on the front side of the dielectric layer 26, and the passivation layer 30 is disposed on the front side of both the emitter 28 and the metal gate 29.
[0039] The IGBT device structure may also include a cutoff layer 32, a P-type layer 34, and a collector 36. The cutoff layer 32 is disposed on the back side of the substrate 12. The P-type layer 34 is disposed on the back side of the cutoff layer 32. The collector 36 is disposed on the back side of the P-type layer 34.
[0040] In this embodiment, the true grating 20 has four grid regions 202, and only one dummy grating 22 is set in each grid region 202. However, this embodiment is not limited to this; in some embodiments, such as... Figure 5 As shown, the true gate 20 can also have four grid regions 202, with two dummy gates 22 set in each grid region 202 to further improve the short-circuit withstand capability of the IGBT device. In addition, more dummy gates 22 can be set in each grid region 202 according to the actual situation.
[0041] The following example illustrates a specific process for manufacturing an IGBT device; however, this case is not limited to this example. The specific manufacturing process for an IGBT device is as follows:
[0042] First, a GR pattern is formed on the front side of the substrate 12 (the substrate 12 can be an N-type Float Zone Wafer). After implantation of P-type ions, a high-temperature annealing is performed to form a protective ring 14 (GR ring).
[0043] Next, a field oxide layer 16 is grown on the guard ring 14, and the required portion of the field plate position is retained by photolithography etching.
[0044] Then, trenches are formed by photomask etching, and the surface of the trenches is dry-oxidized to form a silicon dioxide gate oxide layer (including a true gate oxide layer 201 and a false gate oxide layer 222). Polysilicon is deposited on the gate oxide layer, and a true gate 20 and a false gate 22 are formed by photolithography etching.
[0045] Afterwards, P-type ions are implanted and then subjected to high-temperature annealing to form a P-type well layer 13 (Pwell region). The P-type well layer 13 is located between the real gate 20 and the dummy gate 22. Then, N-type ions are implanted by photolithography and subjected to high-temperature annealing to form an N-type emitter layer 24 (emitter 28 contacts n+ region).
[0046] Subsequently, an insulating dielectric layer 26 (ILD) is deposited on the front side of the N-type emitter layer 24, the true gate 20, the dummy gate 22 and the oxide layer. The dielectric layer 26 is then photolithographically etched to about 0.2 to 0.3 μm below the silicon surface. P-type ions are implanted to form a P+ layer 18 (the P+ layer 18 is used to form ohmic contacts) and high-temperature annealing is performed to form the connection hole 42.
[0047] Subsequently, Ti / TiN is deposited to form an ohmic contact, metal is deposited, and a metal gate 29 and an emitter 28 are formed by photolithography etching;
[0048] Then, a passivation layer 30 is deposited and photolithographically etched to form a passivation layer 30 for protection, completing the front-side process;
[0049] After completing the front-side process, the back side of the substrate 12 is ground and thinned to the required thickness. N-type ions are implanted from the back side of the substrate 12 to form a cutoff region, and then P-type ions are implanted to form a P-type layer 34 (P+ region), followed by laser annealing.
[0050] Finally, the back side is polished, cleaned, evaporated, and alloyed to form the back metal as the collector 36. The resulting IGBT device includes a cell region 46 and a termination region 48. The cell region 46 can be used to conduct current when turned on and to withstand voltage when turned off. The termination region 48 can be used to smooth the electric field by voltage division, improving the high-voltage withstand performance of the IGBT device.
[0051] Please see Figure 6 , Figure 6 This is a schematic flowchart illustrating a method for manufacturing an IGBT device according to an embodiment of the present invention. The present invention provides a method for manufacturing an IGBT device, which includes the following steps:
[0052] S10: Provide a substrate; the substrate has opposing front and back sides;
[0053] S12: A protective ring is formed on the front side of the substrate;
[0054] S14: A field oxide layer is formed on the protective ring;
[0055] S16: A true gate and a dummy gate are provided on the front side of a portion of the substrate; wherein, when viewed from above the substrate toward the front side of the substrate, the true gate is in the form of a grid, the true gate has a number of grid regions 202, and at least one dummy gate is provided in each grid region 202.
[0056] After completing step S16, the following steps may also be included:
[0057] S17: A P-type well layer is formed on the front side of the substrate;
[0058] S18: An N-type emitter layer is disposed on the front side of the P-type well layer;
[0059] S20: A dielectric layer is disposed on the front side of the N-type emitter layer, the real gate, the dummy gate, and the field oxide layer;
[0060] S22: Connecting holes are set in the dielectric layer, P+ is injected to form a P+ layer; the N-type emitter layer and the P+ layer are independent of each other;
[0061] S24: An emitter is disposed on the front side of the dielectric layer;
[0062] S26: A metal gate is disposed on the front side of the dielectric layer;
[0063] S28: A passivation layer is provided on the front side of the emitter and the front side of the metal gate;
[0064] S30: A cut-off layer is provided on the back side of the substrate;
[0065] S32: A P-type layer is provided on the back side of the stop layer;
[0066] S34: A collector electrode is provided on the back side of the P-type layer.
[0067] The formation, function, and effectiveness of the above structures can be found in the description of the IGBT device embodiments above. Furthermore, the specific materials used for the above structures can also be materials known in the art. The resulting IGBT device includes a cell region 46 and a termination region 48. The cell region 46 can be used to conduct current when turned on and to withstand voltage when turned off. The termination region 48 can be used to smooth the electric field by voltage division, improving the high-voltage withstand performance of the IGBT device.
[0068] In summary, the IGBT device structure and manufacturing method provided by the present invention can increase the conductive channel by using a grid-shaped true gate 20 to reduce the on-state voltage drop. Furthermore, a dummy gate 22 is set in the grid region 202 of the true gate 20 to improve the short-circuit withstand capability of the IGBT device, so that the IGBT device structure can simultaneously have low on-state voltage drop and high short-circuit withstand capability.
[0069] Furthermore, those skilled in the art should understand that although many problems exist in the prior art, each embodiment or technical solution of the present invention can be improved in only one or a few aspects, without necessarily solving all the technical problems listed in the prior art or the background art simultaneously. Those skilled in the art should understand that any content not mentioned in a claim should not be construed as a limitation on that claim.
[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. An IGBT device structure, characterized in that: The IGBT device structure includes: The substrate has a front side and a back side with opposite sides; A P-type well layer is disposed on the front side of the substrate; A true gate is disposed on the front side of the substrate and connected to the P-type well layer; A dummy gate is disposed on the front side of the substrate and connected to the P-type well layer; Viewed from above the IGBT device structure and facing the front of the substrate, the true gate is in the form of a grid, and the true gate has several grid regions, with at least one dummy gate disposed in each grid region; the true gate and the dummy gate are independent of each other.
2. The IGBT device structure according to claim 1, characterized in that: The IGBT device structure further includes a true gate oxide layer and a dummy gate oxide layer. The true gate oxide layer covers the true gate, and the dummy gate oxide layer connects to the dummy gate. The dummy gate oxide layer has an opening to expose the dummy gate.
3. The IGBT device structure according to claim 2, characterized in that: The materials of the true gate oxide layer and the dummy gate oxide layer include silicon dioxide.
4. The IGBT device structure according to claim 1, characterized in that: The dummy gate refers to a gate that is connected to the emitter or is floating.
5. The IGBT device structure according to claim 1, characterized in that: The true grid has four grid regions, and two dummy grids are set in each grid region.
6. The IGBT device structure according to claim 1, characterized in that: The IGBT device structure also includes a P+ layer and an N-type emitter layer. The P+ layer is disposed on the front side of the P-type well layer, and the N-type emitter layer is disposed on the front side of the P-type well layer. The N-type emitter layer and the P+ layer are independent of each other.
7. The IGBT device structure according to claim 6, characterized in that: The IGBT device structure further includes a guard ring, a field oxide layer, a dielectric layer, an emitter, a metal gate, and a passivation layer. The guard ring is disposed on the front side of the substrate. The field oxide layer is disposed on the guard ring. The dielectric layer covers the N-type emitter layer, the true gate, the dummy gate, and the field oxide layer. The dielectric layer has a connection hole. The emitter is disposed on the front side of the dielectric layer and connects to the P+ layer, the N-type emitter layer, the P-type well layer, and the dummy gate through the connection hole. The metal gate is disposed on the front side of the dielectric layer. The passivation layer is disposed on the front side of the emitter and the front side of the metal gate.
8. The IGBT device structure according to claim 7, characterized in that: The IGBT device structure further includes a cutoff layer, a P-type layer, and a collector. The cutoff layer is disposed on the back side of the substrate, the P-type layer is disposed on the back side of the cutoff layer, and the collector is disposed on the back side of the P-type layer.
9. A method for manufacturing an IGBT device structure, characterized in that: The manufacturing method of the IGBT device structure includes the following steps: A substrate is provided, the substrate having opposing front and back sides; A protective ring is formed on the front side of the substrate; A field oxide layer is formed on the protective ring; A real gate and a fake gate are disposed on the front side of a portion of the substrate; Viewed from above the substrate and facing the front of the substrate, the true gate is in the shape of a grid, the true gate has a plurality of grid regions, and at least one dummy gate is disposed in each grid region; The real gate and the fake gate are independent of each other.
10. The method for manufacturing the IGBT device structure according to claim 9, characterized in that: After completing the step of setting the real gate and the dummy gate on the front side of a portion of the substrate, the following steps are also included: A P-type well layer is formed on the front side of the substrate; An N-type emission layer is disposed on the front side of the P-type well layer; A dielectric layer is disposed on the front side of the N-type emitter layer, the true gate, the dummy gate, and the field oxide layer; A connection hole is provided in the dielectric layer, and P+ is injected to form a P+ layer. The N-type emitter layer and the P+ layer are independent of each other. An emitter is disposed on the front side of the dielectric layer; A metal gate is disposed on the front side of the dielectric layer; A passivation layer is provided on the front side of the emitter and the front side of the metal gate; A cutoff layer is provided on the back side of the substrate; A P-type layer is provided on the back side of the stop layer; A collector electrode is disposed on the back side of the P-type layer.