Semiconductor device and manufacturing method thereof

Abstract

The present invention discloses a semiconductor device and a manufacturing method thereof, which relates to the field of semiconductor technology and is used to improve the driving capability of at least a portion of the nanosheet layers in the channel region included in the ring-gate transistor, thereby facilitating the improvement of the driving performance of the ring-gate transistor. The semiconductor device comprises: a semiconductor substrate, an active structure, and a gate stack structure. The active structure is formed on the semiconductor substrate. The active structure comprises a source region, a drain region, and a channel region located between the source region and the drain region. The channel region comprises a first channel portion and a second channel portion. The first channel portion comprises at least two nanosheet layers spaced apart along the thickness direction of the semiconductor substrate. The second channel portion extends through at least one nanosheet layer from the top of the first channel portion downward. There is a gap between each nanosheet layer and the semiconductor substrate, and between the second channel portion and the semiconductor substrate. The gate stack structure surrounds the outer periphery of the channel region. The manufacturing method of the semiconductor device is used to manufacture the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] The gate stack structure included in the ring-gate transistor can be formed not only on the top of the channel region and on the sidewalls along the width direction, but also on the bottom of the channel region. Therefore, the ring-gate transistor has advantages such as higher gate control capability compared with planar transistors and fin field-effect transistors, which can improve the operating performance of semiconductor devices including the ring-gate transistor.

[0003] However, when the width of each channel portion of the channel region included in the all-around gate transistor is large, the driving performance of the all-around gate transistor is low. Summary of the Invention

[0004] The object of the present invention is to provide a semiconductor device and a manufacturing method thereof, which are used to improve the driving capability of at least a portion of the nanosheet layer in the channel region included in the all-around gate transistor, thereby facilitating the improvement of the driving performance of the all-around gate transistor.

[0005] The present invention provides a semiconductor device, which includes a semiconductor substrate, an active structure and a gate stack structure.

[0006] The active structure is formed on a semiconductor substrate. The active structure includes a source region, a drain region, and a channel region located between the source region and the drain region. The channel region includes a first channel portion and a second channel portion. The first channel portion includes at least two layers of nanosheets spaced apart along the thickness direction of the semiconductor substrate. The second channel portion extends downward through at least one layer of nanosheets from at least the top of the first channel portion. A gap exists between each layer of nanosheets and the semiconductor substrate, and between the second channel portion and the semiconductor substrate. The gate stack structure surrounds the periphery of the channel region.

[0007] Compared with the prior art, in the semiconductor device provided by the present invention, there is a gap between each layer of nanosheets included in the channel region and the semiconductor substrate, and between the second channel portion and the semiconductor substrate. Moreover, the gate stack structure can be surrounded by the gap around the periphery of the channel region, so the semiconductor device provided by the present invention is a ring-gate device to improve the gate control capability of the semiconductor device. In addition, the above-mentioned channel region includes a first channel portion and a second channel portion. Among them, the first channel portion includes at least two layers of nanosheets spaced apart and distributed along the thickness direction of the semiconductor substrate. Moreover, the second channel portion penetrates at least one layer of nanosheets from the top of the first channel portion downward. Based on this, although the width of each layer of nanosheets is relatively large, so that its crystal orientation is

[100] crystal orientation. However, each layer of nanosheets penetrated by the second channel portion can be connected to the corresponding part of the second channel portion. At this time, when the semiconductor device is in the on state, the existence of the second channel portion can increase the conductive area of the structure composed of each layer of nanosheets penetrated and the corresponding part of the second channel portion. Based on this, when the voltage applied to both ends of each layer of nanosheets along the length direction is constant, increasing the conductive area of each layer of the above-mentioned component structure can reduce the conductive resistance of the component structure, and then increase the current of each layer of nanosheets penetrated, improve the driving ability of each layer of nanosheets penetrated, and ultimately improve the driving performance of semiconductor devices.

[0008] The present invention also provides a method for manufacturing a semiconductor device, the method comprising:

[0009] A semiconductor substrate is provided.

[0010] An active structure is formed on a semiconductor substrate. The active structure includes a source region, a drain region, and a channel region located between the source and drain regions. The channel region includes a first channel portion and a second channel portion. The first channel portion includes at least two layers of nanosheets spaced apart along the thickness of the semiconductor substrate. The second channel portion extends downward from at least the top of the first channel portion through at least one layer of nanosheets. Gaps are defined between each layer of nanosheets and the semiconductor substrate, and between the second channel portion and the semiconductor substrate.

[0011] A gate stack structure is formed surrounding the periphery of the channel region.

[0012] Compared with the prior art, the beneficial effects of the method for manufacturing a semiconductor device provided by the present invention can be analyzed with reference to the beneficial effects of the semiconductor device described above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0014] Figure 1Schematic diagram of a structure after at least two stacked layers are formed on a semiconductor substrate in an embodiment of the present invention;

[0015] Figure 2 Schematic diagram of a structure after forming at least two stacked layers and a sacrificial layer on the at least two stacked layers on a semiconductor substrate according to an embodiment of the present invention;

[0016] Figure 3 A schematic diagram of a structure after a mask layer is formed in an embodiment of the present invention;

[0017] Figure 4 A longitudinal cross-sectional view of a structure after a groove is formed in an embodiment of the present invention along the width direction of the groove;

[0018] Figure 5 A longitudinal cross-sectional view of another structure after a groove is formed in an embodiment of the present invention along the width direction of the groove;

[0019] Figure 6 A longitudinal cross-sectional view of a structure after semiconductor material is formed along the width direction of a groove in an embodiment of the present invention;

[0020] Figure 7 A longitudinal cross-sectional view of a structure along the width direction of a groove after removing the mask layer in an embodiment of the present invention;

[0021] Figure 8 This is a longitudinal cross-sectional view of a structure along the width direction of a groove after the mask layer is removed and the semiconductor material is planarized in an embodiment of the present invention;

[0022] Figure 9 A longitudinal cross-sectional view of another structure after semiconductor material is formed along the width direction of the groove in an embodiment of the present invention;

[0023] Figure 10 is a longitudinal cross-sectional view along the width direction of the groove of another structure after removing the mask layer in an embodiment of the present invention;

[0024] Figure 11 This is a longitudinal cross-sectional view along the width direction of the groove of another structure after the mask layer is removed and the semiconductor material is planarized in an embodiment of the present invention;

[0025] Figure 12 Schematic diagram of a first structure after forming fins on a semiconductor substrate in an embodiment of the present invention;

[0026] Figure 13 Schematic diagram of a second structure after forming fins on a semiconductor substrate in an embodiment of the present invention;

[0027] Figure 14 Part (1) of Figure 13The structure shown is a longitudinal cross-sectional view of the structure along the A-A' direction; Figure 14 Part (2) of Figure 13 The structure shown is a longitudinal cross-sectional view along the B-B' direction;

[0028] Figure 15 Schematic diagram of a third structure after forming fins on a semiconductor substrate according to an embodiment of the present invention;

[0029] Figure 16 Part (1) of Figure 15 The structure shown is a longitudinal cross-sectional view of the structure along the A-A' direction; Figure 16 Part (2) of Figure 15 The structure shown is a longitudinal cross-sectional view along the B-B' direction;

[0030] Figure 17 Schematic diagram of a structure after a fin structure is formed on a semiconductor substrate in an embodiment of the present invention;

[0031] Figure 18 A schematic diagram of a structure after forming a sacrificial gate in an embodiment of the present invention;

[0032] Figure 19 A schematic diagram of a structure after forming a gate sidewall in an embodiment of the present invention;

[0033] Figure 20 Part (1) is a schematic diagram of a longitudinal cross-section of the structure along the length direction of the fin structure and at the stacking position after the gate sidewall is formed in an embodiment of the present invention; Figure 20 Part (2) is a schematic diagram of a longitudinal cross-section of the structure along the length direction of the fin structure and at the semiconductor material after the gate sidewall is formed in an embodiment of the present invention;

[0034] Figure 21 Part (1) is a schematic diagram of a longitudinal cross-section of the structure along the length direction of the fin structure and at the stacking position after removing the portions of the fin structure located in the first and second regions in an embodiment of the present invention;

[0035] Figure 21 Part (2) is a schematic diagram of a longitudinal cross-section of the structure at the semiconductor material along the length direction of the fin structure after removing the portions of the fin structure located in the first region and the second region in an embodiment of the present invention;

[0036] Figure 22 Part (1) is a schematic diagram of a longitudinal cross-section of the structure along the length direction of the fin structure and at the stacking position after the source region and the drain region are formed in an embodiment of the present invention; Figure 22 Part (2) is a schematic diagram of a longitudinal cross-section of the structure at the semiconductor material along the length direction of the fin structure after the source region and the drain region are formed in an embodiment of the present invention;

[0037] Figure 23 Part (1) is a schematic diagram of a longitudinal cross-section of the structure along the length direction of the fin structure and at the stacking position after the dielectric layer is formed in an embodiment of the present invention; Figure 23 Part (2) is a schematic diagram of a longitudinal cross-section of the structure along the length direction of the fin structure and at the semiconductor material after the dielectric layer is formed in an embodiment of the present invention;

[0038] Figure 24 Part (1) is a schematic longitudinal cross-sectional view of the structure at the first channel portion along the length direction of the channel region after the channel region is formed in an embodiment of the present invention; Figure 24 Part (2) is a schematic longitudinal cross-sectional view of the structure at the second channel portion along the length direction of the channel region after the channel region is formed in an embodiment of the present invention;

[0039] Figure 25 Part (1) is a schematic longitudinal cross-sectional view of the structure along the length direction of the channel region and at the first channel portion after the gate stack structure is formed in an embodiment of the present invention; Figure 25 Part (2) is a schematic longitudinal cross-sectional view of the structure along the length direction of the channel region and at the second channel portion after the gate stack structure is formed in an embodiment of the present invention;

[0040] Figure 26 Part (1) is a schematic diagram of a longitudinal cross-section of a structure along the width direction of the channel region after forming a gate stack structure in an embodiment of the present invention; Figure 26 Part (2) is a schematic longitudinal cross-sectional view of another structure along the width direction of the channel region after forming the gate stack structure in an embodiment of the present invention;

[0041] Figure 27 A flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention.

[0042] Figure numerals: 11 is a semiconductor substrate, 12 is a stacked layer, 121 is a sacrificial layer, 122 is a channel layer, 13 is a mask layer, 14 is a groove, 15 is a semiconductor material, 16 is a fin, 17 is a shallow trench isolation structure, 18 is a fin-shaped structure, 181 is a first region, 182 is a second region, 183 is a third region, 19 is a sacrificial gate, 20 is a gate sidewall, 21 is a source region, 22 is a drain region, 23 is a dielectric layer, 24 is a channel region, 241 is a first channel portion, 242 is a second channel portion, and 25 is a gate stack structure. DETAILED DESCRIPTION

[0043] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely illustrative and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0044] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments of the present disclosure. These figures are not drawn to scale, and for the purpose of clarity, certain details are exaggerated and certain details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0045] In the context of this disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intervening layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, it may be "below" the other layer / element when the orientation is reversed. To further clarify the technical problems, technical solutions, and beneficial effects to be solved by the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are intended solely to explain the present invention and are not intended to limit the present invention.

[0046] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined. "Several" means one or more, unless otherwise specifically defined.

[0047] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and may encompass internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0048] The gate stack structure included in the ring-gate transistor can be formed not only on the top of the channel region and on the sidewalls along the width direction, but also on the bottom of the channel region. Therefore, the ring-gate transistor has advantages such as higher gate control capability compared with planar transistors and fin field-effect transistors, which can improve the operating performance of semiconductor devices including the ring-gate transistor.

[0049] However, when the width of each channel portion of the channel region included in the ring-gate transistor is large, the driving performance of the ring-gate transistor is poor. Specifically, because the width of the channel region included in the existing fin field-effect transistor is relatively small and the height is relatively large, the crystal orientation of the channel region included in the fin field-effect transistor is usually a

[110] crystal orientation. When the width of each channel portion of the channel region included in the ring-gate transistor is large, the crystal orientation of the channel region is a

[100] crystal orientation. The carrier mobility of the channel region with a

[100] crystal orientation is lower than the carrier mobility of the channel region with a

[110] crystal orientation, resulting in the driving performance of the ring-gate transistor with a

[100] crystal orientation channel region being lower than the driving performance of the fin field-effect transistor with a

[110] crystal orientation channel region. For example: when the material of the nanosheet included in the P-type ring-gate transistor is silicon, and the material of the nanosheet included in the N-type ring-gate transistor is a high-mobility material, the carrier mobility of the channel region included in the above-mentioned P-type ring-gate transistor and the above-mentioned N-type ring-gate transistor is lower than the carrier mobility of the channel region in the

[110] crystal orientation, thereby resulting in a decrease in the driving performance of the above-mentioned P-type ring-gate transistor and the above-mentioned N-type ring-gate transistor.

[0050] To address the aforementioned technical issues, embodiments of the present invention provide a semiconductor device and a method for manufacturing the same. In the semiconductor device provided by the embodiments of the present invention, a second channel portion included in a channel region extends downward from at least one nanosheet layer from the top of the first channel portion, thereby increasing the current flowing through each nanosheet layer and improving the driving capability of each nanosheet layer, ultimately enhancing semiconductor driving performance.

[0051] like Figure 25 (1) and (2) of Figure 26 As shown in parts (1) and (2) of the figure, the semiconductor device provided by the embodiment of the present invention includes: a semiconductor substrate 11, an active structure and a gate stack structure 25. The above-mentioned active structure is formed on the semiconductor substrate 11. The active structure includes a source region 21, a drain region 22, and a channel region 24 located between the source region 21 and the drain region 22. The channel region 24 includes a first channel portion 241 and a second channel portion 242. The first channel portion 241 has at least two layers of nanosheets spaced apart along the thickness direction of the semiconductor substrate 11. The second channel portion 242 penetrates at least one layer of nanosheets from the top of the first channel portion 241 downward. There is a gap between each layer of nanosheets and the semiconductor substrate 11, and between the second channel portion 242 and the semiconductor substrate 11. The gate stack structure 25 surrounds the periphery of the channel region 24.

[0052] Specifically, the specific structure of the above-mentioned semiconductor substrate can be set according to the actual application scenario. For example: the semiconductor substrate can be a semiconductor substrate such as a silicon substrate, a silicon germanium substrate, a germanium substrate, a silicon-on-insulator substrate, etc. on which no other structures are formed. For another example: if the semiconductor device provided in the embodiment of the present invention is applied to the second layer or higher layer semiconductor device included in the integrated circuit, the semiconductor substrate can at least include a semiconductor substrate, a first layer device structure formed on the semiconductor substrate, and a dielectric layer covering the first layer device structure. In this case, the materials of the various parts included in the semiconductor substrate can be set according to actual needs, as long as they can be applied to the semiconductor device provided in the embodiment of the present invention.

[0053] For the above-mentioned gate stack structure, since there is a gap between each layer of nanosheets included in the channel region and the semiconductor substrate, and between the second channel portion and the semiconductor substrate, and the gate stack structure can surround the periphery of the channel region through the gap, the semiconductor device provided by the embodiment of the present invention is a ring gate device to improve the gate control capability of the semiconductor device. The gate stack structure includes a gate dielectric layer and a gate located on the gate dielectric layer. The gate dielectric layer at least surrounds the periphery of the channel region. Or, as Figure 26 As shown in parts (1) and (2) of FIG. 1 , a gate dielectric layer may also be formed between the gate and the semiconductor substrate 11. Specifically, the material of the gate dielectric layer may be an insulating material with a low dielectric constant, such as silicon oxide or silicon nitride, or an insulating material with a high dielectric constant, such as HfO2, ZrO2, TiO2, or Al2O3. The material of the gate may be a conductive material, such as polysilicon, TiN, TaN, or TiSiN.

[0054] Regarding the active structure described above, the materials of the source, drain, and channel regions included in the active structure can be semiconductor materials such as silicon, silicon-germanium, germanium, or Group III-V compounds. Specifically, the materials of the source and drain regions can be the same or different. When the materials of the source and drain regions are the same, they can be formed simultaneously in a unified operation step, simplifying the manufacturing process of the semiconductor device. Furthermore, the materials of the first and second channel portions included in the channel region can be the same. For example, the materials of the first and second channel portions can both be silicon. Alternatively, the materials of the first and second channel portions included in the channel region can be different. For example, the material of the first channel portion can be silicon, and the material of the second channel portion can be silicon-germanium. Because different channel materials have different carrier mobilities, when the materials of the first and second channel portions are different, the driving capability of the channel region can be controlled by adjusting the material type and size of the second channel portion, thereby improving the applicability of the semiconductor device provided by the embodiments of the present invention in different application scenarios.

[0055] Structurally, the first channel portion can include only two layers of nanosheets, or three or more. The specific number of nanosheets in the first channel portion and the specific specifications of each nanosheet layer can be set according to actual needs and are not specifically limited here.

[0056] As for the second channel portion included in the above-mentioned channel region, Figure 26 As shown in parts (1) and (2) of FIG, the second channel portion 242 penetrates at least one layer of nanosheet from the top of the first channel portion 241 downward. Figure 26 As shown in part (1) of FIG. 1 , the top height of the second channel portion 242 may be greater than the top height of the first channel portion 241. Alternatively, as shown in FIG. Figure 26 As shown in part (2), the top height of the second channel portion 242 may also be equal to the top height of the first channel portion 241. The specific height of the second channel portion 242 can be set according to actual needs and is not specifically limited here.

[0057] It is worth noting that Figure 26 As shown in parts (1) and (2) of the figure, although the width of each layer of nanosheets is larger than that of nanowires with smaller widths, the crystal orientation of each layer of nanosheets is

[100] . However, each layer of nanosheets penetrated by the second channel portion 242 can be connected to the corresponding portion of the second channel portion 242. At this time, when the semiconductor device provided by the embodiment of the present invention is in the on state, the presence of the second channel portion 242 can increase the conductive area of the structure composed of each layer of nanosheets penetrated and the corresponding portion of the second channel portion 242. Based on this, when the voltage applied to both ends of each layer of nanosheets along the length direction is constant, increasing the conductive area of each layer of the structure can reduce the conductive resistance of the structure, thereby increasing the current of each layer of nanosheets penetrated, improving the driving ability of each layer of nanosheets penetrated, and ultimately improving the driving performance of the semiconductor device.

[0058] In the above case, the number of nanosheet layers that the second channel portion penetrates can be determined based on the number of nanosheet layers whose driving capability is to be improved in the actual application scenario. For example, when only the driving capability of the nanosheet located at the upper portion of the first channel portion needs to be improved, Figure 5 As shown, the second channel portion may only penetrate at least one layer of nanosheets located on the upper portion of the first channel portion. Figure 26 As shown in parts (1) and (2), when it is necessary to improve the driving capability of all layers of nanosheets in the first channel portion 241 , the second channel portion 242 penetrates all layers of nanosheets included in the first channel portion 241 .

[0059] In addition, it can be understood that, within a certain range, the larger the cross-sectional area of the second channel portion, the higher the degree of improvement in the driving capability of the nanosheet penetrated by the second channel portion. Therefore, the formation range of the second channel portion can be determined based on the requirements for the degree of improvement in the driving capability of the corresponding nanosheet in the actual scenario.

[0060] As for the length extension direction of the second channel portion, it can be set according to the actual application scenario and is not specifically limited here.

[0061] In one example, Figure 12 ,as well as Figure 25 As shown in parts (1) and (2) of FIG, the second channel portion 242 may extend along the length direction of the first channel portion 241 (the direction being parallel to the length direction of the gate stack structure 25). In this case, as Figure 12 ,as well as Figure 25 As shown in parts (1) and (2) of FIG, the length of the second channel portion 242 can be equal to the length of the first channel portion 241. Figure 26 As shown in parts (1) and (2) of FIG, along the width direction of the first channel portion 241, the second channel portion 242 separates the corresponding layer of nanosheets into two parts. The width direction of the first channel portion 241 is parallel to the width direction of the gate stack structure 25. In this case, Figure 12 As shown, when forming the semiconductor material 15 for manufacturing the second channel portion, the semiconductor material 15 can be formed to have a length equal to the length of the fin structure 18. Based on this, when manufacturing the gate stack structure, there is no need to strictly require manufacturing conditions and precision in order to align the gate stack structure with the second channel portion of a fixed length and a fixed position, thereby reducing the difficulty of manufacturing the gate stack structure.

[0062] Alternatively, the length of the second channel portion may be smaller than the length of the first channel portion.

[0063] In another example, Figure 15 ,as well as Figure 16 As shown in (1) and (2) of FIG, the second channel portion may also extend along the width direction of the first channel portion. In this case, Figure 15 ,as well as Figure 16 As shown in parts (1) and (2) of FIG, the length of the second channel portion may be equal to the width of the first channel portion. Alternatively, the length of the second channel portion may be smaller than the width of the first channel portion.

[0064] In one example, Figure 25 (1) and (2) of Figure 26As shown in parts (1) and (2) of the figure, the semiconductor device further includes a shallow trench isolation structure 17, a gate sidewall 20 and a dielectric layer 23. The shallow trench isolation structure 17 is formed on the semiconductor substrate 11 to isolate the different active areas of the semiconductor substrate 11 to prevent leakage. The thickness of the shallow trench isolation structure 17 can be set according to actual conditions. The material of the shallow trench isolation structure 17 can be an insulating material such as SiN, Si3N4, SiO2 or SiCO. The gate sidewall 20 is formed at least on both sides of the gate stack structure 25 along the length direction to isolate the gate included in the gate stack structure 25 from other conductive structures formed subsequently, thereby improving the electrical characteristics of the semiconductor device. The material of the gate sidewall 20 can be an insulating material such as silicon oxide or silicon nitride. The dielectric layer 23 covers the semiconductor substrate 11, and its top is flush with the top of the gate stack structure 25. During the actual manufacturing process, the presence of the dielectric layer 23 can protect the source region 21 and the drain region 22 from being affected by subsequent operations such as removing the portion of the sacrificial layer located in the third region, thereby improving the yield of the semiconductor device. The dielectric layer 23 can be made of an insulating material such as silicon oxide or silicon nitride.

[0065] In one example, the semiconductor device may further include an inner sidewall (not shown). The inner sidewall is formed between the gate stack structure and the source region, and between the gate stack structure and the drain region, to define the length of the gate stack structure. The material of the inner sidewall may be an insulating material such as silicon oxide or silicon nitride.

[0066] like Figure 27 As shown, the embodiment of the present invention also provides a method for manufacturing a semiconductor device. Figures 1 to 26 The manufacturing process is described by using a perspective view or a cross-sectional view of the operation shown. Specifically, the manufacturing method of the semiconductor device includes the following steps:

[0067] First, a semiconductor substrate is provided. The structure and material of the semiconductor substrate can be referred to above and will not be described in detail here.

[0068] like Figure 24 As shown in parts (1) and (2) of FIG, an active structure is formed on a semiconductor substrate 11. The active structure includes a source region 21, a drain region 22, and a channel region 24 located between the source region 21 and the drain region 22. The channel region 24 includes a first channel portion 241 and a second channel portion 242. The first channel portion 241 has at least two layers of nanosheets spaced apart along the thickness direction of the semiconductor substrate 11. The second channel portion 242 penetrates at least one layer of nanosheets from at least the top of the first channel portion 241 downward. There is a gap between each layer of nanosheets and the semiconductor substrate 11, and between the second channel portion 242 and the semiconductor substrate 11.

[0069] Specifically, the specific structure and materials of the source region, drain region and channel region included in the active structure can be found in the previous text and will not be repeated here.

[0070] In actual application, the above-mentioned formation of the active structure on the semiconductor substrate may include the following steps:

[0071] like Figure 1 As shown, at least two stacked layers 12 are formed on the semiconductor substrate 11 along the thickness direction of the semiconductor substrate 11 . Each stacked layer 12 includes a sacrificial layer 121 and a channel layer 122 located on the sacrificial layer 121 .

[0072] Specifically, the channel layer is a film layer used to manufacture the nanosheets included in the first channel portion, so the number of layers of the stack formed on the semiconductor substrate, as well as the material and thickness of the channel layer, can be determined based on the number of nanosheets included in the first channel portion, as well as the material and thickness of the nanosheets. The sacrificial layer is used to form a gap between two adjacent nanosheets, as well as a gap between the bottom nanosheet and the semiconductor substrate, so the thickness of the sacrificial layer can be determined based on the specifications of the gate stack structure. In addition, the material of the sacrificial layer can be any semiconductor material that is different from the material of the channel layer. For example: in the case where the material of the channel layer is Si, the material of the sacrificial layer can be Si 0.6 Ge 0.4 wait.

[0073] In actual application, the above-mentioned stacked layers can be formed by using processes such as epitaxial growth.

[0074] In addition, if Figure 2 As shown, after forming the at least two stacked layers 12, an additional sacrificial layer 121 can be formed on the at least two stacked layers 12 using a process such as epitaxial growth. Based on this, since the film layer at the top of the at least two stacked layers 12 is the channel layer 122, forming another sacrificial layer 121 on the at least two stacked layers 12 can protect the channel layer 122 located below it from being affected during subsequent operations such as forming a fin structure, thereby improving the quality of the nanosheets formed based on the channel layer 122 and further improving the driving performance of the semiconductor device. The specific thickness of the sacrificial layer 121 located at the top can be set according to actual needs and is not specifically limited here.

[0075] Of course, if in actual application, the quality requirements for the top channel layer are relatively low, or the subsequent formation of the fin structure and other operations have little impact on the top channel layer, the above-mentioned sacrificial layer at the top may not be formed.

[0076] like Figures 6 to 11 As shown, a second channel portion is formed in at least two stacked layers 12. Figure 17 As shown, a fin structure 18 is formed on a semiconductor substrate 11 based on at least two stacked layers 12 having a second channel portion. The fin structure 18 includes a second channel portion. Along the length of the fin structure 18, the fin structure 18 has a first region 181, a second region 182, and a third region 183 located between the first region 181 and the second region 182.

[0077] Specifically, as mentioned above, the top height of the second channel portion is greater than or equal to the top height of the first channel portion. Moreover, the channel layer in the at least two stacked layers is a film layer for manufacturing nanosheets, so the top height of the at least two stacked layers formed on the semiconductor substrate is equal to the top height of the nanosheet located at the top layer (i.e., the top height of the first channel portion). Based on this, when the top height of the second channel portion is equal to the top height of the first channel portion, it is necessary to form the second channel portion in the at least two stacked layers, and the top of the second channel portion is flush with the top of the channel layer located at the top layer. When the top height of the second channel portion is greater than the top height of the first channel portion, the second channel portion is not only formed in the at least two stacked layers, but also protrudes from the channel layer located at the top layer.

[0078] In addition, the formation position of the second channel portion in the at least two stacked layers can be determined according to the formation position of the second channel portion on the semiconductor substrate in the finally obtained semiconductor device.

[0079] In actual application, Figure 13 ,as well as Figure 14 As shown in parts (1) and (2) of FIG, only semiconductor material 15 having the same specifications as the second channel portion can be formed in at least two stacked layers 12. In this case, the semiconductor material 15 is the second channel portion.

[0080] Or, as Figure 12 As shown, in the case where the length extension direction of the second channel portion is parallel to the length direction of the gate stack structure, and the length of the second channel portion is equal to the length of the first channel portion; or Figure 15 ,as well as Figure 16 As shown in parts (1) and (2) of FIG, in the case where the length extension direction of the second channel portion is parallel to the width direction of the gate stack structure and the length of the second channel portion is equal to the width of the first channel portion, a semiconductor material 15 can also be formed to separate the corresponding channel layer 122 and the sacrificial layer 121 in the at least two stacked layers 12 into two parts along the corresponding direction. In this case, the portion of the semiconductor material 15 located in the third region is the second channel portion.

[0081] For example, the step of forming the second channel portion in at least two stacked layers may include the following steps: Figure 3 As shown, a mask layer 13 is formed on a portion of at least two stacked layers 12. Figure 4 and Figure 5 As shown, under the masking effect of the mask layer 13, the at least two stacked layers 12 are patterned to form grooves 14 in the mask layer 13 and the at least two stacked layers 12. The depth of the grooves 14 is less than the sum of the thicknesses of the mask layer 13 and the at least two stacked layers 12. Figures 6 to 24 As shown, a semiconductor material 15 is formed to fill the groove, and a second channel portion 242 is formed based on the semiconductor material 15 .

[0082] Specifically, chemical vapor deposition and photolithography processes can be used to form the mask layer. The exposed area of the mask layer corresponds to the area formed by the semiconductor material. The material of the mask layer can be silicon nitride, polysilicon or amorphous silicon. In addition, Figure 3 As shown in FIG, if a sacrificial layer 121 is formed on at least two stacked layers 12 before forming the mask layer 13, the mask layer 13 is formed on a portion of the sacrificial layer 121. If a sacrificial layer is not formed on at least two stacked layers before forming the mask layer, the mask layer is formed on a portion of the at least two stacked layers. Figure 4 and Figure 5 As shown, dry etching or wet etching can be used to pattern at least two stacked layers 12 to form grooves 14. The specifications of the grooves 14 are the same as those of the semiconductor materials described above. Figure 6 and Figure 9 As shown, the semiconductor material 15 that fills the groove can be formed by processes such as epitaxial growth and chemical mechanical polishing. Finally, the manufacturing process of forming the second channel portion based on the semiconductor material 15 can be determined according to the height of the second channel portion. According to whether a sacrificial layer 121 is formed on at least two stacked layers 12 and the top height of the second channel portion, the formation of the second channel portion based on the semiconductor material 15 is divided into at least the following three cases:

[0083] The first type: no sacrificial layer is formed on the at least two stacked layers, and the top height of the second channel portion is equal to the top height of the first channel portion. In this case, the mask layer is directly formed on the at least two stacked layers. The portion of the semiconductor material protruding from the top channel layer is located within the mask layer. Based on this, the above-mentioned formation of the second channel portion based on the semiconductor material includes the following steps: Figure 10 As shown, the mask layer is removed by wet etching or dry etching. At this time, the portion of the semiconductor material 15 protruding from the top channel layer 122 is exposed. Figure 11 As shown, the semiconductor material 15 can then be planarized using a process such as chemical mechanical polishing to remove the portion of the semiconductor material 15 protruding from at least two stacked layers 12. At this point, the top of the remaining portion of the semiconductor material 15 is flush with the top of the top channel layer 122.

[0084] The second type: no sacrificial layer is formed on the at least two stacked layers, and the top height of the second channel portion is greater than the top height of the first channel portion. In this case, the mask layer is directly formed on the at least two stacked layers, and the portion of the semiconductor material protruding from the top channel layer is located within the mask layer. Based on this, the above-mentioned formation of the second channel portion based on the semiconductor material only includes the following steps: Figure 10 As shown, the mask layer is removed by wet etching or dry etching. At this time, the portion of the semiconductor material 15 protruding from the top channel layer 122 is retained, so that the top height of the second channel portion formed based on the semiconductor material 15 can be greater than the top height of the first channel portion.

[0085] The third method is to form a sacrificial layer on at least two stacked layers. In this case, the mask layer is formed on a portion of the sacrificial layer located on the top layer. Based on this, the second channel portion formed based on the semiconductor material includes the following steps: Figure 7 As shown, the mask layer is removed by wet etching or dry etching. Alternatively, the second channel portion formed based on the semiconductor material 15 includes the following steps: Figure 7 As shown in FIG, a wet etching or dry etching process is first used to remove the mask layer. Figure 8 As shown, the semiconductor material 15 is planarized by using processes such as chemical mechanical polishing to remove the portion of the semiconductor material 15 protruding from the sacrificial layer 121 on the top layer.

[0086] It should be noted that in the third case above, if Figure 4 and Figure 5 As shown, the groove 14 penetrates the mask layer 13, the top sacrificial layer 121, and the at least two stacked layers 12 including a portion of the channel layer 122 and a portion of the sacrificial layer 121. Figures 6 to 8 As shown, because the semiconductor material 15 completely fills the groove, the height of the semiconductor material 15 is equal to the depth of the groove. Based on this, regardless of whether only the mask layer 13 is removed or the exposed portion of the semiconductor material 15 is planarized after removing the mask layer 13, the top of the semiconductor material 15 after the two types of operations in the third case is at least flush with the top of the sacrificial layer 121 located on the top layer. The top height of the sacrificial layer 121 located on the top layer is greater than the top height of the channel layer 122 located on the top layer. Therefore, the top height of the second channel portion formed by the semiconductor material 15 after the two types of operations in the third case is greater than the top height of the first channel portion.

[0087] Then, a technique such as self-aligned double imaging can be used to form a corresponding mask layer on the sacrificial layer located on the top layer. Figures 12 to 16As shown in parts (1) and (2) of FIG, and under the masking action of the corresponding mask layer, the sacrificial layer 121 located on the top layer, the at least two stacked layers 12, and a portion of the semiconductor substrate 11 are etched to form a fin 16 on the semiconductor substrate 11. Alternatively, when the sacrificial layer is not formed on the at least two stacked layers, it is necessary to etch the at least two stacked layers and a portion of the semiconductor substrate to form a fin on the semiconductor substrate. Then, as Figure 17 As shown, a shallow trench isolation structure 17 can be formed on the semiconductor substrate 11 using processes such as chemical vapor deposition and etching. The top height of the shallow trench isolation structure 17 is less than or equal to the bottom height of the sacrificial layer 121 located at the bottom. The portion of the fin exposed outside the shallow trench isolation is a fin-shaped structure 18.

[0088] In actual applications, a replacement gate process is often used to form a gate stack structure included in a semiconductor device to improve the quality of the gate stack structure. In this case, after forming the shallow trench isolation structure and before performing subsequent operations, the manufacturing method of the semiconductor device further includes the following steps:

[0089] like Figures 18 to 20 As shown in parts (1) and (2) of the present invention, chemical vapor deposition and etching processes can be used to form a sacrificial gate 19 and a gate sidewall 20 across the portion of the fin structure 18 corresponding to the third region 183. The gate sidewall 20 is formed on at least two sides of the sacrificial gate 19 along the length direction. The material of the sacrificial gate 19 can be polysilicon or other materials. The material and specifications of the gate sidewall 20 can be referred to above and will not be repeated here.

[0090] like Figure 21 and Figure 22 As shown in parts (1) and (2) of FIG, the portion of the fin structure located in the first region and the portion located in the second region are processed to form a source region 21 and a drain region 22 .

[0091] In actual application, the ion implantation process can be used to directly process the portion of the fin structure located in the first region and the second region under the masking effect of the sacrificial gate and the gate sidewall to form the source region and the drain region. Figure 21 As shown in parts (1) and (2) of FIG, the portion of the fin structure located in the first region and the second region can be removed by dry etching or wet etching under the masking effect of the sacrificial gate 19 and the gate sidewall 20. Figure 22 As shown in parts (1) and (2), a source region 21 and a drain region 22 may be formed along both sides of the length of the portion of the fin structure corresponding to the third region by using a source-drain epitaxial method.

[0092] like Figure 23As shown in parts (1) and (2) of FIG. 1 , a dielectric layer 23 covering the semiconductor substrate 11 can be formed by processes such as chemical vapor deposition and chemical mechanical polishing. The top of the dielectric layer 23 is flush with the top of the sacrificial gate 19. The material of the dielectric layer 23 can be referred to above and will not be described again here.

[0093] Then, a dry etching process or a wet etching process may be used to remove the sacrificial gate to expose the portion of the fin structure corresponding to the third region, thereby facilitating subsequent operations.

[0094] like Figure 24 As shown, a dry etching process or a wet etching process may be used to remove the portion of each sacrificial layer located in the third region, so that each channel layer 122 forms a corresponding layer of nanosheets to obtain a first channel portion 241 .

[0095] like Figure 25 (1) and (2) of Figure 26 As shown in parts (1) and (2), atomic layer deposition and other processes can be used to form a gate stack structure 25 surrounding the periphery of the channel region 24. The structure and material of the gate stack structure 25 can be referred to above and will not be repeated here.

[0096] Compared with the prior art, the beneficial effects of the method for manufacturing a semiconductor device provided by an embodiment of the present invention can be analyzed by referring to the beneficial effects of the semiconductor device provided by the above embodiment, and will not be repeated here.

[0097] While the above description does not provide detailed technical details regarding patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0098] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which are intended to fall within the scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: semiconductor substrates, An active structure is formed on the semiconductor substrate; the active structure includes a source region, a drain region, and a channel region located between the source region and the drain region; the channel region includes a first channel portion and a second channel portion; the first channel portion includes at least two layers of nanosheets spaced apart along the thickness direction of the semiconductor substrate; the second channel portion extends downward through at least one layer of the nanosheets from at least the top of the first channel portion; a gap is formed between each layer of the nanosheets and the semiconductor substrate, and between the second channel portion and the semiconductor substrate; A gate stack structure surrounds the periphery of the channel region through the gap.

2. The semiconductor device according to claim 1, wherein The length of the second channel portion is equal to the length of the first channel portion; along the width direction of the first channel portion, the second channel portion separates the corresponding layer of the nanosheet into two parts; wherein, The length directions of the first channel portion and the second channel portion are both parallel to the length direction of the gate stack structure; and the width direction of the first channel portion is parallel to the width direction of the gate stack structure.

3. The semiconductor device according to claim 1 or 2, wherein: The first channel portion and the second channel portion are made of different materials.

4. A method for manufacturing a semiconductor device, characterized in that: include: providing a semiconductor substrate; An active structure is formed on the semiconductor substrate; the active structure includes a source region, a drain region, and a channel region located between the source region and the drain region; the channel region includes a first channel portion and a second channel portion; the first channel portion includes at least two layers of nanosheets spaced apart along the thickness direction of the semiconductor substrate; the second channel portion extends downward through at least one layer of the nanosheets from at least the top of the first channel portion; a gap is defined between each layer of the nanosheets and the semiconductor substrate, and between the second channel portion and the semiconductor substrate; A gate stack structure surrounding the periphery of the channel region is formed through the gap.

5. The method for manufacturing a semiconductor device according to claim 4, wherein: The active structure is formed on the semiconductor substrate, comprising: At least two stacked layers are formed on at least the semiconductor substrate along a thickness direction of the semiconductor substrate; each stacked layer includes a sacrificial layer and a channel layer located on the sacrificial layer; forming the second channel portion at least in the at least two stacked layers; A fin structure is formed on the semiconductor substrate based on at least the at least two stacked layers having the second channel portion formed therein; the fin structure includes the second channel portion; along a length direction of the fin structure, the fin structure has a first region, a second region, and a third region located between the first region and the second region; The portion of each sacrificial layer located in the third region is removed, so that each channel layer forms a corresponding layer of nanosheets, thereby obtaining the first channel portion.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: The forming of the second channel portion at least in the at least two stacked layers comprises: forming a mask layer on a partial region of the at least two stacked layers; Under the masking action of the mask layer, patterning the at least two stacked layers to form grooves in the mask layer and the at least two stacked layers; the depth of the grooves is less than the sum of the thicknesses of the mask layer and the at least two stacked layers; A semiconductor material is formed to fill the groove, and the second channel portion is formed based on the semiconductor material.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The forming of the second channel portion based on the semiconductor material includes: removing the mask layer; The semiconductor material is planarized to remove the portion of the semiconductor material protruding from the at least two stacked layers; wherein the portion of the semiconductor material located in the third region is the second channel portion, and the top height of the second channel portion is equal to the top height of the first channel portion.

8. The method for manufacturing a semiconductor device according to claim 6, wherein: The forming of the second channel portion based on the semiconductor material includes: The mask layer is removed; wherein the portion of the semiconductor material located in the third region is the second channel portion, and the top height of the second channel portion is greater than the top height of the first channel portion.

9. The method for manufacturing a semiconductor device according to claim 6, wherein: The step of forming at least two stacked layers on at least the semiconductor substrate comprises: forming the at least two stacked layers on the semiconductor substrate, and the sacrificial layer on the at least two stacked layers; The forming of the mask layer on the partial area of the at least two stacked layers is: forming the mask layer on the partial area of the sacrificial layer located on the top layer; The forming of the second channel portion based on the semiconductor material includes: removing the mask layer; or, the forming of the second channel portion based on the semiconductor material includes: removing the mask layer; and performing a planarization process on the semiconductor material to remove a portion of the semiconductor material protruding from the sacrificial layer located on the top layer; wherein, The portion of the semiconductor material located in the third region is the second channel portion, and a top height of the second channel portion is greater than a top height of the first channel portion.

10. The method for manufacturing a semiconductor device according to claim 5, wherein: After forming a fin structure on the semiconductor substrate based on at least the at least two stacked layers having the second channel portion formed thereon, and before removing the portion of each sacrificial layer located in the third region, the method for manufacturing a semiconductor device further includes: forming a sacrificial gate and a gate spacer spanning a portion of the fin-shaped structure corresponding to the third region; the gate spacer is formed at least on both sides of the sacrificial gate along the length direction; Processing portions of the fin structure located in the first region and the second region to form the source region and the drain region; forming a dielectric layer covering the semiconductor substrate; wherein the top of the dielectric layer is flush with the top of the sacrificial gate; The sacrificial gate is removed.

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