Transistors, power amplifiers and electronic devices

Abstract

This application provides a transistor, a power amplifier, and an electronic device. The transistor includes an AlN barrier layer and an AlGaN layer and a SiN layer stacked on top of an AlGaN layer. Because the AlGaN layer can form an AlGaN / AlN composite barrier with the AlN barrier layer, and the SiN layer can form a SiN / AlN composite barrier with the AlN barrier layer, the transistor of this application is an enhancement-mode transistor, which avoids safety issues caused by leakage when the transistor is not operating. Furthermore, since the SiN layer is an insulating material and partially covers the AlN barrier layer, it can act as a surface passivation layer, further providing the transistor with higher safety performance.

Description

Technical Field

[0001] This application relates to the field of electronic device technology, and more particularly to a transistor, a power amplifier, and an electronic device. Background Technology

[0002] With the development of mobile technology, higher requirements have been placed on devices such as power amplifiers in mobile terminals such as mobile phones, requiring power amplifiers to have higher safety performance and faster response speed. Summary of the Invention

[0003] This application provides a transistor, a power amplifier, and an electronic device, wherein the power amplifier made from the transistor has high safety performance and fast response speed.

[0004] In a first aspect, this application provides a transistor. The transistor includes a channel layer, an AlN barrier layer, an AlGaN layer, a SiN layer, a gate, a source, and a drain. The AlN barrier layer, the source, and the drain are all stacked on the channel layer, with the source and drain spaced apart. The source and drain are both disposed on the surface of the channel layer facing the AlN barrier layer, and the AlN barrier layer is located between the spaced-apart source and drain. The SiN layer and the AlGaN layer are both stacked on the side of the AlN barrier layer facing away from the channel layer. The SiN layer includes a first portion and a second portion spaced apart. The first portion of the SiN layer covers a second region of the AlN barrier layer, and the second portion of the SiN layer covers a third region of the AlN barrier layer. The AlGaN layer is disposed between the spaced-apart first and second portions, and is adjacent to both the first and second portions. The AlGaN layer covers the first region of the AlN barrier layer. The gate is stacked on the side of the AlGaN layer facing away from the AlN barrier layer and is in Schottky contact with the AlGaN layer.

[0005] In this embodiment, both the SiN layer and the AlGaN layer are stacked on the side of the AlN barrier layer away from the channel layer. The SiN layer includes a first portion and a second portion spaced apart, and the AlGaN layer is disposed between the first portion and the second portion, adjacent to both portions. In other words, the AlN barrier layer includes a first region, a second region, and a third region, with the first region connected between the second and third regions. The AlGaN layer covers the first region of the AlN barrier layer, the first portion of the SiN layer covers the second region of the AlN barrier layer, and the second portion of the SiN layer covers the third region of the AlN barrier layer. In this embodiment, an AlGaN / AlN composite barrier can be formed between the AlGaN layer and the first region of the AlN barrier layer, a SiN / AlN composite barrier can be formed between the first portion of the SiN layer and the second region of the AlN barrier layer, and a SiN / AlN composite barrier can also be formed between the second portion of the SiN layer and the third region of the AlN barrier layer. Because the conduction band of the SiN / AlN composite barrier is below the Fermi level, the corresponding channel is a depletion-type channel, which is always in the open state and always contains a two-dimensional electron gas. Since the conduction band of the AlGaN / AlN composite barrier is above the Fermi level, the corresponding channel is an enhancement-type channel. Therefore, only when the gate voltage applied to the gate of the AlGaN layer is positive and greater than the transistor's turn-on voltage can conductive electrons be induced in the enhancement-type channel, forming a two-dimensional electron gas. At this time, the two-dimensional electron gas can flow within the channel layer, the transistor is in the open state, and data signal transmission can occur between the source and drain. When the gate voltage applied to the gate of the AlGaN layer is negative or less than the transistor's turn-on voltage, conductive electrons cannot be induced in the enhancement-type channel. At this time, the transistor is in the closed state, and data signal transmission cannot occur between the source and drain. In this application, since the channel corresponding to the AlGaN / AlN composite barrier is an enhancement-type channel and the SiN / AlN composite barrier is a depletion-type channel, the transistor is in the off state when no gate voltage is applied or the applied gate voltage is small, thereby avoiding safety issues caused by leakage when the transistor is not working, and thus having higher safety performance.

[0006] Furthermore, due to the presence of a SiN layer stacked on the surface of the AlN barrier layer facing away from the channel layer, the SiN layer enhances the polarization effect between the AlN barrier layer and the channel layer at the contact points with the SiN layer. This allows for the generation of more electrons within the channel layer at the location corresponding to the SiN / AlN composite barrier, forming a higher-density two-dimensional electron gas. Moreover, since the SiN layer is an insulating material, its partial coverage of the AlN barrier layer provides surface passivation, thereby reducing leakage current at the source and drain surfaces and resulting in higher safety performance for the transistor.

[0007] Furthermore, in this embodiment, the gate is in Schottky contact with the AlGaN layer, eliminating the need for a dielectric layer on the side of the gate facing the AlGaN layer, thus simplifying the transistor fabrication process. In other embodiments, such as insulated-gate field-effect transistors (MISFETs) with an insulating gate dielectric layer, the probability of charge trapping in the insulating gate dielectric layer is high during the switching process between the gate being in the on state (with an on-state voltage applied) and the off state (without a voltage applied to the gate, or with a voltage applied less than the on-state voltage, or with a negative voltage applied to the gate), affecting the transistor's switching speed and output power. In contrast, this embodiment uses a gate metal electrode in Schottky contact with the underlying electrode, eliminating the need for an insulating gate dielectric layer. Therefore, there are no easily trapped charges in the insulating gate dielectric layer, resulting in faster transistor switching speeds and improved long-term device stability.

[0008] In some embodiments of this application, the thickness of the SiN layer is greater than the thickness of the AlGaN layer, and a trench is formed between the first part of the SiN layer, the AlGaN layer, and the second part of the SiN layer. The bottom wall of the trench is the AlGaN layer, and the two opposite sidewalls of the trench are the first part of the SiN layer and the second part of the SiN layer, respectively.

[0009] In some embodiments of this application, the gate includes a first block filled in a trench, and the length of the first block of the gate is 200±100nm.

[0010] The gate length is typically the most significant factor affecting the transistor's operating frequency; a shorter gate length results in a higher operating frequency. In this embodiment, the gate length is the distance between the first portion and the second portion of the SiN layer. In this embodiment, the gate length is the length of the first block of the gate. The length of the first block is 200±100nm, enabling the transistor to be suitable for high-frequency signal transmission. For example, in some embodiments of this application, the transistor is suitable for operation in sub-6G and millimeter-wave 5G bands. Furthermore, the smaller distance between the source and drain also reduces the channel resistance between them, lowering the transistor's operating voltage.

[0011] In some embodiments, the gate further includes a second block located outside the trench and stacked on the side of the first block facing away from the AlGaN layer. The length of the second block is greater than the length of the first block, meaning the gate has a "T"-shaped cross-section. By setting the gate's cross-section to a "T"-shaped structure, the gate's cross-sectional area can be larger than that of a rectangular gate, thereby reducing the gate's transmission resistance and achieving better signal transmission performance. Furthermore, since the first block of the gate fills the trench, meaning the gate makes Schottky contact with the AlGaN layer, a dielectric layer is not required on the side of the gate facing the AlGaN layer. This reduces fabrication steps and improves the long-term stability of the transistor.

[0012] In some embodiments, the AlGaN layer has a thickness of 2-5 nm. In the embodiments of this application, when the AlGaN layer thickness is 2-5 nm, the thickness-to-length ratio of the AlGaN layer is small, which can avoid the short-channel effect. Furthermore, because the AlGaN layer is thinner and shorter, the transistor size can be smaller, thus meeting the requirements for use in small electronic devices.

[0013] In some embodiments, the length of the first portion of the SiN layer is 200±100nm, and the length of the second portion of the SiN layer is 200±100nm. The lengths of the first and second portions may be the same or different. In the embodiments of this application, the lengths of both the first and second portions of the SiN layer are relatively small, thereby enabling a smaller distance between the source and drain, and also enabling a smaller channel resistance between the source and drain, thus reducing the operating voltage of the transistor.

[0014] In some embodiments, the thickness of the SiN layer is 10-30 nm. In this embodiment, the thickness of the SiN layer is 10-30 nm. When a SiN layer is stacked on top of an AlN barrier layer, the SiN layer can enhance the polarization effect of band distortion in the AlN barrier layer and the channel, thereby enabling the generation of more electrons in the channel corresponding to the SiN / AlN composite barrier, forming a higher density two-dimensional electron gas, which can reduce the operating voltage between the source and drain, i.e., reduce the operating voltage of the transistor.

[0015] In some embodiments, the source includes a first n-type heavily doped GaN layer and a source metal electrode. The first n-type heavily doped GaN layer is in contact with the channel layer, and the source metal electrode is stacked on the side of the first n-type heavily doped GaN layer away from the channel layer. The Hall concentration of the first n-type heavily doped GaN layer is greater than 1E20.

[0016] By stacking a first n-type heavily doped GaN layer on the channel layer, and then stacking a source metal electrode on the first n-type heavily doped GaN layer, the contact resistance between the first n-type heavily doped GaN layer and the channel layer is smaller compared to directly stacking the source metal electrode on the channel layer, thereby reducing the operating voltage of the transistor. In some embodiments of this application, the Hall concentration of the first n-type heavily doped GaN layer is greater than 1E20 to ensure that the first n-type heavily doped GaN layer has good conductivity and ensures the signal transmission performance of the transistor.

[0017] In some embodiments, the source includes a second n-type heavily doped GaN layer and a drain metal electrode. The second n-type heavily doped GaN layer is in contact with the channel layer, and the drain metal electrode is stacked on the side of the second n-type heavily doped GaN layer away from the channel layer. The Hall concentration of the second n-type heavily doped GaN layer is greater than 1E20.

[0018] By stacking a second n-type heavily doped GaN layer on the channel layer, and then stacking a source metal electrode on the second n-type heavily doped GaN layer, the contact resistance between the second n-type heavily doped GaN layer and the channel layer is smaller compared to directly stacking the source metal electrode on the channel layer, thereby reducing the operating voltage of the transistor. In some embodiments of this application, the Hall concentration of the second n-type heavily doped GaN layer is greater than 1E20 to ensure that the second n-type heavily doped GaN layer has good conductivity and ensures the signal transmission performance of the transistor.

[0019] In some embodiments, the first n-type heavily doped GaN layer and the second n-type heavily doped GaN layer are formed of GaN material doped with n-type material or InGaN material doped with n-type material.

[0020] In some implementations, the transistor also includes a back barrier layer located on the side of the channel layer away from the AlN barrier layer. The barrier of the back barrier layer is higher than that of the channel layer. The back barrier improves the confinement characteristics of the charge carriers and has a better suppression effect on the leakage current of the device's buffer layer.

[0021] In some embodiments of this application, the channel layer is a GaN channel layer, which can be deposited from GaN material. In some embodiments of this application, the thickness of the channel layer is 20nm-40nm. In this embodiment, by stacking a SiN layer on the AlN barrier layer, more electrons are generated in the channel corresponding to the SiN / AlN composite barrier, forming a higher density two-dimensional electron gas, thereby enabling the flow of a sufficiently dense two-dimensional electron device even when the channel layer is relatively thin.

[0022] In this embodiment, the transistor includes a GaN channel layer, an AlN barrier layer, and an AlGaN layer, meaning the transistor in this embodiment is a GaN-based transistor. Compared to typical GaAs-based transistors, power amplifiers made from GaN-based transistors can transmit and process radio frequency signals with a wider bandwidth. In some embodiments, this transistor can transmit and process radio frequency signals with a bandwidth greater than 2 GHz.

[0023] In some embodiments, the transistor further includes a substrate, on which a channel layer is stacked, the substrate being a high-resistivity silicon material, and the sheet resistance of the substrate being greater than 10,000 ohms / sq.

[0024] In some embodiments, the transistor further includes a first buffer layer stacked on the substrate. The first buffer layer is used to modulate the stress between the layer structure on the side of the first buffer layer away from the substrate and the substrate, to prevent the effects caused by excessive stress, and to avoid or mitigate the problem of thermal stress generated between the substrate and the layer structure stacked on it due to the different degrees of expansion or contraction between the substrate and the layer structure stacked on it during the heating or annealing process of manufacturing the transistor, thereby causing the substrate and the layer structure stacked on it to crack, warp excessively or separate.

[0025] In some embodiments, the transistor further includes a second buffer layer stacked on the side of the first buffer layer facing away from the substrate. The second buffer layer modulates the stress between the layer structure on the side of the second buffer layer facing away from the first buffer layer and the first buffer layer, thereby avoiding or mitigating problems such as cracking, excessive warping, or separation caused by differences in the degree of expansion or contraction between the layer structure on the side of the second buffer layer facing away from the first buffer layer and the first buffer layer during the heating or annealing process of transistor fabrication. In some embodiments, the layer structure on the side of the second buffer layer facing away from the first buffer layer is a back barrier layer.

[0026] In some implementations, the AlN barrier layer is formed of AlN material or indium-doped AlN material.

[0027] In some implementations, the Al composition in the AlGaN layer is 50% ± 10%, which ensures a sufficiently large polarization effect between the AlGaN / AlN composite barrier and GaN. At the same time, when no voltage is applied to the gate electrode, the conduction band at its interface is above the Fermi level, ensuring that the channel region corresponding to the AlGaN / AlN composite barrier is enhancement-mode.

[0028] In some embodiments of this application, notches are provided on opposite sides of the surface of the channel layer facing the AlN barrier layer, with the source and drain each disposed within one notch. Since the two-dimensional electron gas generated within the channel layer tends to accumulate more at the boundary between the channel layer and the AlN barrier layer, by placing the source and drain within the notches of the channel layer facing the AlN barrier layer in these embodiments, better electrical connection between the source / drain and the two-dimensional electron gas within the channel layer can be ensured, thereby guaranteeing the signal transmission effect between the source and drain of the transistor.

[0029] Secondly, this application provides a power amplifier, which includes a package structure and the aforementioned transistor, wherein the transistor is packaged within the package structure to protect the transistor through the package structure.

[0030] Because the transistors of this application have higher safety performance and faster response speed, power amplifiers including the transistors of this application can also have higher safety performance and faster signal processing speed.

[0031] Thirdly, this application provides an electronic device including an antenna and the aforementioned power amplifier, wherein the power amplifier is used to amplify radio frequency signals and the antenna is used to transmit the amplified radio frequency signals.

[0032] Since the power amplifier of this application can also have higher safety performance and faster signal processing speed, electronic devices including the power amplifier can have higher safety performance and faster processing speed for radio frequency signals. Attached Figure Description

[0033] To more clearly illustrate the structural features and effects of this application, a detailed description is provided below in conjunction with the accompanying drawings and specific embodiments.

[0034] Figure 1 This is a schematic diagram of the structure of an electronic device according to one embodiment of this application.

[0035] Figure 2 for Figure 1 The diagram shows the radio frequency signal transmission principle of the electronic device.

[0036] Figure 3 This is a cross-sectional schematic diagram of a transistor according to one embodiment of this application.

[0037] Figure 4 for Figure 3 The diagram shows the conduction band structure of the SiN / AlN composite barrier in the transistor.

[0038] Figure 5 for Figure 3The diagram shows the conduction band structure of the AlGaN / AlN composite barrier in the transistor.

[0039] Figure 6 When the transistor is in the off state, Figure 3 The diagram shows the state of the transistor.

[0040] Figure 7 When the transistor is in the ON state, Figure 3 The diagram shows the state of the transistor. Detailed Implementation

[0041] The technical solutions of various embodiments of this application will now be described with reference to the accompanying drawings.

[0042] This application provides an electronic device including a wireless communication module capable of receiving or transmitting signals. In this application, the electronic device can be a router, mobile phone, tablet, wearable device, aircraft, vehicle antenna, or various other electronic devices. This application primarily uses a mobile phone as an example to describe the electronic device.

[0043] Please see Figure 1 , Figure 1 The diagram shows a structural schematic of an electronic device 1000 according to one embodiment of this application. In this embodiment, the electronic device 1000 includes an antenna 1001 and a radio frequency signal transmission module 1002. The radio frequency signal transmission module 1002 can be connected to the antenna 1001. External radio frequency signals received by the antenna 1001 can be transmitted to the radio frequency signal transmission module 1002, and after processing by the radio frequency signal transmission module 1002, transmitted to other structures of the electronic device 1000; or, data signals transmitted by other structures of the electronic device 1000 can be transmitted through the antenna 1001 after being processed by the radio frequency signal transmission module 1002.

[0044] In some embodiments of this application, the electronic device 1000 further includes a frame 1003. In some embodiments, the frame 1003 can be a metal frame, and a portion of the metal frame can serve as a radiator of the antenna 1001, thereby reducing the internal space occupied by the antenna 1001 in the electronic device 1000. It is understood that in other embodiments of this application, the frame 1003 can also be made of other materials, or it can simply serve as an antenna support for the radiator of the antenna 1001. For example, in some embodiments, the frame 1003 is a plastic frame, and the radiator of the antenna 1001 is fixed to the inner wall surface of the frame 1001, so that the frame 1003 serves as an antenna support for the antenna 1001. It is understood that in other embodiments of this application, the electronic device 1000 can also include a rear cover and a front cover, and a portion of the rear cover or a portion of the front cover can also serve as a radiator of the antenna 1001 or as an antenna support for the antenna 1001.

[0045] Please see Figure 2 , Figure 2 As shown Figure 1 The diagram illustrates the radio frequency (RF) signal transmission principle of the electronic device 1000. In this embodiment, the RF signal transmission module 1002 includes a power amplifier 100, a processor 200, an RF transceiver 300, and an RF front-end 400. In the RF signal transmission direction, the data processed by the processor 200 is transmitted to the RF transceiver 300, modulated by the RF transceiver 300, and then sent to the power amplifier 100 for power amplification. After the RF front-end 400 performs transmit / receive switching, the data is sent to the antenna 1001 for signal transmission. In the RF signal reception direction, the RF signal in space is received by the antenna 1001, and after the RF front-end 400 performs transmit / receive switching, filtering, and amplification, it is transmitted to the RF transceiver 300 for demodulation to obtain the baseband signal, which is then sent to the processor 200 for further processing.

[0046] In this embodiment, the power amplifier 100 includes a transistor 101 and a package structure for encapsulating the transistor 101. In some embodiments, the power amplifier also includes other circuits and electrical components electrically connected to the transistor 101, enabling the power amplifier 100 to perform power amplification. Please refer to [link to relevant documentation]. Figure 3 , Figure 3The diagram shown is a cross-sectional view of a transistor 101 according to one embodiment of this application. In this embodiment, the transistor 101 includes a channel layer 10, an AlN barrier layer 20, an AlGaN layer 30, a SiN layer 40, a source 50, a drain 60, and a gate 70. The AlN barrier layer 20, the source 50, and the drain 60 are all stacked on the channel layer 10. Specifically, the source 50 and the drain 60 are spaced apart at opposite edges of the channel layer 10, and the AlN barrier layer 20 is located between the spaced-apart source 50 and drain 60. Furthermore, in this embodiment, the AlN barrier layer 20 is adjacent to the source 50 and the drain 60; in other words, opposite sides of the AlN barrier layer 20 are in contact with the source 50 and the drain 60, respectively. The SiN layer 40 and the AlGaN layer 30 are both stacked on the side of the AlN barrier layer 20 facing away from the channel layer 10. In this embodiment, the SiN layer 40 includes a first portion 41 and a second portion 42 spaced apart, and the AlGaN layer 30 is disposed between the spaced-apart first portion 41 and second portion 42. Furthermore, in this embodiment, the AlGaN layer 30 is adjacent to the first portion 41 and the second portion 42 of the SiN layer 40; in other words, opposite sides of the AlGaN layer 30 are in contact with the first portion 41 and the second portion 42, respectively. Also, in this embodiment, the source electrode 50 is located on the side of the first portion 41 of the SiN layer 40 facing away from the AlGaN layer 30, and the first portion 41 of the SiN layer 40 is in contact with the source electrode 50; the drain electrode 60 is located on the side of the second portion 42 of the SiN layer 40 facing away from the AlGaN layer 30, and the second portion 42 of the SiN layer 40 is in contact with the drain electrode 60.

[0047] In this embodiment, a two-dimensional electron gas (2-DEG) can be formed within the channel layer 10. Specifically, in this embodiment, the 2-DEG can be formed at the interface position near the AlN barrier layer in the channel layer 10. The 2-DEG flows within the channel layer 10, thereby turning on the source 50 and drain 50 of the transistor 101, allowing the transistor 101 to operate. In this embodiment, the channel layer 10 is relatively thin, which allows for a thinner transistor 101, enabling miniaturization of the power amplifier 100, suitable for use in miniaturized electronic devices 1000. In some embodiments of this application, the thickness of the channel layer 10 can be 20-40 nm. In this embodiment, the channel layer 10 is a GaN channel layer, meaning that the channel layer 10 can be obtained by depositing GaN material through methods such as metal-organic chemical vapor deposition (MOCVD). It should be noted that the GaN material in this application can be a binary material formed by combining Ga and N elements in a certain proportion. It is understood that in some other embodiments of this application, the channel layer 10 may also be formed of other materials.

[0048] In some embodiments of this application, notches are provided on opposite sides of the surface of the channel layer 10 facing the AlN barrier layer 20. In this embodiment, the notches on opposite sides of the surface of the channel layer 10 facing the AlN barrier layer 20 are notch 11 and notch 12, respectively. The source 50 is disposed in notch 11, and the drain 60 is disposed in notch 12. Since the two-dimensional electron gas generated in the channel layer 10 tends to accumulate more at the boundary position of the channel layer 10 facing the AlN barrier layer 20, by disposing the source 50 and drain 60 within the notches of the channel layer 10 facing the AlN barrier layer 20 in this embodiment of the application, a better electrical connection between the source 50, drain 60 and the two-dimensional electron gas in the channel layer 10 can be ensured, thereby ensuring the signal transmission effect between the source 50 and drain 60 of the transistor 101.

[0049] In this embodiment, the channel layer 10 includes a first region I, a second region II, and a third region III, with the first region I connecting the second region II and the third region III. Specifically, the region of the channel layer 10 opposite to the AlGaN layer 30 is the first region I, the region of the channel layer 10 opposite to the first portion 41 of the SiN layer 40 is the second region II, and the region of the channel layer 10 opposite to the second portion 42 of the SiN layer 40 is the third region III.

[0050] In this embodiment, the AlN barrier layer 20 can be deposited from pure AlN material using methods such as MOCVD. It is understood that in other embodiments of this application, the AlN barrier layer 20 can also be deposited from In-doped AlN material. It should be noted that when the AlN barrier layer 20 is formed from pure AlN material, the forming material can be a binary material formed by combining Al and N elements in a certain proportion; when the AlN barrier layer 20 is an In-doped AlN material, the forming material can be a ternary material formed by combining In, Al, and N elements in a certain proportion. In this embodiment, the thickness of the AlN barrier layer 20 can also be relatively thin, thereby allowing for a thinner transistor 101, enabling miniaturization of the power amplifier 100, suitable for use in miniaturized electronic devices 1000. In some embodiments of this application, the thickness of the AlN barrier layer 20 can be 2-5 nm.

[0051] In this embodiment, the AlN barrier layer 20 includes a first region 21, a second region 22, and a third region 23, with the first region 21 connected between the second region 22 and the third region 23. The AlGaN layer 30 covers the first region 21 of the AlN barrier layer 20, and the first region 21 of the AlN barrier layer 20 covers the first region I of the channel layer 10. The first portion 41 of the SiN layer 40 covers the second region 22 of the AlN barrier layer 20, and the second region 22 of the AlN barrier layer 20 covers the second region II of the channel layer 10. The second portion 42 of the SiN layer 40 covers the third region 23 of the AlN barrier layer 20, and the third region 23 of the AlN barrier layer 20 covers the third region III of the channel layer 10. The AlGaN layer 30 can form an AlGaN / AlN composite barrier with the first region 21 of the AlN barrier layer 20. The SiN layer 40 can form a SiN / AlN composite barrier with the second region 22 and the third region 23 of the AlN barrier layer 20.

[0052] It should be noted that in this embodiment, there are no clear boundaries between the first region 21, the second region 22, and the third region 23 of the AlN barrier layer 20; they are simply different parts defined artificially for the sake of description. Specifically, in this embodiment, the portion of the AlN barrier layer 20 covered by the AlGaN layer 30 is the first region 21 of the AlN barrier layer 20, the portion of the AlN barrier layer 20 covered by the first portion 41 of the SiN layer 40 is the second region 22 of the AlN barrier layer 20, and the portion of the AlN barrier layer 20 covered by the second portion 42 of the SiN layer 40 is the third region 23 of the AlN barrier layer 20. In this embodiment, the channel layer 10 includes the first region I, the second region II, and the third region III; there are no clear boundaries between them; they are simply different parts defined artificially for the sake of description. Specifically, in this embodiment, the portion of the channel layer 10 covered by the second region 22 of the AlN barrier layer 20 is the second region II of the channel layer 10, and the portion of the channel layer 10 covered by the third region 23 of the AlN barrier layer 20 is the third region III of the channel layer 10. In this embodiment, the SiN layer 40 is deposited from SiN material. It should be noted that the SiN material in this application can be a binary material formed by combining Si and N elements in a certain proportion. In this embodiment, since the SiN layer 40 is an insulating material layer, the first portion 41 of the SiN layer 40 covers the second region 22 of the AlN barrier layer 20, and the second portion 42 of the SiN layer 40 covers the third region 23 of the AlN barrier layer 20. That is, the SiN layer 40 partially covers the AlN barrier layer 20, and the SiN layer 40 can play a surface passivation role, thereby reducing the leakage current on the surfaces of the source 50 and the drain 60, so that the transistor 101 can have higher safety performance.

[0053] In this embodiment, the AlGaN layer 30 can be formed by depositing AlGaN material. It should be noted that the AlGaN material can be a ternary material formed by combining Al, Ga, and N elements in a certain proportion. The thickness of the AlGaN layer 30 can be relatively thin; in some embodiments of this application, the thickness of the AlGaN layer 30 can be 2-5 nm. In this embodiment, when the thickness of the AlGaN layer 30 is small, the length L1 of the AlGaN layer 30 can also be small. A smaller ratio of the thickness of the AlGaN layer 30 to its length L1 can avoid short-channel effects in the channel region corresponding to the AlGaN layer 30 (i.e., the first region I of the channel layer 10), thereby ensuring the stability of the gate operation and gate voltage control of the transistor 101. In some embodiments of this application, the length of the AlGaN layer 30 can be 200±100 nm, and the ratio of the thickness of the AlGaN layer 30 to its length L1 can be less than 0.1. Furthermore, because the AlGaN layer 30 is thin and short, the transistor 101 can be smaller in size, thus enabling its use in small electronic devices. It should be noted that in this embodiment, the length L1 of the AlGaN layer 30 is the distance between the first portion 41 and the second portion 42 of the SiN layer 40.

[0054] The SiN layer 40 is thicker than the AlGaN layer 30. In some embodiments of this application, the thickness of the SiN layer 40 can be 10-30 nm. In the embodiments of this application, by stacking a SiN layer 40 of a certain thickness on the AlN barrier layer, the polarization effect of band distortion in the channel regions (i.e., the second region II and the third region III) corresponding to the AlN barrier layer 20 and the SiN layer 40 can be strengthened, thereby enabling the generation of more electrons in the channel regions (i.e., the second region II and the third region III) corresponding to the SiN / AlN composite barrier, forming a higher density two-dimensional electron gas. This reduces the operating voltage between the source 50 and the drain 60, i.e., reduces the operating voltage of the transistor 101, making the transistor 101 more suitable for use in miniaturized electronic devices such as mobile phones and wearable devices.

[0055] In this embodiment, the length L2 of the first portion 41 and the length L3 of the second portion 42 of the SiN layer 40 can both be 200±100nm. The length L2 of the first portion 41 of the SiN layer 40 is the distance between the AlGaN layer 30 and the source 50, and the length L2 of the second portion 42 of the SiN layer 40 is the distance between the AlGaN layer 30 and the drain 60. In this embodiment, the lengths L2 of the first portion 41 and L3 of the second portion 42 of the AlGaN layer 30 and the SiN layer 40 are all relatively small, meaning the distance between the source 50 and the drain 60 is small. This also reduces the channel resistance between the source 50 and the drain 60, thereby lowering the operating voltage of the transistor 101. In some embodiments of this application, the operating voltage of the transistor 101 can be less than 10V, making it more suitable for use in miniaturized devices such as mobile phones and wearable devices.

[0056] In this embodiment, since the SiN layer 40 is thicker than the AlGaN layer 30, specifically the first portion 41 and the second portion 42 of the SiN layer 40 are both thicker than the AlGaN layer 30, a trench 43 is formed between the first portion 41 of the SiN layer 40, the AlGaN layer 30, and the second portion 42 of the SiN layer 40. In some embodiments of this application, the gate 70 includes a first block 71 and a second block 72 connected together. The first block 71 fills the trench 43 and makes Schottky contact with the AlGaN layer 30. The second block 72 of the gate 70 is located outside the trench 43, and the length L4 of the second block 72 is longer than the length L5 of the portion located inside the trench 43. That is, the cross-section of the gate 70 is a "T" shaped structure, and a portion of the second block 72 of the gate 70 is stacked on the SiN layer 40. In this embodiment, by setting the cross-section of the gate 70 to a "T" shape, the cross-sectional area of ​​the gate 70 can be larger than that of a rectangular cross-section, thereby reducing the transmission resistance of the gate 70 and achieving better signal transmission performance.

[0057] It should be noted that in the embodiments of this application, there is no obvious boundary between the first block 71 and the second block 72; they are simply different parts defined artificially for the sake of description. Specifically, in the embodiments of this application, the portion of the gate 70 located within the trench 43 is the first block 71, and the portion of the gate 70 located outside the trench 43 is the second block 72.

[0058] In this embodiment, the first block 71 of the gate 70 is located between the first portion 41 and the second portion 42 of the SiN layer 40, and the length L4 of the first block 71 of the gate 70 is the same as the length L1 of the AlGaN layer 30. Typically, the length of the gate 70 is the biggest factor affecting the operating frequency of the transistor 101; the shorter the gate length 70, the higher the operating frequency of the transistor 101. In this embodiment, the length of the gate 70 is the length L4 of the first block 71, which is basically the same as the length L1 of the AlGaN layer 30, at 200±100nm. In this embodiment, because the length of the gate 70 is relatively short, the operating frequency of the transistor 101 can be relatively high. In some embodiments of this application, the power amplifier 100 made of the transistor 101 can meet the requirements of sub-6G and millimeter-wave 5G frequency band operation, satisfying the current needs of high-frequency signal transmission.

[0059] Please see Figure 4 and Figure 5 , Figure 4 As shown Figure 3 The diagram shows the conduction band structure of the SiN / AlN composite barrier in transistor 101. Figure 5 As shown Figure 3 The conduction band structure diagram of the AlGaN / AlN composite barrier in transistor 101 is shown. Please refer to [link / reference]. Figure 4 In this embodiment, a SiN / AlN composite barrier is formed between the first portion 41 of the SiN layer 40 between the gate 70 and the source 50 and the second region 22 of the AlN barrier layer 20. Similarly, a SiN / AlN composite barrier is formed between the second portion 42 of the SiN layer 40 between the gate 70 and the drain 60 and the third region 23 of the AlN barrier layer 20. Since the conduction band of the SiN / AlN composite barrier is below the Fermi level, the channel region corresponding to the SiN / AlN composite barrier (i.e., the second region II and the third region III of the channel layer 10) is a depletion-type channel and is always in a normally open state. A two-dimensional electron gas can be formed within the channel region corresponding to the SiN / AlN composite barrier (i.e., the second region II and the third region III of the channel layer 10).

[0060] Please see Figure 5In this embodiment, the AlGaN layer 30 can form an AlGaN / AlN composite barrier with the first region 21 of the AlN barrier layer 20. Since the conduction band of the AlGaN / AlN composite barrier is located above the Fermi level, a two-dimensional electron gas cannot be formed in the channel region corresponding to the AlGaN / AlN composite barrier (i.e., the first region I of the channel layer 10) when no voltage is applied to the gate 70. Therefore, the channel region corresponding to the AlGaN / AlN composite barrier (i.e., the first region I of the channel layer 10) belongs to the enhancement-mode channel. When the gate voltage applied to the gate 70 stacked on the AlGaN layer 30 is positive and less than the turn-on voltage of the transistor 101, or when the gate voltage applied to the gate 70 stacked on the AlGaN layer 30 is negative, no electrons are induced in the enhancement-mode channel, and the conductive electrons in the channel layer cannot flow between the source 50 and the drain 60. At this time, the transistor 101 is in the off state and does not work. Please refer to [link to relevant documentation]. Figure 6 , Figure 6 When transistor 101 is in the off state, Figure 3 The diagram shows the state of transistor 101. In this embodiment, when transistor 101 is in the off state, since the channel regions corresponding to the SiN / AlN composite barrier (i.e., the second region II and the third region III of the channel layer 10) are depletion-type channels, two-dimensional electron gases 101 and 102 can be induced to form at the interfaces of the second region II and the third region III of the channel layer 10 near the AlN barrier layer 20. However, since the first region I of the channel layer 10 is an enhancement-mode channel, and the gate voltage applied to the gate 70 is positive and less than the turn-on voltage of the transistor 101, or the gate voltage applied to the gate 70 stacked on the AlGaN layer 30 is negative, a two-dimensional electron gas cannot be induced to form in the first region I of the channel layer 10. As a result, the source 50 and drain 60 of the transistor 101 cannot be turned on, and the transistor 101 is in a closed state, preventing the transmission of signals between the source 50 and drain 60. When the gate voltage applied to the gate 70 stacked on the AlGaN layer 30 is positive and greater than the turn-on voltage of the transistor 101, conductive electrons are induced in the enhancement-mode channel. Furthermore, since the channel regions corresponding to the SiN / AlN composite barrier (i.e., the second region II and the third region III of channel layer 10) are depletion-type channels and are always in the normally open state, when the gate voltage applied to the gate 70 stacked on the AlGaN layer 30 is positive and greater than the turn-on voltage of transistor 101, a two-dimensional electron gas can be induced to form in the first region I of channel layer 10. The two-dimensional electron gas in the first region I of channel layer 10 can connect with the two-dimensional electron gases in the second region II and the third region III of channel layer 10. Thus, the conductive electrons in the two-dimensional electron gas in channel layer 10 can flow under the drive of the operating voltage applied between the source 50 and the drain 60, thereby enabling transistor 101 to operate. Please refer to [link to relevant documentation]. Figure 7 , Figure 7When transistor 101 is in the ON state, Figure 3 The diagram shows the state of transistor 101. In this embodiment, when transistor 101 is in the ON state, since the second region II and the third region III of the channel layer 10 of transistor 101 are depletion-type channels, two-dimensional electron gases 101 and 102 can be induced at the interfaces of the second region II and the third region III of the channel layer 10 near the AlN barrier layer 20. The first region I of the channel layer 10 is an enhancement-type channel, and the gate voltage loaded on the gate 70 is positive and greater than the turn-on voltage of transistor 101. Two-dimensional electron gases 103 can also be induced in the first region I of the channel layer 10, so that the source 50 and the drain 60 of transistor 101 can conduct, transistor 101 is in the ON state, and signal transmission can be performed between the source 50 and the drain 60.

[0061] The transistor 101 in this embodiment is an enhancement-mode transistor 101, meaning that when no gate voltage 70 is applied to the transistor 101, the transistor 101 is in a turned-off state; when a gate voltage 70 exceeding the turn-on voltage of the transistor 101 is applied to the transistor 101, the transistor 101 is in a turned-on state, thereby avoiding safety issues caused by leakage when the transistor 101 is not working.

[0062] In this embodiment, the Al content in the AlGaN layer 30 is approximately 50% ± 10%, which makes the polarization effect of the AlGaN / AlN composite barrier and the GaN channel sufficiently strong. This ensures that the conduction band of the AlGaN / AlN composite barrier is above the Fermi level, that the channel corresponding to the AlGaN / AlN composite barrier is an enhancement channel, and that the surface cracking problem caused by excessive surface stress due to the high Al content in the AlGaN layer 30 is avoided.

[0063] Please refer to it again. Figure 3In some embodiments of this application, the source electrode 50 may include a first n-type heavily doped GaN layer 51 and a source metal electrode 52 stacked together. The first n-type heavily doped GaN layer 51 is in contact with the channel layer 10, and the source metal electrode 52 is stacked on the side of the first n-type heavily doped GaN layer 51 away from the channel layer 10. In this embodiment, the first n-type heavily doped GaN layer 51 can be formed by GaN material doped with n-type materials such as Ge and Si. In this embodiment, by stacking the first n-type heavily doped GaN layer 51 on the channel layer 10 and then stacking the source metal electrode 52 on the first n-type heavily doped GaN layer 51, compared with the method of directly stacking the source metal electrode 52 on the channel layer 10, the contact resistance between the first n-type heavily doped GaN layer 51 and the channel layer 10 is smaller, thereby reducing the operating voltage of the transistor 101 and saving the power consumption of the transistor 101. In some embodiments of this application, the Hall concentration of the first n-type heavily doped GaN layer 51 is greater than 1E20 to ensure that the first n-type heavily doped GaN layer 51 has good conductivity and ensures the signal transmission effect of the transistor 101. Similarly, in this embodiment, the drain 60 may include a second n-type doped GaN layer 61 and a drain metal electrode 62 stacked together. The second n-type heavily doped GaN layer 61 is in contact with the channel layer 10, and the drain metal electrode 62 is stacked on the side of the second n-type heavily doped GaN layer 61 away from the channel layer 10. In this embodiment, the second n-type heavily doped GaN layer 61 can be formed by GaN material doped with n-type materials such as Ge and Si. In this embodiment, an n-type heavily doped GaN layer 61 is stacked on the channel layer 10, and then a drain metal electrode 62 is stacked on the second n-type heavily doped GaN layer 61. Compared to directly stacking the drain metal electrode 62 on the channel layer 10, the contact resistance between the second n-type heavily doped GaN layer 61 and the channel layer 10 is smaller, thereby reducing the operating voltage of the transistor 101 and saving the power consumption of the transistor 101. In some embodiments of this application, the Hall concentration of the n-type heavily doped GaN layer 61 is greater than 1E20 to ensure that the n-type heavily doped GaN layer 61 has good conductivity and ensures the signal transmission effect of the transistor 101.

[0064] In this embodiment, transistor 101 further includes a back barrier layer 80, which is located on the side of channel layer 10 away from AlN barrier layer 20, i.e., channel layer 10 is stacked on back barrier layer 80. Back barrier layer 80 can have a high barrier to prevent the movement of two-dimensional electron gas within channel layer 10 in the vertical direction of transistor 101. This allows the two-dimensional electron gas to concentrate its flow within channel layer 10, creating a confinement effect and reducing leakage current caused by the two-dimensional electron gas flowing to other layers on the side of back barrier layer 80 away from channel layer 10, further improving the safety performance of transistor 101.

[0065] In some embodiments of this application, transistor 101 further includes a substrate 91, with a channel layer 10, an AlN barrier layer 20, an AlGaN layer 30, a SiN layer 40, and a source 50, a drain 60, and a gate 70 all supported on the substrate 91. In this embodiment, the substrate 91 is formed of a high-resistivity silicon material, which can serve as the substrate for transistor 101 because high-resistivity silicon substrates are inexpensive, resulting in lower costs. In some embodiments of this application, the sheet resistance of substrate 91 is greater than 10,000 ohms / sq. It is understood that in other embodiments of this application, substrate 91 can also be a high-purity (HP) semi-insulating (SI) SiC substrate with a 4H crystal structure. The high-purity (HP) semi-insulating (SI) SiC substrate with a 4H crystal structure has a higher thermal conductivity than the high-resistivity silicon substrate, thereby enabling transistor 101 to have better thermal conductivity and heat dissipation performance. It is understood that in other embodiments of this application, the substrate 91 may be made of other materials, for example, in some embodiments, the substrate 91 may be made of sapphire or other materials.

[0066] In some embodiments of this application, the transistor 101 may further include a first buffer layer 92. The first buffer layer 92 can be used to modulate the stress between the layer structure on the side of the first buffer layer 92 facing away from the substrate 91 and the substrate 91, preventing the effects of excessive stress. This avoids or mitigates the problem of thermal stress generated between the substrate 91 and the layer structure stacked thereon due to differences in the degree of expansion or contraction during the heating or annealing process of fabricating the transistor 101, which could lead to cracking, excessive warping, or separation of the substrate 91 and the layer structure stacked thereon. In some embodiments of this application, the first buffer layer 92 may be formed by deposition of AlN material, AlGaN material, or a composite material including AlN and AlGaN. In this embodiment, the layer structure on the side of the first buffer layer 92 facing away from the substrate 91 is a second buffer layer 93, that is, the first buffer layer 92 in this embodiment can modulate the stress between the second buffer layer 93 and the substrate 91.

[0067] In some embodiments of this application, transistor 101 may further include a second buffer layer 93. In this embodiment, the second buffer layer 93 is stacked on the first buffer layer 92, and the back barrier layer 80 is stacked on the side of the second buffer layer 93 facing away from the first buffer layer 92. The second buffer layer 93 can be used to modulate the stress between the layer structure on the side of the second buffer layer 93 facing away from the first buffer layer 92 and the first buffer layer 92, thereby avoiding or mitigating the problem of cracking, excessive warping, or separation caused by the different degrees of expansion or contraction between the layer structure on the side of the second buffer layer 93 facing away from the first buffer layer 92 and the first buffer layer 92 during the heating or annealing process of manufacturing transistor 101. In this embodiment, the layer structure on the side of the second buffer layer 93 facing away from the first buffer layer 92 is a back barrier layer 80. The second buffer layer 93 is disposed between the back barrier layer 80 and the first buffer layer 92. During the heating or annealing process of fabricating the transistor 101, the thermal stress between the back barrier layer 80 and the second buffer layer 93 can be relatively small, as can the thermal stress between the first buffer layer 92 and the second buffer layer 93. Therefore, cracking, excessive warping, or separation is less likely between the back barrier layer 80 and the second buffer layer 93, and between the first buffer layer 92 and the second buffer layer 93, thus ensuring the quality of the transistor 101. In some embodiments, the second buffer layer 93 can be formed by GaN material deposition. In some embodiments of this application, the thickness of the second buffer layer 93 can be 1μm-5μm, ensuring that the second buffer layer 93 can better buffer the thermal stress between the back barrier layer 80 and the first buffer layer 92.

[0068] In this application, transistor 101 includes an AlN barrier layer 20 and an AlGaN layer 30 and a SiN layer 40 stacked on the AlGaN layer 20. Since the AlGaN layer 30 can form an AlGaN / AlN composite barrier with the AlN barrier layer 20, and the SiN layer 40 can form a SiN / AlN composite barrier with the AlN barrier layer 20, the transistor 101 is an enhancement-mode transistor. The transistor is in the on-state only when the gate voltage applied to the gate 70 on the AlGaN layer 30 is positive and greater than the transistor's turn-on voltage. When no gate voltage is applied to the gate 70 or the applied gate voltage is small, the transistor 101 is in the off-state, thus avoiding safety issues caused by leakage when the transistor 101 is not working, and providing higher safety performance. Furthermore, since the SiN layer is an insulating material, and the SiN layer partially covers the AlN barrier layer, it can act as a surface passivation layer, further providing the transistor with higher safety performance.

[0069] In some embodiments of this application, the SiN layer 40 enhances the polarization effect between the AlN barrier layer 20 and the channel layer 10 at the contact position with the SiN layer 40, thereby generating more electrons in the channel layer 10 at the corresponding position of the SiN / AlN composite barrier, forming a higher density two-dimensional electron gas, and thus reducing the operating voltage of the transistor 101. Furthermore, in the embodiments of this application, the length L1 of the AlGaN layer 30, the length L2 of the first portion 41 of the SiN layer 40, and the length L3 of the second portion 42 are all relatively small, meaning the distance between the source 50 and the drain 60 is small, which also reduces the channel resistance between the source 50 and the drain 60, further lowering the operating voltage of the transistor 101. In some embodiments, the source 50 may include a first n-type heavily doped GaN layer 51 and a source metal electrode 52 stacked together, and the drain 60 may include a second n-type doped GaN layer 61 and a drain metal electrode 62 stacked together, thereby reducing the contact resistance between the first n-type heavily doped GaN layer 51 and the second n-type heavily doped GaN layer 61 and the channel layer 10, further reducing the operating voltage of the transistor 101, and saving the power consumption of the transistor 101.

[0070] In this embodiment, the gate 70 is in Schottky contact with the AlGaN layer 30. No dielectric layer is required on the side of the gate 70 facing the AlGaN layer 30, which simplifies the fabrication process of the transistor 101, reduces the fabrication cost of the transistor 101, and enables the transistor 101 to switch faster, ensuring that the device including the transistor 101 (such as the power amplifier 100 of this application) has a high response speed.

[0071] In this application, transistor 101 includes a GaN channel layer, an AlN barrier layer, an AlGaN layer, and other layer structures. That is, transistor 101 in this application is a GaN-based transistor. Compared with general GaAs-based transistors, the power amplifier 100 made from transistor 101 in this application can transmit and process radio frequency signals with a larger bandwidth.

[0072] The above are preferred embodiments of this application. It should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principles of this application, and these improvements and modifications are also considered to be within the scope of protection of this application.

Claims

1. A transistor, characterized in that, The transistor includes a channel layer, an AlN barrier layer, an AlGaN layer, a SiN layer, a gate, a source, and a drain. The AlN barrier layer, the source, and the drain are all stacked on the channel layer. The source and the drain are spaced apart and are located on the surface of the channel layer facing the AlN barrier layer. The AlN barrier layer is located between the spaced-apart source and drain. Both the SiN layer and the AlGaN layer are stacked on the side of the AlN barrier layer away from the channel layer; the AlN barrier layer includes a first region, a second region, and a third region, the first region being connected between the second region and the third region; the SiN layer includes a first portion and a second portion spaced apart, the first portion of the SiN layer covering the second region of the AlN barrier layer, and the second portion of the SiN layer covering the third region of the AlN barrier layer; The AlGaN layer is disposed between the first portion and the second portion, and the AlGaN layer is adjacent to the first portion and the second portion, and the AlGaN layer covers the first region of the AlN barrier layer; The gate layer is stacked on the side of the AlGaN layer away from the AlN barrier layer and is in Schottky contact with the AlGaN layer.

2. The transistor as claimed in claim 1, characterized in that, The thickness of the SiN layer is greater than the thickness of the AlGaN layer. A trench is formed between the first portion of the SiN layer, the AlGaN layer, and the second portion of the SiN layer. The bottom wall of the trench is the AlGaN layer, and the two opposite sidewalls of the trench are the first portion of the SiN layer and the second portion of the SiN layer, respectively.

3. The transistor as claimed in claim 2, characterized in that, The gate includes a first block that fills the trench, and the length of the first block of the gate is 200±100nm.

4. The transistor as claimed in claim 3, characterized in that, The gate further includes a second block located outside the trench and stacked on the side of the first block away from the AlGaN layer, with the length of the second block being greater than the length of the first block.

5. The transistor according to any one of claims 1-4, characterized in that, The thickness of the AlGaN layer is 2-5 nm.

6. The transistor according to any one of claims 1-4, characterized in that, The length of the first part of the SiN layer is 200±100nm, and the length of the second part of the SiN layer is 200±100nm. The lengths of the first part and the second part may be the same or different.

7. The transistor of claim 6, characterized in that, The thickness of the SiN layer is 10-30 nm.

8. The transistor of claim 1, characterized in that, The source includes a first n-type heavily doped GaN layer and a source metal electrode. The first n-type heavily doped GaN layer is in contact with the channel layer. The source metal electrode is stacked on the side of the first n-type heavily doped GaN layer away from the channel layer. The Hall concentration of the first n-type heavily doped GaN layer is greater than 1E20.

9. The transistor as claimed in claim 1 or 8, characterized in that, The source includes a second n-type heavily doped GaN layer and a drain metal electrode. The second n-type heavily doped GaN layer is in contact with the channel layer. The drain metal electrode is stacked on the side of the second n-type heavily doped GaN layer away from the channel layer. The Hall concentration of the second n-type heavily doped GaN layer is greater than 1E20.

10. The transistor of claim 9, characterized in that, The first n-type heavily doped GaN layer and the second n-type heavily doped GaN layer are formed from GaN material doped with n-type material or InGaN material doped with n-type material.

11. The transistor of claim 1, characterized in that, The transistor further includes a back barrier layer located on the side of the channel layer away from the AlN barrier layer, and the barrier of the back barrier layer is higher than that of the channel layer.

12. The transistor as claimed in claim 1 or 11, characterized in that, The channel layer is a GaN channel layer.

13. The transistor of claim 1, characterized in that, The transistor further includes a substrate, the channel layer is stacked on the substrate, the substrate is a high-resistivity silicon material, and the sheet resistance of the substrate is greater than 10,000 ohms / sq.

14. The transistor of claim 13, characterized in that, The transistor further includes a first buffer layer, which is stacked on the substrate and is used to modulate the stress between the layer structure of the first buffer layer on the side opposite to the substrate and the substrate.

15. The transistor of claim 14, characterized in that, The transistor further includes a second buffer layer, which is stacked on the side of the first buffer layer away from the substrate. The second buffer layer is used to modulate the stress between the layer structure of the second buffer layer away from the first buffer layer and the first buffer layer.

16. The transistor of claim 1, characterized in that, The AlN barrier layer is formed of AlN material or indium-doped AlN material.

17. The transistor of claim 1, characterized in that, The Al composition in the AlGaN layer is 50% ± 10%.

18. The transistor of claim 1, characterized in that, The channel layer has notches on both opposite sides of its surface facing the AlN barrier layer, and the source and drain are each located within one of the notches.

19. A power amplifier, characterized in that, The transistor includes a package structure as described in any one of claims 1-18, wherein the transistor is packaged within the package structure.

20. An electronic device, characterized in that, The device includes an antenna and a power amplifier as described in claim 19, wherein the power amplifier is used to amplify a radio frequency signal, and the antenna is used to transmit the radio frequency signal amplified by the power amplifier.

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