Mi pi interface circuit and control method thereof, chip and terminal

Abstract

A MIPI interface circuit, a control method thereof, a chip and a terminal are provided.The MIPI interface circuit comprises a first switch unit, which is used for being turned on in a high-speed mode, and a first end of the first switch unit is connected to a power supply voltage; a high-speed driver, which is used for driving a high-speed signal in the high-speed mode, and an input end of the high-speed driver is coupled to a second end of the first switch unit; a second switch unit, which is used for being turned on in the high-speed mode, and a first end of the second switch unit is coupled to an output end of the high-speed driver, and a second end of the second switch unit is grounded; and a low-power-consumption driver, which is used for driving a low-power-consumption signal in a low-power-consumption mode. The technical scheme can solve the problem of insufficient voltage resistance of MOS tubes in a sending interface driver.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a MIPI interface circuit and its control method, chip, and terminal. Background Technology

[0002] The Mobile Industry Processor Interface (MIPI) is an open standard and specification for mobile application processors, initiated by the MIPI Alliance.

[0003] In the MIPI protocol's D-PHY or C-PHY, the output port can output high-speed (HS) mode signals and low-power (LP) mode signals. For example... Figure 1 As shown, in a traditional MIPI interface circuit, the high-speed mode signal and the low-power mode signal are driven by the HS driver and the LP driver, respectively. Figure 1 (As shown by the dashed line) Drive. The output voltage swing in LP mode is 0–1.2V, and the output voltage swing in HS mode is 0.1–0.3V. Under non-advanced process technology, the internal analog power supply voltage of the chip is 1.2V.

[0004] However, with the use of advanced manufacturing processes (such as 28nm process), the internal analog power supply voltage of the chip is reduced. If the HS driver uses internal transistors of the chip with advanced manufacturing processes, the source-drain withstand voltage of the internal transistors is less than 1.2V, which causes the internal MOS transistors of the HS driver to withstand unsafe source-drain voltages when the transmit interface is operating in LP mode. Summary of the Invention

[0005] The technical problem solved by this invention is the insufficient withstand voltage of the internal MOS transistor in the transmit interface driver.

[0006] To address the aforementioned technical problems, this invention provides a control method for a MIPI interface circuit. The MIPI interface circuit includes: a high-speed driver, a first switching unit, a second switching unit, and a low-power driver. A first terminal of the first switching unit is connected to a power supply voltage. The input terminal of the high-speed driver is coupled to a second terminal of the first switching unit. The first terminal of the second switching unit is coupled to the output terminal of the high-speed driver, and the second terminal of the second switching unit is grounded. The control method for the MIPI interface circuit includes: controlling the high-speed driver to operate in high-speed mode and outputting a high-speed signal via a first timing control signal; controlling the first switching unit to turn on or off via a second timing control signal; controlling the second switching unit to turn on or off via a third timing control signal; and controlling the low-power driver to operate in low-power mode via a fourth timing control signal, so as to drive the output of a low-power signal in low-power mode.

[0007] To address the aforementioned technical problems, this invention also discloses a MIPI interface circuit. The MIPI interface circuit includes: a first switching unit for conduction in high-speed mode, wherein a first terminal of the first switching unit is connected to a power supply voltage; a high-speed driver for driving the output of a high-speed signal in high-speed mode, wherein the input terminal of the high-speed driver is coupled to a second terminal of the first switching unit; a second switching unit for conduction in high-speed mode, wherein a first terminal of the second switching unit is coupled to the output terminal of the high-speed driver, and a second terminal of the second switching unit is grounded; and a low-power driver for driving the output of a low-power signal in low-power mode.

[0008] Optionally, the MIPI interface circuit further includes a mode switching unit, used to control the first switching unit to conduct in high-speed mode according to the operating mode of the interface circuit, and to control the second switching unit to conduct in the high-speed mode.

[0009] Optionally, the output terminal of the mode switching unit outputs a mode control voltage, which controls the first switching unit and the second switching unit to be in the on state in the high-speed mode and in the off state in the low-power mode.

[0010] Optionally, the mode switching unit includes: a NOR gate, wherein the first input terminal of the NOR gate is connected to a first control voltage, and the second input terminal of the NOR gate is connected to a second control voltage; a NAND gate, wherein the first input terminal of the NAND gate is coupled to the output terminal of the NOR gate, and the second input terminal of the NAND gate is connected to a third control voltage; and a NOT gate, wherein the input terminal of the NOT gate is coupled to the output terminal of the NAND gate, and the output terminal of the NOT gate outputs the mode control voltage.

[0011] Optionally, the high-speed driver includes multiple high-speed drive units connected in parallel. The input terminal of each high-speed drive unit is coupled to the second terminal of a corresponding first switching unit, and the output terminal of each high-speed drive unit is coupled to the first terminal of a corresponding second switching unit; or, the input terminal of each high-speed drive unit is coupled to the second terminal of a corresponding first switching unit, and the output terminal of each high-speed drive unit is coupled to the first terminal of the same second switching unit; or, the input terminal of each high-speed drive unit is coupled to the second terminal of the same first switching unit, and the output terminal of each high-speed drive unit is coupled to the first terminal of a corresponding second switching unit; or, the input terminal of each high-speed drive unit is coupled to the second terminal of the same first switching unit, and the output terminal of each high-speed drive unit is coupled to the first terminal of the same second switching unit.

[0012] Optionally, the first switching unit includes a first NMOS transistor, the gate of which is connected to a first control voltage, the source of which is coupled to the input terminal of the high-speed driver, and the drain of which is connected to a power supply voltage; the second switching unit includes a second NMOS transistor, the gate of which is connected to a second control voltage, the drain of which is coupled to the output terminal of the high-speed driver, and the source of which is grounded.

[0013] Optionally, the number of the first NMOS transistors is one or more, and the multiple first NMOS transistors are connected in parallel or in series with each other; the number of the second NMOS transistors is one or more, and the multiple second NMOS transistors are connected in parallel or in series with each other.

[0014] Optionally, the first switching unit includes a first resistor, and the second switching unit includes a second resistor. The number of first resistors is one or more, and the multiple first resistors are connected in parallel or in series. The number of second resistors is one or more, and the multiple second resistors are connected in parallel or in series.

[0015] Optionally, the number of the first switching units is one or more, and the multiple first switching units are connected in parallel or in series with each other; the number of the second switching units is one or more, and the multiple second switching units are connected in parallel or in series with each other.

[0016] This invention also discloses a chip, which includes the MIPI interface circuit.

[0017] This invention also discloses a terminal, which includes the MIPI interface circuit.

[0018] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0019] In this invention, the MIPI interface circuit includes a first switching unit for conduction in high-speed mode, with a first terminal connected to a power supply voltage; a high-speed driver for driving a high-speed signal output in high-speed mode, with its input terminal coupled to a second terminal of the first switching unit; a second switching unit for conduction in high-speed mode, with its first terminal coupled to the output terminal of the high-speed driver and its second terminal grounded; and a low-power driver for driving a low-power signal output in low-power mode. By setting up a first and a second switching unit, and having them operate in different states in different modes, this invention minimizes the source-drain voltage of the internal transistors in the high-speed driver, avoiding the problem of insufficient voltage withstand capability of the internal MOS transistors, thereby ensuring the normal operation of the high-speed driver and improving its driving performance. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the structure of a MIPI interface circuit in the prior art;

[0021] Figure 2 This is a schematic diagram of the structure of a MIPI interface circuit according to an embodiment of the present invention;

[0022] Figure 3 This is a schematic diagram of the specific structure of a MIPI interface circuit according to an embodiment of the present invention;

[0023] Figure 4 This is a schematic diagram of the specific structure of another MIPI interface circuit according to an embodiment of the present invention;

[0024] Figure 5 This is a schematic diagram of the structure of a mode switching unit according to an embodiment of the present invention;

[0025] Figure 6 This is a schematic diagram of the specific structure of a mode switching unit according to an embodiment of the present invention;

[0026] Figure 7 This is a signal timing diagram according to an embodiment of the present invention;

[0027] Figure 8 This is another signal timing diagram according to an embodiment of the present invention. Detailed Implementation

[0028] As described in the background section, with the use of advanced manufacturing processes (such as 28nm process), the internal analog power supply voltage of the chip is reduced. If the HS driver uses an internal transistor of an advanced process chip, the source-drain withstand voltage of the internal transistor is less than 1.2V, causing the internal MOS transistor of the HS driver to withstand an unsafe source-drain voltage when the transmit interface is operating in LP mode.

[0029] The inventors of this application, through research, discovered that... Figure 1 In the traditional MIPI interface circuit shown, when the interface is working in low power mode, the output voltage Vout swings in the range of 0 to 1.2V. At this time, the input signal Vup = Vdn = 0 of the high-speed driver (i.e., the control signal B), and the internal MOS transistor of the high-speed driver may be subjected to an unsafe source-drain voltage of 1.2V.

[0030] The technical solution of this invention sets up a first switching unit and a second switching unit, which are in different states in different modes, so that the source-drain voltage of the internal transistor of the high-speed driver is small, avoiding the problem of insufficient withstand voltage of the internal MOS transistor of the high-speed driver, thereby ensuring the normal operation of the high-speed driver and improving the driving performance.

[0031] The high-speed mode (also known as high-speed signal mode) mentioned in this embodiment of the invention is used for high-speed data transmission, for example, a transmission rate of 80Mbps to 1Gbps / Lane.

[0032] The low-power mode (also known as low-power signal mode) mentioned in this embodiment of the invention is used for control, and the power consumption is usually low, for example, the maximum transmission frequency is 10MHz.

[0033] Accordingly, the high-speed driver referred to in this embodiment of the invention refers to a driver capable of operating in high-speed mode, and the output signal can be referred to as a high-speed signal. The low-power driver referred to in this embodiment of the invention refers to a driver capable of operating in low-power mode, and the output signal can be referred to as a low-power signal.

[0034] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0035] Figure 2 This is a schematic diagram of the structure of a MIPI interface circuit according to an embodiment of the present invention.

[0036] The MIPI interface circuit includes a first switching unit and a second switching unit, which are respectively used to conduct in high-speed mode. The first terminal of the first switching unit is connected to the power supply voltage VX400, the first terminal of the second switching unit is coupled to the output terminal of the high-speed driver 20, and the second terminal of the second switching unit is grounded to AVSS.

[0037] exist Figure 2 In the diagram, the first switching unit is shown using MOS transistor MN1 as an example, and the second switching unit is shown using MOS transistor MN2 as an example.

[0038] Those skilled in the art should understand that, in addition to MOSFETs, the first switching unit and the second switching unit can also be any other implementable switching device, and the embodiments of the present invention do not limit this.

[0039] The output signal Vout of the MIPI interface circuit can be either a high-speed signal or a low-power signal. (Continue to refer to...) Figure 2 The MIPI interface circuit also includes a high-speed driver 20 for driving the output of a high-speed signal in high-speed mode. The input terminal of the high-speed driver 20 is coupled to the second terminal of the MOSFET MN1. The MIPI interface circuit also includes a low-power driver 21 (such as...). Figure 2 (As shown by the dashed line in the middle), it is used to drive the output of low-power signals in low-power mode.

[0040] In the specific implementation, the drain of MOSFET MN1 is connected to the power supply voltage VX400, and the source of MOSFET MN1 is coupled to one end of the high-speed driver 20. The drain of MOSFET MN2 is coupled to the other end of the high-speed driver 20, and the source of MOSFET MN2 is grounded to AVSS. The gates of MOSFET MN1 and MOSFET MN2 are connected to the control voltage Vsw. The control voltage Vsw is a combination of low-power control-related signals and high-speed control-related signals.

[0041] In practical implementation, MOSFETs MN1 and MN2 can be either core transistors or input / output (I / O) transistors. Choosing core transistors results in lower on-resistance and better performance when the interface operates in high-speed mode. Choosing I / O transistors provides higher source-drain voltage withstand, making the high-speed driver safer when the interface operates in low-power mode. The gate control voltages of MOSFETs MN1 and MN2 can be the same or different. The relevant power supply voltages only need to ensure the circuit functions normally; there are no other restrictions.

[0042] It should be noted that the high-speed driver in this embodiment of the invention can be D-PHY, C-PHY, or a combination of D-PHY and C-PHY (C / D-PHY Combo).

[0043] In a non-limiting embodiment of the present invention, the MIPI interface circuit may further include a mode switching unit (not shown), configured to control the first switching unit to conduct in high-speed mode according to the operating mode of the interface circuit, and to control the second switching unit to conduct in the high-speed mode.

[0044] Furthermore, the output terminal of the mode switching unit outputs a mode control voltage (i.e., the aforementioned control voltage Vsw), which controls the first switching unit and the second switching unit to be in the on state in the high-speed mode and in the off state in the low-power mode.

[0045] In one specific embodiment, Figure 3 and Figure 4In the MIPI interface circuit shown, the high-speed driver 20 includes multiple high-speed drive units connected in parallel. The input terminal of each high-speed drive unit is coupled to the second terminal of the corresponding first switching unit, and the output terminal of each high-speed drive unit is coupled to the first terminal of the corresponding second switching unit; or, the input terminal of each high-speed drive unit is coupled to the second terminal of the corresponding first switching unit, and the output terminal of each high-speed drive unit is coupled to the first terminal of the same second switching unit; or, the input terminal of each high-speed drive unit is coupled to the second terminal of the same first switching unit, and the output terminal of each high-speed drive unit is coupled to the first terminal of the corresponding second switching unit; or, the input terminal of each high-speed drive unit is coupled to the second terminal of the same first switching unit, and the output terminal of each high-speed drive unit is coupled to the first terminal of the same second switching unit.

[0046] In a non-limiting embodiment of the present invention, please refer to Figure 5 , Figure 5 The input and output signals of the mode switching unit are shown. The input signals of the mode switching unit include a first control voltage Vlpdp, a second control voltage Vlpdn, a third control voltage Vhsen, and control signal A. The output signals of the mode switching unit include a mode control voltage Vsw and control signal B, which is used to input to the high-speed driver 20.

[0047] In a non-limiting embodiment of the present invention, the mode switching unit includes: a NOR gate, wherein a first input terminal of the NOR gate is connected to a first control voltage and a second input terminal of the NOR gate is connected to a second control voltage; a NAND gate, wherein a first input terminal of the NAND gate is coupled to the output terminal of the NOR gate and a second input terminal of the NAND gate is connected to a third control voltage; and a NOT gate, wherein an input terminal of the NOT gate is coupled to the output terminal of the NAND gate and the output terminal of the NOT gate outputs the mode control voltage.

[0048] Please refer to the details. Figure 6 In the specific structure of the mode switching unit, the first input terminal of the NOR gate O1 is connected to the first control voltage Vlpdp, the second input terminal of the NOR gate O1 is connected to the second control voltage Vlpdn, the first input terminal of the NAND gate A1 is coupled to the output terminal of the NOR gate O1, and the second input terminal of the NAND gate A1 is connected to the third control voltage Vhsen. The input terminal of the NOT gate N1 is coupled to the output terminal of the NAND gate A1, and the output terminal of the NOT gate N1 outputs the mode control voltage Vsw.

[0049] Furthermore, the mode switching unit can also provide the control signal B of the high-speed driver 20, namely the input voltages Vup and Vdn. Specifically, the input of NOT gate N2 is connected to the fourth control voltage Vupa, the output of NOT gate N1 is coupled to the first input of NAND gate A2, the second input of NAND gate A2 is connected to the third control voltage Vhsen, and the output of NAND gate A2 outputs the voltage Vup. The input of NOT gate N3 is connected to the fifth control voltage Vdna, the output of NOT gate N3 is coupled to the first input of NAND gate A3, the second input of NAND gate A3 is connected to the third control voltage Vhsen, and the output of NAND gate A3 outputs the voltage Vdn.

[0050] In this embodiment, when the MIPI transmitter operates in high-speed mode (HS mode), the input voltages Vlpdp and Vlpdn of the low-power driver 21 are both 0 (i.e., both the first and second control voltages are 0), and the mode control voltage Vsw is the power supply voltage AVDD. The input voltage Vup = Vupa (fourth control voltage), and the input voltage Vdn = Vdna (fifth control voltage). At this time, the control signal B of the high-speed driver 20 takes effect. When the MIPI transmitter operates in low-power mode (LP mode), the third control voltage Vhsen = 0, the mode control voltage Vsw = 0, the input voltage Vup = AVDD, the input voltage Vdn = AVDD, the control signal of the high-speed driver 20 is pulled high, and the high-speed driver 20 outputs a high-impedance state.

[0051] Figure 7 The timing diagram for each signal is shown in High Speed ​​Mode. The first control voltage Vlpdp and the second control voltage Vlpdn are both 0, the third control voltage Vhsen is high, control signals A and B are active, and the control voltage Vsw is the power supply voltage AVDD. The active state of control signals A and B can mean that they can control the corresponding MOSFETs to turn on.

[0052] Please refer to the above as well. Figure 3 When the MIPI transmitter operates in high-speed mode (HS mode), the input voltages Vlpdp and Vlpdn (i.e., the first control voltage and the second control voltage) of the low-power driver 21 are both 0, and the low-power driver 21 outputs a high-impedance state. At the same time, the mode control voltage Vsw is the power supply voltage AVDD, MOSFETs MN1 and MN2 are turned on, and the high-speed driver 20 operates normally.

[0053] In another specific embodiment, please refer to... Figure 4When the MIPI transmitter operates in high-speed mode (HSmode), the input voltages Vlpdp and Vlpdn of the low-power driver 21 are both 0, and the low-power driver 21 outputs a high-impedance state. At the same time, the mode control voltage Vsw is the power supply voltage AVDD, MOSFETs MN1 and MN2 are turned on, and the high-speed driver 20 operates normally.

[0054] Figure 8 The timing diagram for each signal is shown in Low Power Mode. The first control voltage Vlpdp and the second control voltage Vlpdn are active, the third control voltage Vhsen is low, control signal A is active, control signal B is inactive, and control voltage Vsw is low. Control signal B being inactive can mean that it can control the corresponding MOSFET to turn off.

[0055] Please refer to the above as well. Figure 3 When the MIPI transmitter operates in low-power mode (LP mode), the mode control voltage Vsw is 0, MOSFETs MN1 and MN2 are turned off, and the high-speed driver 20 outputs a high-impedance state. The low-power driver 21 operates normally. At this time, the source voltage of the internal MOSFET MN4 of the high-speed driver 20 is slightly lower than the power supply voltage AVDD, ensuring that the source-drain voltage of MOSFET MN4 is within a safe range.

[0056] In another specific embodiment, please refer to... Figure 4 When the MIPI transmitter operates in low-power mode (LPmode), the mode control voltage Vsw is 0, MOSFETs MN1 and MN2 are turned off, and the high-speed driver 20 outputs a high-impedance state. The low-power driver 21 operates normally. At this time, the source voltage of the internal MOSFETs MN4 and MN6 of the high-speed driver 20 is slightly lower than the power supply voltage AVDD, ensuring that the source-drain voltage of MOSFETs MN4 and MN6 is within a safe range.

[0057] In a non-limiting embodiment of the present invention, the number of the first NMOS transistors (i.e., MOS transistors MN1) is one or more, and the multiple first NMOS transistors are connected in parallel or in series; the number of the second NMOS transistors (i.e., MOS transistors MN2) is one or more, and the multiple second NMOS transistors are connected in parallel or in series. The control voltages connected to the gates of the multiple first NMOS transistors can be the same or different; the control voltages connected to the gates of the multiple second NMOS transistors can also be the same or different.

[0058] This invention also discloses a control method for a MIPI interface circuit. The control method for the MIPI interface circuit is a timing control method, which specifically includes the following steps: controlling a high-speed driver to operate in a high-speed mode and output a high-speed signal through a first timing control signal; controlling a first switching unit to turn on or off through a second timing control signal; controlling a second switching unit to turn on or off through a third timing control signal; and controlling a low-power driver to operate in a low-power mode through a fourth timing control signal, so as to drive the output of a low-power signal in the low-power mode.

[0059] It should be noted that the sequence number of each step in this embodiment does not represent a limitation on the execution order of each step.

[0060] In specific implementation, when controlling the high-speed driver to operate in high-speed mode, the first switching unit and the second switching unit are turned on; when controlling the low-power driver to operate in low-power mode, the first switching unit and the second switching unit are turned off.

[0061] In specific implementation, the first timing control signal may be the first control voltage Vlpdp, the second control voltage Vlpdn, the control signal B, and the mode control voltage Vsw in the aforementioned embodiments.

[0062] The second timing control signal and the third timing control signal can be the mode control voltage Vsw in the foregoing embodiments.

[0063] The fourth timing control signal can be the first control voltage Vlpdp, the second control voltage Vlpdn, the control signal B, and the mode control voltage Vsw in the aforementioned embodiments.

[0064] It is understood that the timing relationship of the first timing control signal, the second timing control signal, the third timing control signal and the fourth timing control signal can be referred to the description of the foregoing embodiments, and will not be repeated here.

[0065] This invention also discloses a chip, which includes the MIPI interface circuit. The chip can be a single chip component or a chip module.

[0066] This invention also discloses a terminal chip, the terminal including the MIPI interface circuit. The terminal includes, but is not limited to, terminal devices such as mobile phones, computers, and tablet computers.

[0067] The descriptions of "first," "second," etc., appearing in the embodiments of this application are for illustrative purposes and to distinguish the objects being described. They have no order and do not indicate any special limitation on the number of devices in the embodiments of this application, nor do they constitute any limitation on the embodiments of this application.

[0068] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A control method for a MIPI interface circuit, characterized in that, The MIPI interface circuit includes: a high-speed driver, a first switching unit, a second switching unit, and a low-power driver; a first terminal of the first switching unit is connected to a power supply voltage; the input terminal of the high-speed driver is coupled to a second terminal of the first switching unit; the first terminal of the second switching unit is coupled to the output terminal of the high-speed driver, and the second terminal of the second switching unit is grounded; the control method includes: The high-speed driver is controlled to operate in high-speed mode and output a high-speed signal by the first timing control signal; The first switching unit is turned on or off by controlling the second timing control signal; The second switching unit is turned on or off by a third timing control signal; The low-power driver is controlled to operate in low-power mode by the fourth timing control signal, so as to drive the output low-power signal in low-power mode.

2. A MIPI interface circuit, characterized in that, include: The first switching unit is used to be turned on in high-speed mode, and the first terminal of the first switching unit is connected to the power supply voltage. A high-speed driver is used to drive the output of a high-speed signal in the high-speed mode, and the input terminal of the high-speed driver is coupled to the second terminal of the first switching unit. A second switching unit is used to turn on in the high-speed mode. The first terminal of the second switching unit is coupled to the output terminal of the high-speed driver, and the second terminal of the second switching unit is grounded. Low-power driver for driving low-power output signals in low-power mode.

3. The MIPI interface circuit according to claim 2, characterized in that, Also includes: The mode switching unit is used to control the first switching unit to conduct in high-speed mode according to the working mode of the interface circuit, and to control the second switching unit to conduct in the high-speed mode.

4. The MIPI interface circuit according to claim 3, characterized in that, The output terminal of the mode switching unit outputs a mode control voltage, which controls the first switching unit and the second switching unit to be in the on state in the high-speed mode and in the off state in the low-power mode.

5. The MIPI interface circuit according to claim 4, characterized in that, The mode switching unit includes: NOR gate, wherein the first input terminal of the NOR gate is connected to a first control voltage, and the second input terminal of the NOR gate is connected to a second control voltage; A NAND gate, wherein the first input terminal of the NAND gate is coupled to the output terminal of the NOR gate, and the second input terminal of the NAND gate is connected to a third control voltage; The NOT gate has its input terminal coupled to the output terminal of the NAND gate, and its output terminal outputs the mode control voltage.

6. The MIPI interface circuit according to claim 2, characterized in that, The high-speed driver includes multiple high-speed drive units connected in parallel. The input terminal of each high-speed drive unit is coupled to the second terminal of a corresponding first switching unit, and the output terminal of each high-speed drive unit is coupled to the first terminal of a corresponding second switching unit; or, the input terminal of each high-speed drive unit is coupled to the second terminal of a corresponding first switching unit, and the output terminal of each high-speed drive unit is coupled to the first terminal of the same second switching unit; or, the input terminal of each high-speed drive unit is coupled to the second terminal of the same first switching unit, and the output terminal of each high-speed drive unit is coupled to the first terminal of a corresponding second switching unit; or, the input terminal of each high-speed drive unit is coupled to the second terminal of the same first switching unit, and the output terminal of each high-speed drive unit is coupled to the first terminal of the same second switching unit.

7. The MIPI interface circuit according to claim 2, characterized in that, The first switching unit includes a first NMOS transistor, the gate of which is connected to a first control voltage, the source of which is coupled to the input terminal of the high-speed driver, and the drain of which is connected to a power supply voltage; the second switching unit includes a second NMOS transistor, the gate of which is connected to a second control voltage, the drain of which is coupled to the output terminal of the high-speed driver, and the source of which is grounded.

8. The MIPI interface circuit according to claim 7, characterized in that, The number of the first NMOS transistors is one or more, and the multiple first NMOS transistors are connected in parallel or in series with each other; the number of the second NMOS transistors is one or more, and the multiple second NMOS transistors are connected in parallel or in series with each other.

9. The MIPI interface circuit according to claim 2, characterized in that, The first switching unit includes a first resistor, and the second switching unit includes a second resistor. The number of first resistors is one or more, and the multiple first resistors are connected in parallel or in series. The number of second resistors is one or more, and the multiple second resistors are connected in parallel or in series.

10. The MIPI interface circuit according to claim 2, characterized in that, The number of the first switch units is one or more, and the multiple first switch units are connected in parallel or in series with each other; the number of the second switch units is one or more, and the multiple second switch units are connected in parallel or in series with each other.

11. A chip, characterized in that, Includes the MIPI interface circuit as described in any one of claims 2 to 10.

12. A terminal, characterized in that, Includes the MIPI interface circuit as described in any one of claims 2 to 10.

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