Timing synchronization method and system for uqpsk-dsss signals

Abstract

The application discloses a timing synchronization method and system for UQPSK-DSSS signals, and belongs to the field of communication signal processing. The application replaces the traditional digital interpolation with zero value interpolation, shaping filtering and extraction units at the sending end, reduces the general system jitter caused by non-integer oversampling, and guarantees the stability of normal tracking work after loop locking. The application adds a timing deviation estimation module and a symbol interpolation module at the receiving end. In the case that there is large jitter in the non-integer oversampling signal system, the UQPSK-DSSS signal has the characteristics of complete alignment of coupling, and the code ring NCO phase accumulation in the delay locked loop has the characteristics of stability. Only the code ring NCO phase accumulation is used to realize the joint demodulation of the measurement and control link and the data transmission link, without too many calculation processes. The application estimates the normalized timing error estimation value of the accurate non-spread spectrum branch by using the code ring NCO phase accumulation, and realizes the accurate bit timing synchronization of the signal under the low oversampling rate by means of the symbol interpolation operation.

Description

Technical Field

[0001] This invention relates to a hybrid bit timing synchronization method and system for UQPSK-DSSS signals, belonging to the field of communication signal processing. Background Technology

[0002] Unbalanced quadrature phase shift keying (UQPSK) can be used to transmit two independent information streams with different transmission rates. The two independent streams can be spread or unspread as needed. The spread-spectrum branch has strong anti-interference capabilities, while the unspread-spectrum branch has a high transmission rate. In a UQPSK-DSSS signal, one branch uses direct sequence spread spectrum, while the other is unspread. The spread-spectrum branch can be used for command and control and ranging services, offering good anti-interference and security. The unspread-spectrum branch can be used to transmit high-speed data, meeting the needs of large-capacity data transmission services. The UQPSK-DSSS signal system combines ranging and control with high-speed data transmission functions, making it widely applicable in information-asymmetric scenarios such as UAVs and satellite systems.

[0003] Timing synchronization of UQPSK-DSSS signals is based on code rings, where the output of the instantaneous branch of the code ring is the demodulated information of the spread spectrum branch. Timing synchronization of non-spread spectrum branches can employ direct decimation, zero-crossing detection, Gardener's algorithm, or other bit synchronization algorithms. Direct decimation performs well under high oversampling rates but shows a significant performance degradation under low oversampling rates. Bit synchronization algorithms perform well under integer multiple oversampling conditions. Under non-integer multiple oversampling conditions, the signal jitter is large, making bit timing synchronization of non-spread spectrum branches difficult to achieve. Summary of the Invention

[0004] One of the main objectives of this invention is to provide a timing synchronization method for UQPSK-DSSS signals. This invention utilizes the fully aligned coupling characteristic of UQPSK-DSSS signals and the stable phase accumulation of the code ring NCO. It can achieve efficient joint demodulation of the measurement and control link and the data transmission link using only the phase accumulation of the code ring NCO, thereby realizing the mixed bit timing synchronization of UQPSK-DSSS signals without requiring excessive signal processing hardware resources, which is convenient for FPGA hardware implementation.

[0005] The objective of this invention is achieved through the following technical solution.

[0006] This invention discloses a timing synchronization method for UQPSK-DSSS signals. The spread spectrum branch of the UQPSK-DSSS signal is used for measurement and control, while the non-spread spectrum branch is used for data transmission. Demodulation of the spread spectrum branch is implemented based on the code ring. Under non-integer multiple oversampling, the UQPSK-DSSS signal exhibits significant jitter. By employing an interpolation-filtering-decimation sampling rate transformation operation, the significant jitter caused by non-integer multiple oversampling is reduced. This ensures the fully aligned coupling characteristics of the I and Q paths of the UQPSK-DSSS signal while maintaining the stability of the code ring NCO phase accumulation. Based on the aforementioned coupling characteristics of the UQPSK-DSSS signal, a normalized timing error demodulation model for the non-spread spectrum branch is constructed. Based on the code ring NCO phase accumulation required for demodulation in the measurement and control link, the NCO of the Q-path symbol is obtained. Q Phase accumulation; according to the normalized timing error demodulation model, the timing deviation estimate of the non-spread spectrum branch is obtained by linear interpolation; the input signal is interpolated based on the timing deviation estimate, and the optimal sampling point of the non-spread spectrum branch is obtained using the existing information of the spread spectrum branch, that is, the joint demodulation of the measurement and control link and the data transmission link is realized, thereby realizing the hybrid bit timing synchronization of the UQPSK-DSSS signal.

[0007] The method for hybrid bit timing synchronization of UQPSK-DSSS signals disclosed in this invention includes the following steps:

[0008] Step 1: The source I channel is low-speed data, and the Q channel is high-speed data. The spread spectrum I channel and the non-spread spectrum Q channel are mapped to obtain the UQPSK-DSSS signal. Through interpolation-filtering-decimation sampling rate transformation, based on the characteristic that high sampling rates can reduce the adverse effects of non-integer multiple oversampling, the large-scale jitter caused by non-integer multiple oversampling is reduced, and the modulated digital baseband signal is obtained. After mapping, the signal is interpolated with zero values ​​to ensure that the chip information of the spread spectrum branch and the symbol information of the non-spread spectrum branch have complete alignment coupling. The digital baseband signal is converted into an analog signal by a digital-to-analog converter (DAC), and the analog signal is transmitted through a coaxial cable.

[0009] Step 1.1: The I-channel information is d1(n), the Q-channel information is d2(n), and the spreading code is c1(n). The chip rate of the spread I-channel is the same as the information rate of the Q-channel. The spread I-channel is directly mapped to the unspread Q-channel to obtain a sampling rate of R. chip The UQPSK-DSSS signal s1(n), R chip This represents the chip rate after I-channel spread spectrum.

[0010] Step 1.2: The sampling rate of the DAC is f s D is a positive integer. Zero-value interpolation is used to insert zero-value points between adjacent sampling points of the sequence s1(n) obtained in step 1.1, resulting in a sampling rate of D×f.s The sequence s2(n).

[0011] Preferably, the zero-value interpolation in step 1.2 uses NCO. tx Phase accumulation is achieved, NCO tx Quantized to an N-bit integer, with an increment of R each time. chip / (D×f s )×2 N NCO tx Each accumulation outputs a new sampling point. When overflow occurs, the known sequence s1(n) is output. When no overflow occurs, the zero value is output, thus achieving zero-value interpolation.

[0012] Step 1.3: Input the sequence s2(n) obtained in Step 1.2 into the root-raised cosine filter to obtain a sampling rate of D×f. s The sequence s3(n) is transformed more slowly than the sequence s2(n).

[0013] Step 1.4: For sampling rates D×f s The sequence s3(n) is sampled to reduce the sampling rate. Specifically, every D-1 sampling points in the sequence s3(n) are taken to form a new sampling rate of f. s The sequence s4(n).

[0014] Step 1.5: The sampling rate is f s The sequence s4(n) is converted into an analog modulated signal by a digital-to-analog converter (DAC), and the analog signal is transmitted through a coaxial cable.

[0015] Step 2: Perform matched filtering on the digital signal sampled by the ADC to obtain the digital baseband signal x(n). The matched filter is a root-raised cosine filter with the same roll-off factor as the shaping filter unit at the transmitting end.

[0016] The analog-to-digital converter (ADC) receives baseband analog signals, and its sampling rate is the same as that of the DAC, both being f. s The digital baseband signal obtained after ideal matched filtering is

[0017]

[0018] Where P1 is the signal power of the I-path, P2 is the signal power of the Q-path, and the power ratio p = P2 / P1 > 1; d1(n) and d2(n) ∈ {-1, 1} are the data sequences of the I-path and Q-path, respectively; c1(n) ∈ {-1, 1} is the PN code sequence used for direct sequence spread spectrum; and n(n) is the Gaussian white noise signal.

[0019] The I and Q signals are denoted as i(n) and q(n) respectively:

[0020]

[0021] Where, n I (n), n Q (n) is a Gaussian white noise signal.

[0022] Step 3: Based on the principle of direct digital frequency synthesizer, a local PN code with the same frequency and phase as the received PN code c1(n) is generated by the code ring frequency control word FCW. In the direct digital frequency synthesizer, the phase accumulator of the code ring NCO gradually increases from zero, with each increment equal to the current frequency control word. The input signal is correlated with the local PN code, and integration and clearing operations are performed. The integration time is the length L of one PN code cycle. pn That is, the duration T of a symbol in path I. symbol The specific expression is

[0023]

[0024] When the code ring achieves ideal synchronization, the I-path information remains unchanged during the integration time of one cycle of the PN code in the instantaneous branch. The I-path expression in equation (3) simplifies to

[0025]

[0026] In the above formula, the first term contains valid information from the I-channel, and the second term represents noise. Once the loop stabilizes, the local PN code of the instantaneous branch is... Alignment with the PN code c1(n) of the received signal, correlation operation The result of obtaining the maximum value is the coherent integral result, which is the I-path position timing synchronization result.

[0027] Step 4: Input the coherent integration result into the code ring phase detector to obtain the phase detection error of the code ring; filter out the noise in the phase detection error of the code ring through the loop filter so that the filtering result truly reflects the phase change of the filter input signal.

[0028] Preferably, the code ring phase detector is a normalized lead-hysteresis power phase detector; the loop filter is a second-order loop to stabilize and track the sampling error caused by clock bias.

[0029] Step 5: Construct a normalized timing error demodulation model for the non-spread spectrum branch based on the fully aligned coupling characteristics of the I and Q paths of the UQPSK-DSSS signal; obtain the NCO of the Q path symbol based on the NCO phase accumulation in the code ring required for I path demodulation. Q Phase accumulation; based on the normalized timing error demodulation model, the normalized timing deviation estimate of the non-spread spectrum branch is obtained through linear interpolation.

[0030] Step 5.1: Normalize the code NCO accumulator to [0, L] pn Within the range of L pn This is the length of one PN code cycle. Once the loop achieves ideal synchronization, the received signal completes PN code stripping, and the local PN code... Aligned with the PN code c1(n) of the received signal, one cycle of the code NCO corresponds to one cycle of the local PN code and one cycle of the received signal PN code.

[0031] Step 5.2: Take the decimal part of the code NCO from Step 5.1 and name it NCO. Q The NCO accumulation period divided by L pn The duration of one PN code corresponding to the received signal is the duration of one chip in the I channel, which corresponds to one period of a Q-channel symbol.

[0032] Step 5.3: NCO Q One cycle of [0,1) corresponds to one cycle of the Q-path symbol. Further, we can obtain that NCO... Q The optimal sampling point for the Q-path symbol is when NCO = 0.5. Q (n)≤0.5, NCO Q When (n+1)>0.5, it means that there is an optimal sampling point between the nth sampling point and the (n+1)th sampling point.

[0033] Step 5.4: If NCO Q (n)≤0.5, NCO Q (n+1)>0.5, the current optimal sampling point is the m-th symbol, and its corresponding optimal sampling time is (n+μ). m )T s Among them, T s For the sampling interval, μ m The normalized timing bias estimate is given by the normalized timing error demodulation model:

[0034]

[0035] Step 6: In equation (2), the first term of the Q-path expression contains Q-path information, and the second term is noise. The optimal sampling point extracted from this expression is the Q-path bit timing synchronization result. Based on the timing deviation estimate, interpolation is performed on the input signal. The optimal sampling point of the non-spread spectrum branch is obtained using the existing information of the spread spectrum branch. This achieves joint demodulation of the I-path (measurement and control link) and the Q-path (data transmission link), thereby realizing the hybrid bit timing synchronization of the UQPSK-DSSS signal.

[0036] Preferably, the interpolation operation in step 6 uses the Farrow interpolation formula. When there is M times oversampling (M is an even number), the optimal sampling time is (n+μ). m )Ts Then, the sampling points q(nM / 2+1), q(nM / 2+2), ..., q(n+M / 2) are the current symbols. According to the Farrow interpolation formula, the optimal sampling points can be calculated as follows:

[0037]

[0038] In the formula b l (i) are the coefficients of the interpolation filter, which are constants, and N is the order of the interpolation polynomial. According to equation (6), the bit timing synchronization of the Q-channel information is achieved. Thus, the bit timing synchronization of the UQPSK-DSSS signal is completed.

[0039] This invention also discloses a timing synchronization system for UQPSK-DSSS signals, used to implement the aforementioned timing synchronization method for UQPSK-DSSS signals. The transmitting end digital baseband signal generation module includes a spreading unit, a mapping unit, a zero-value interpolation unit, a shaping filter unit, and a decimation unit. The receiving end of the timing synchronization system adds a timing deviation estimation module and a symbol interpolation module to the traditional code ring. The code ring includes an integration and clearing unit and a phase detection and loop filtering unit. The zero-value interpolation unit, shaping filter unit, and decimation unit work together to replace traditional digital interpolation. Through sampling rate transformation, they utilize the low jitter characteristic of the signal at high sampling rates to reduce signal jitter caused by non-integer multiple oversampling. The timing deviation estimation module constructs a normalized timing error demodulation model for the non-spreading branch based on the fully aligned coupling characteristics of the I and Q paths of the UQPSK-DSSS signal. Based on the NCO phase accumulation of the code ring required for demodulation in the telemetry and control link, it obtains the NCO of the Q-path symbols. Q Phase cumulative amount, the NCO of the Q-path symbol Q The phase accumulator is substituted into the normalized timing error demodulation model to obtain the timing deviation estimate of the non-spread spectrum branch. The symbol interpolation module performs interpolation on the input signal based on the timing deviation estimate to obtain the optimal sampling point of the non-spread spectrum branch. This invention reduces the large jitter caused by non-integer multiple oversampling by replacing the traditional digital interpolation at the transmitter with three units: zero-value interpolation, shaping filtering, and decimation. While ensuring the fully aligned coupling characteristics of the I and Q paths of the UQPSK-DSSS signal, it also ensures the stability of the code ring NCO phase accumulator. Furthermore, by adding a timing deviation estimation module and a symbol interpolation module, this invention leverages the fully aligned coupling characteristics of the UQPSK-DSSS signal and the stability of the code ring NCO phase accumulator to achieve joint demodulation of the telemetry and control link and the data transmission link using only the code ring NCO phase accumulator, thus achieving mixed-bit timing synchronization of the UQPSK-DSSS signal and improving the robustness of this invention against large jitter interference.

[0040] The digital baseband signal generation module includes a spreading unit, a mapping unit, a zero-value interpolation unit, a shaping filter unit, and a decimation unit. The I-channel information, after passing through the spreading unit, becomes a 0,1 sequence, and the Q-channel information also becomes a 0,1 sequence. The mapping unit outputs a sampling rate of R0. chip The UQPSK-DSSS signal s1(n) is obtained by using a zero-value interpolation unit to insert zero points between adjacent sampling points of the sequence s1(n), thereby increasing the sampling rate of the digital signal and obtaining a sampling rate of D×f. s The sequence s2(n) is used; the shaping filter unit is a root-raised cosine filter, which outputs a smoothed sequence s3(n); the decimation unit directly decimates the sequence s3(n) by integer multiples to obtain the result with the DAC sampling rate f. s The digital baseband signal s4(n) is consistent with the digital baseband signal s4(n); the digital baseband signal s4(n) is converted into a baseband analog modulation signal by a digital-to-analog converter (DAC), and the analog signal is transmitted through a coaxial cable.

[0041] The matched filtering module performs matched filtering on the digital signal sampled by the ADC to obtain the digital baseband signal x(n). The matched filter is a root-raised cosine filter with the same roll-off factor as the shaping filter unit at the transmitting end.

[0042] The code ring module processes the digital baseband signal x(n), stripping away the spreading code and demodulating the I-channel information. The integration clearing unit, based on the principle of a direct digital frequency synthesizer, uses the code ring frequency control word to generate a local PN code with the same frequency and phase as the received PN code c1(n). The input signal is correlated with the local PN code and subjected to integral clearing operations to remove the spreading code from the received signal and demodulate the original information of the spreading branch. The phase detection and loop filtering unit obtains the phase detection error of the current code loop based on the integration result of the integral clearing unit, filters out noise information in the phase detection error to obtain the updated code loop frequency control word, and feeds it back to the integral clearing unit. Preferably, the phase detection and loop filtering unit adopts a normalized lead-lag power phase detector and a second-order loop.

[0043] The timing deviation estimation module constructs a normalized timing error demodulation model for the non-spread spectrum branch based on the fully aligned coupling characteristics of the I and Q channels of the UQPSK-DSSS signal; and normalizes it to [0,L] based on the NCO phase accumulation in the code ring required for demodulation of the I channel (measurement and control link). pn Take the decimal part after ) L pn Given the length of a periodic PN code, the NCO of the Q-way symbol is obtained. Q Phase cumulative amount; NCO of Q-path symbol Q Substituting the phase cumulative value into the normalized timing error demodulation model, the normalized timing deviation estimate of the non-spread spectrum branch is obtained through linear interpolation.

[0044] The symbol interpolation module reads the corresponding sampling point of the input signal based on the normalized timing deviation estimate output by the timing deviation estimation module. Combining this with the current normalized timing deviation estimate, it uses the symbol interpolation algorithm to interpolate the optimal sampling point for the current symbol, i.e., the timing synchronization result of the non-spread spectrum branch. Preferably, the symbol interpolation algorithm uses the Farrow interpolation formula.

[0045] Beneficial effects:

[0046] 1. The timing synchronization method and system for UQPSK-DSSS signals disclosed in this invention reduces the large jitter caused by non-integer multiple oversampling by replacing the traditional digital interpolation at the transmitting end with three units: zero-value interpolation, shaping filtering, and decimation. This ensures the stability of normal tracking operation after the loop is locked and improves the robustness of the system to large jitter interference.

[0047] 2. The timing synchronization method and system for UQPSK-DSSS signals disclosed in this invention, by adding a timing deviation estimation module and a symbol interpolation module at the receiving end, utilizes the fully aligned coupling characteristic of UQPSK-DSSS signals and the stable characteristic of the NCO phase accumulation in the delay-locked loop to achieve joint demodulation of the measurement and control link and the data transmission link using only the NCO phase accumulation, without excessive calculation process, thus saving resources.

[0048] 3. The timing synchronization method and system for UQPSK-DSSS signals disclosed in this invention uses the phase accumulation of the code ring NCO to estimate the normalized timing deviation estimate of the accurate non-spread spectrum branch, and supplements it with symbol interpolation to achieve accurate bit timing synchronization of UQPSK-DSSS signals under low oversampling rate. Compared with the traditional direct decimation scheme, it reduces the requirement for ADC sampling rate. Attached Figure Description

[0049] Figure 1 This is a structural block diagram of the present invention, "A timing synchronization method and system for UQPSK-DSSS signals";

[0050] Figure 2 This is a flowchart of Embodiment 1 of the present invention, "A timing synchronization method and system for UQPSK-DSSS signals";

[0051] Figure 3 This is a flowchart of step 1 of embodiment 1 of the present invention, "A timing synchronization method and system for UQPSK-DSSS signals".

[0052] Figure 4 It is the output sequence of the mapping unit, zero-value interpolation unit, shaping filter unit, and decimation unit in the digital baseband signal generation module of the transmitting end.

[0053] Figure 5 This is a flowchart of step 5 of embodiment 1 of the present invention, "A timing synchronization method and system for UQPSK-DSSS signals".

[0054] Figure 6 The cumulative phase of the code ring NCO and the symbol NCO of the Q-path are the values ​​after the loop stabilizes when the UQPSK signal signal-to-noise ratio is 15dB. Q Phase accumulation;

[0055] Figure 7 This is a constellation diagram of the digital baseband signal, the output of the integration clearing unit, and the output of the symbol interpolation module when the UQPSK signal signal-to-noise ratio is 15dB. Detailed Implementation

[0056] To make the present invention clearer and more understandable, the present invention will be further described clearly and in detail below with reference to the accompanying drawings and specific embodiments.

[0057] Example 1:

[0058] To verify the feasibility of this method, a simulation was conducted with an I-channel information rate of 204.8 Kbps, a Q-channel information rate of 30.1056 Mbps, and both ADC and DAC sampling rates of 120 MHz. The spreading ratio was 147, and the chip rate of the spread I-channel was the same as that of the Q-channel. Other simulation conditions were as follows: the power ratio of the I and Q signals was 1:10, and the transmit / receive clock offset was 100 ppm.

[0059] like Figure 1As shown, this invention discloses a timing synchronization system for UQPSK-DSSS signals. The transmitting end digital baseband signal generation module 1 includes a spreading unit 1, a mapping unit 2, a zero-value interpolation unit 3, a shaping filter unit 4, and a decimation unit 5. The digital signal obtained after sampling by the receiving end ADC is passed through a matched filter module 2, a code loop module 3, a timing deviation estimation module 4, and a symbol interpolation module 5 to obtain the mixed bit timing synchronization result of the UQPSK-DSSS signal. The code loop module 3 includes an integration clearing unit 6 and a phase detection and loop filtering unit 7. Digital baseband signal generation module 1 generates a UQPSK-DSSS digital baseband signal to be transmitted with the same sampling rate as the DAC; spreading unit 1 completes I-channel spreading; mapping unit 2 maps two 0,1 sequences into a UQPSK signal with an I:Q power ratio of 1:10 and a sampling rate of 30.1056MHz; zero-value interpolation unit 3 increases the sampling rate of the UQPSK signal to 960MHz through zero-placing operation; shaping filtering unit 4 smooths the interpolated 960MHz sampling rate UQPSK signal; decimation unit 5 performs 8x decimation to achieve downsampling and thus obtain a 120MHz sampling rate digital baseband signal to be transmitted. Matched filtering module 2 performs matched filtering on the digital baseband signal sampled by the ADC using a root-raised cosine filter; after the code ring module 3 stabilizes the loop, it strips the spreading code from the digital baseband signal and demodulates the I-channel information; the integration clearing unit 6 in the code ring module 3 generates a local PN code for correlation calculation to strip the PN code from the received signal; the phase detection and loop filtering unit 7 in the code ring module 3 obtains the phase detection error of the current loop and updates the frequency control word; the timing deviation estimation module 4 obtains the normalized timing deviation estimate of the UQPSK signal based on the phase accumulation of the code ring NCO; the symbol interpolation module 5 interpolates the optimal sampling point of the UQPSK signal based on the normalized timing deviation estimate and demodulates the Q-channel information.

[0060] like Figure 2 As shown, this invention discloses a method for hybrid bit timing synchronization of UQPSK-DSSS signals, and the specific implementation steps are as follows:

[0061] S1: Digital baseband signal generation module 1 generates a UQPSK-DSSS digital baseband signal to be transmitted with a chip rate of 30.1056MHz and a sampling rate of 120MHz. The specific implementation method is as follows: Figure 3 As shown.

[0062] S1.1: The {0,1} sequence with an I-channel information rate of 204.8Kbps is spread through the spreading unit 1 and then input together with the {0,1} sequence with a Q-channel information rate of 30.1056Mbps into the mapping unit 2 to obtain a UQPSK signal with an I:Q power ratio of 1:10 and a sampling rate of 30.1056MHz. Figure 4 The sequence s1(n) is shown.

[0063] S1.2: Input the sequence s1(n) obtained in S1.1 into the zero-value interpolation unit 3, and insert 30 or 31 zero-value points between adjacent sampling points of the sequence s1(n) to obtain a sequence with a sampling rate of 960MHz. Zero-value interpolation uses NCO. tx Phase accumulation is achieved, NCO tx Quantized to a 48-bit integer, with each increment being 30.1056M / 960M×2. 48 NCO tx Each accumulation outputs a new sampling point. If overflow occurs, the next point of sequence s1(n) is output; otherwise, zero is output. This achieves zero-value interpolation with 30 or 31 sampling points. For example... Figure 4 The sequence s2(n) is shown.

[0064] S1.3: Shaping filter unit 4 smooths the sequence s2(n) using a root-raised cosine filter to obtain a sequence s3(n) with a sampling rate of 960MHz, as shown below. Figure 4 The sequence s3(n) is shown.

[0065] S1.4: Extraction unit 5 performs an 8-fold decimation on sequence s3(n), that is, on the sampling data points of sequence s3(n), one point is taken every 7 points to reduce the sampling rate, forming a new sequence s4(n) with a sampling rate of 120MHz, such as... Figure 4 The sequence s4(n) is shown.

[0066] S1.5: The sequence s4(n) with a sampling rate of 120MHz is converted into an analog modulated signal by a digital-to-analog converter (DAC), and the analog signal is transmitted through a coaxial cable.

[0067] S2: Matched filtering module 2 performs matched filtering on the 120MHz digital signal obtained by the ADC sampling to obtain the digital baseband signal x(n), as shown in equation (1). The I and Q signals are shown in equation (2). The matched filter is a root-raised cosine filter with the same roll-off factor as the shaping filter unit 4 in the digital baseband signal generation module 1 at the transmitting end. The constellation diagram of the output result of the matched filtering module is shown in equation (2). Figure 7 As shown in (a).

[0068] S3: The integral clearing unit 6, based on the principle of direct digital frequency synthesizer, generates a local PN code with the same frequency and phase as the received PN code c1(n) under the control of the code ring frequency control word FCW. The input signal is correlated with the local PN code and then subjected to integration and clearing operations. The integration time is the length L of one PN code cycle. pn The instantaneous branch integral clearing operation expression is shown in Equation (3); the coherent integral results of the leading and lagging branches are shown in Equations (7) and (8), respectively.

[0069]

[0070]

[0071] When the code ring achieves ideal synchronization, equation (3) can be simplified to equation (4), i.e., the local PN code of the branch. Alignment with the PN code c1(n) of the received signal, correlation operation The result reaches its maximum value, and the instantaneous branch coherent integration result is the I-path position timing synchronization result. The constellation diagram of the coherent integration result is as follows: Figure 7 As shown in (b).

[0072] In a direct digital frequency synthesizer (DCE), the code ring NCO phase accumulator accumulates gradually from zero, with each increment equal to the current frequency control word. The code ring NCO phase accumulator update model is as follows:

[0073] NCO(n)=NCO(n-1)+FCW(n-1) (9)

[0074] S4: The phase detection and loop filtering unit 7 obtains the phase detection error of the current loop based on the coherent integration results of the lead and lag branches; it filters out noise in the phase detection error of the code loop through the loop filter, so that the filtering result truly reflects the phase change of the filter input signal and updates the frequency control word.

[0075] Based on the coherent integration results of the lead and lag branches, the phase detection error of the code ring is obtained using a normalized lead-lag power phase detector.

[0076]

[0077] Using a second-order loop, the filter system function is:

[0078]

[0079] Where K is the loop gain, which can be directly set to 1; ω n The characteristic frequency is equal to the loop equivalent noise bandwidth B. L The relationship is B L =ω n [ξ+1 / (4ξ)] / 2, loop equivalent noise bandwidth B L Take 50Hz; ξ is the damping coefficient, and the optimal value is... T symbol This is the loop update cycle, equivalent to the I-path symbol cycle of 1 / 204.8 × 10⁻⁶. 3 Seconds, substituting into equation (11), the filter system function is:

[0080]

[0081] The output of the phase detection and loop filtering unit 7 is the frequency control word FCW, which is fed back to the integration clearing unit 6 to update the phase accumulation of the code ring NCO.

[0082] S5: Timing Deviation Estimation Module 4 constructs a normalized timing error demodulation model for the non-spread spectrum branch based on the fully aligned coupling characteristics of the I and Q paths of the UQPSK-DSSS signal; based on the NCO phase accumulation in the code ring required for demodulation of the I path (measurement and control link), it is normalized to [0, 147) and the fractional part is taken to obtain the NCO of the Q path symbol. Q Phase cumulative amount; NCO of Q-path symbol Q Substituting the phase cumulative value into the normalized timing error demodulation model, the normalized timing error estimate of the non-spread spectrum branch is obtained through linear interpolation. The specific implementation method is as follows: Figure 5 As shown.

[0083] S5.1: Normalize the NCO cumulant to the range [0, 147), the PN code period is 147, as follows. Figure 6 As shown in (a). After the loop achieves ideal synchronization, one cycle of the NCO code corresponds to one cycle of the received PN code, which is 147 chips, approximately 147 × 4 = 588 sampling points, and... Figure 6 The simulation results shown in (a) are consistent. The NCO cumulative quantity is rounded down to obtain the address of the local PN code, and the address range is [0, 147).

[0084] S5.2: Take the fractional part of the normalized code NCO and name it NCO. Q ,like Figure 6 As shown in (b). NCO Q The accumulation period corresponds to one cycle of a Q-channel symbol. In this embodiment, the sampling rate is 120MHz, the Q-channel information rate is 30.1056Mbps, and each Q-channel symbol has 3 to 4 sampling points. Figure 6 (b) shows the Q-path symbol in the magnified partial view, which represents 4 sampling points.

[0085] S5.3: NCO Q One cycle of [0,1) corresponds to one cycle of the Q-path symbol. Further, we can obtain that NCO... Q The optimal sampling point for the Q-path symbol is when NCO = 0.5. Q (n)≤0.5, NCO Q When (n+1) > 0.5, it means that there exists an optimal sampling point between the nth sampling point and the (n+1)th sampling point. Figure 6 (b) shows that there is an optimal sampling point between the 912th and 913th sampling points.

[0086] S5.4: The formula for calculating the normalized timing deviation estimate is shown in equation (5). Figure 6(b) The normalized timing bias estimate of the optimal sampling point shown in the enlarged view is...

[0087]

[0088] S6: The first term in equation (2) contains Q-channel information, and the second term is noise. Extracting the optimal sampling point from these terms yields the Q-channel bit timing synchronization result. Combining the normalized timing deviation estimate output by timing deviation estimation module 4, the corresponding sampling point in equation (2) is read. Using Farrow interpolation, the sign interpolation module 5 can calculate the optimal sampling point, thus achieving joint demodulation of the I-channel (measurement and control link) and Q-channel (data transmission link), thereby realizing the hybrid bit timing synchronization of the UQPSK-DSSS signal. Figure 6 (b) As shown in the enlarged view, sampling points 911, 912, 913, and 914 share the same symbol. The optimal sampling point is between 912 and 913. The normalized timing bias estimate is shown in equation (13). Using Farrow cubic interpolation, the optimal sampling point at this point can be obtained as follows:

[0089]

[0090] At a signal-to-noise ratio of 15dB, the constellation diagram output by symbol interpolation module 5 is as follows: Figure 7 As shown in (c), with Figure 7 (a) Compared with the input signal, the Q channel information can be completely distinguished. After demodulation, the amplitude ratio of the I and Q channels is about 1:3, which is consistent with the I and Q power ratio of 1:10 set in the simulation conditions. The demodulation is correct and the Q channel position timing synchronization is completed.

[0091] The above detailed description further illustrates the purpose, technical solution, and beneficial effects of the invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for implementing hybrid bit timing synchronization of UQPSK-DSSS signals, characterized in that: Includes the following steps, Step 1: The source I channel is low-speed data, and the Q channel is high-speed data. The spread spectrum I channel and the non-spread spectrum Q channel are mapped to obtain the UQPSK-DSSS signal. Through interpolation-filtering-decimation sampling rate transformation, based on the characteristic that high sampling rates can reduce the adverse effects of non-integer multiple oversampling, the large-scale jitter caused by non-integer multiple oversampling is reduced, resulting in a modulated digital baseband signal. After mapping, the signal is interpolated with zero values ​​to ensure that the chip information of the spread spectrum branch and the symbol information of the non-spread spectrum branch have complete alignment coupling. The digital baseband signal is converted into an analog signal by a digital-to-analog converter (DAC), and the analog signal is transmitted through a coaxial cable. Step 2: Perform matched filtering on the digital signal sampled by the ADC to obtain the digital baseband signal x(n); the matched filter is a root-raised cosine filter with the same roll-off factor as the shaping filter unit at the transmitting end. Step 3: Based on the principle of direct digital frequency synthesizer, a local PN code with the same frequency and phase as the received PN code c1(n) is generated by the code ring frequency control word FCW. In the direct digital frequency synthesizer, the phase accumulation of the code ring NCO gradually accumulates from zero, with each increment being the current frequency control word. The input signal and the local PN code are correlated and integrated to remove the PN code from the received signal, thus obtaining the I-channel bit timing synchronization result. Step 4: Input the coherent integration results of the lead and lag branches into the code ring phase detector to obtain the phase detection error of the code ring; filter out the noise in the phase detection error of the code ring through the loop filter so that the filtering result truly reflects the phase change of the filter input signal. Step 5: Construct a normalized timing error demodulation model for the non-spread spectrum branch based on the fully aligned coupling characteristics of the I and Q paths of the UQPSK-DSSS signal; obtain the NCO of the Q path symbol based on the NCO phase accumulation in the code ring required for I path demodulation. Q Phase accumulation; Based on the normalized timing error demodulation model, the normalized timing deviation estimate of the non-spread spectrum branch is obtained through linear interpolation. Step 6: Perform interpolation on the input signal based on the timing deviation estimate, and use the existing information of the spread spectrum branch to obtain the optimal sampling point of the non-spread spectrum branch, that is, realize the joint demodulation of the I and Q paths, and thus realize the mixed bit timing synchronization of the UQPSK-DSSS signal.

2. The method for hybrid bit timing synchronization of UQPSK-DSSS signals as described in claim 1, characterized in that: Step 1 is implemented as follows: Step 1.1: The I-channel information is d1(n), the Q-channel information is d2(n), and the spreading code is c1(n). The chip rate of the spread I-channel is the same as the information rate of the Q-channel. The spread I-channel is directly mapped to the unspread Q-channel to obtain a sampling rate of R. chip The UQPSK-DSSS signal s1(n), R chip The chip rate after I-channel spread spectrum; Step 1.2: The sampling rate of the DAC is f s D is a positive integer. Zero-value interpolation is used to insert zero-value points between adjacent sampling points of the sequence s1(n) obtained in step 1.1, resulting in a sampling rate of D×f. s The sequence s2(n); Step 1.3: Input the sequence s2(n) obtained in Step 1.2 into the root-raised cosine filter to obtain a sampling rate of D×f. s The sequence s3(n) is transformed more slowly than the sequence s2(n); Step 1.4: For sampling rates D×f s The sequence s3(n) is sampled to reduce the sampling rate. Specifically, every D-1 sampling points in the sequence s3(n) are taken to form a new sampling rate of f. s The sequence s4(n); Step 1.5: The sampling rate is f s The sequence s4(n) is converted into an analog modulated signal by a digital-to-analog converter (DAC), and the analog signal is transmitted through a coaxial cable.

3. The method for hybrid bit timing synchronization of UQPSK-DSSS signals as described in claim 2, characterized in that: In step 2, The analog-to-digital converter (ADC) receives baseband analog signals, and its sampling rate is the same as that of the DAC, both being f. s The digital baseband signal obtained after ideal matched filtering is Where P1 is the signal power of the I-path, P2 is the signal power of the Q-path, and the power ratio p = P2 / P1 > 1; d1(n) and d2(n) ∈ {-1, 1} are the data sequences of the I-path and Q-path, respectively; c1(n) ∈ {-1, 1} is the PN code sequence used for direct sequence spread spectrum; and n(n) is the Gaussian white noise signal. The I and Q signals are denoted as i(n) and q(n) respectively: Where, n I (n), n Q (n) is a Gaussian white noise signal.

4. The method for hybrid bit timing synchronization of UQPSK-DSSS signals as described in claim 1, characterized in that: The interpolation operation described in step 6 uses the Farrow interpolation formula.

5. The method for hybrid bit timing synchronization of UQPSK-DSSS signals as described in claim 2, characterized in that: The zero-value interpolation described in step 1.2 is implemented using NCO phase accumulation. The NCO is quantized into an N-bit integer, and the increment for each step is R. chip / (D×f s )×2 N The NCO outputs a new sampling point each time it accumulates. When it overflows, it outputs the known sequence s1(n). When it does not overflow, it outputs zero value, thus realizing zero value interpolation. The code ring phase detector adopts a normalized lead-hysteresis power phase detector; the loop filter adopts a second-order loop to stabilize the sampling error caused by clock bias.

6. A timing synchronization system for UQPSK-DSSS signals, used to implement the hybrid bit timing synchronization method for UQPSK-DSSS signals as described in claim 1 or 2, characterized in that: The transmitting end of the timing synchronization system includes a digital baseband signal generation module; The receiving end of the timing synchronization system adds a timing deviation estimation module and a symbol interpolation module to the traditional code ring. The code ring includes an integration and clearing unit and a phase detection and loop filtering unit. The zero-value interpolation unit, shaping filtering unit, and decimation unit work together to replace the traditional digital interpolation. Through sampling rate transformation, it utilizes the characteristic of low signal jitter at high sampling rates to reduce signal jitter caused by non-integer multiple oversampling. The timing deviation estimation module constructs a normalized timing error demodulation model for the non-spread spectrum branch based on the fully aligned coupling characteristics of the I and Q paths of the UQPSK-DSSS signal. Based on the NCO phase accumulation of the code ring required for demodulation of the telemetry and control link, it obtains the NCO of the Q-path symbol. Q Phase cumulative amount, the NCO of the Q-path symbol Q The phase accumulator is substituted into the normalized timing error demodulation model to obtain the timing deviation estimate of the non-spread spectrum branch. The symbol interpolation module performs interpolation on the input signal based on the timing deviation estimate to obtain the optimal sampling point of the non-spread spectrum branch. By replacing the traditional digital interpolation at the transmitter with three units: zero-value interpolation, shaping filtering, and decimation, the large jitter caused by non-integer multiple oversampling is reduced. While ensuring the fully aligned coupling characteristics of the I and Q paths of the UQPSK-DSSS signal, the phase accumulator of the code ring NCO remains stable. At the same time, by adding a timing deviation estimation module and a symbol interpolation module, in the case of large jitter in the non-integer multiple oversampling signal system, the fully aligned coupling characteristics of the UQPSK-DSSS signal and the stable characteristics of the code ring NCO phase accumulator are utilized. The joint demodulation of the measurement and control link and the data transmission link is achieved using only the code ring NCO phase accumulator, thereby realizing the hybrid bit timing synchronization of the UQPSK-DSSS signal. The digital baseband signal generation module includes a spreading unit, a mapping unit, a zero-value interpolation unit, a shaping filter unit, and a decimation unit. The I-channel information, after passing through the spreading unit, becomes a 0,1 sequence, and the Q-channel information also becomes a 0,1 sequence. The mapping unit outputs a sampling rate of R0. chip The UQPSK-DSSS signal s1(n) is obtained by using a zero-value interpolation unit to insert zero points between adjacent sampling points of the sequence s1(n), thereby increasing the sampling rate of the digital signal and obtaining a sampling rate of D×f. s The sequence s2(n) is used; the shaping filter unit is a root-raised cosine filter, which outputs a smoothed sequence s3(n); the decimation unit directly decimates the sequence s3(n) by integer multiples to obtain the result with the DAC sampling rate f. s A consistent digital baseband signal s4(n); the digital baseband signal s4(n) is converted into a baseband analog modulation signal by a digital-to-analog converter (DAC), and the analog signal is transmitted through a coaxial cable; The matched filtering module performs matched filtering on the digital signal sampled by the ADC to obtain the digital baseband signal x(n); the matched filter is a root-raised cosine filter with the same roll-off factor as the shaping filter unit at the transmitting end. The code ring module processes the digital baseband signal x(n), stripping away the spreading code and demodulating the I-channel information. The integration and clearing unit, based on the principle of a direct digital frequency synthesizer, uses the code ring frequency control word to generate a local PN code with the same frequency and phase as the received PN code c1(n). The input signal is correlated with the local PN code and integrated clearing is performed to remove the spreading code from the received signal and demodulate the original information of the spreading branch. The phase accumulation of the code ring NCO in the direct digital frequency synthesizer is gradually increased from zero, and the amount of each increase is the current frequency control word. The phase detection and loop filtering unit obtains the phase detection error of the current code ring based on the integration result of the integrated clearing unit, filters out the noise information in the phase detection error to obtain the updated code ring frequency control word, and feeds it back to the integrated clearing unit. The timing error estimation module constructs a normalized timing error demodulation model for the non-spread spectrum branch based on the fully aligned coupling characteristics of the I and Q channels of the UQPSK-DSSS signal; and normalizes it to [0,L] based on the NCO phase accumulation in the code ring required for I-channel demodulation. pn Take the decimal part after ) L pn Given the length of a periodic PN code, the NCO of the Q-way symbol is obtained. Q Phase cumulative amount; NCO of Q-path symbol Q Substituting the phase accumulation into the normalized timing error demodulation model, the normalized timing deviation estimate of the non-spread spectrum branch is obtained through linear interpolation. The symbol interpolation module reads the corresponding sampling point of the input signal based on the normalized timing deviation estimate output by the timing deviation estimation module. Combining the current specific normalized timing deviation estimate, it uses the symbol interpolation algorithm to interpolate the current optimal sampling point of the symbol, which is the timing synchronization result of the non-spread spectrum branch.

7. The timing synchronization system for UQPSK-DSSS signals as described in claim 6, characterized in that: The phase detection and loop filtering unit adopts a normalized lead-lag power phase detector and a second-order loop; the sign interpolation algorithm is implemented using the Farrow interpolation formula.

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