1.5 divider based on a delay locked loop

Abstract

The application relates to the technical field of integrated circuits, and discloses a 1.5 frequency divider based on a delay-locked loop, which comprises a divide-by-1.5 frequency divider and a delay-locked loop, wherein the delay-locked loop comprises a voltage-controlled delay unit, a phase detector, a low-pass filter and an error amplifier. The divide-by-1.5 frequency divider outputs a frequency-divided signal with a duty cycle of 1 / 3 and a frequency-dividing ratio of 1.5 to the phase detector and the voltage-controlled delay unit according to a pair of noninverted and inverted clock signals, the voltage-controlled delay unit outputs the frequency-divided signal to the phase detector after delaying for a certain time. The phase detector performs logical operation on the frequency-divided signal and the delayed frequency-divided signal to form a frequency-divided signal with a duty cycle of 1 / 2 and convert the frequency-divided signal into a pair of differential signals. The pair of differential signals are sequentially output to the voltage-controlled delay unit through the low-pass filter and the error amplifier.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit, and particularly relates to a 1.5 frequency divider based on a delay-locked loop. BACKGROUND

[0002] Suppose that a frequency synthesizer can generate a signal with a two times frequency range, then a voltage-controlled oscillator with a two times tuning frequency range is needed, but it is generally difficult to realize a voltage-controlled oscillator with a two times tuning frequency range, because there is a trade-off between the tuning range and the noise of the voltage-controlled oscillator. In the actual design process, two voltage-controlled oscillators are generally needed to realize a two times tuning frequency coverage, but this greatly increases the cycle of circuit design and the area occupied by the circuit. Suppose that there is a divide-by-1.5 frequency divider with a 50% duty cycle, then the tuning range of the voltage-controlled oscillator can be reduced by one third, so that a resonant cavity can meet the design goal. There are several methods to realize a 1.5 frequency divider at present:

[0003] 1. The signal is divided by three through a logic circuit, and then a phase-locked loop structure based on a ring oscillator is used to realize 2 times frequency, and finally the function of 1.5 frequency division is realized. The noise performance of the ring oscillator is poor, and it is not suitable for use in high-speed high-precision applications. And because the scheme based on the phase-locked loop technology needs to consider the tuning range of the ring oscillator, the stability of the phase-locked loop, and other problems, the design complexity of the system is greatly increased.

[0004] 2. The signal is divided by three through a logic circuit, and then 2 frequency division is realized through sub-harmonic injection locking, which can also realize the function of 1.5 frequency division. But this scheme needs an extra resonant cavity, which greatly increases the area of the loop, and the injection locking technology will bring a relatively large spur, which will greatly worsen the fixed jitter of the output signal, and it is difficult to realize the 50% duty cycle output of the output signal.

[0005] 3. The input clock signal and the signal with one third of the input clock frequency are mixed, and then the signal obtained by mixing is low-pass filtered to obtain a signal with two thirds of the input clock frequency. The 1.5 frequency divider based on the mixer structure has difficult-to-filter spurs, which greatly worsen the fixed jitter of the output signal, and it is difficult to realize the 50% duty cycle output of the output signal, which limits the wide application of the scheme. SUMMARY

[0006] The purpose of the present application is to provide a 1.5 frequency divider based on a delay-locked loop, which reduces the tuning range of the voltage-controlled oscillator.

[0007] The application discloses a 1.5 divider based on a delay-locked loop, comprising: a divide-by-1.5 divider and a delay-locked loop, the delay-locked loop comprising a voltage-controlled delay unit, a phase detector, a low-pass filter and an error amplifier;

[0008] The divide-by-1.5 divider outputs a frequency-divided signal with a duty cycle of 1 / 3 and a frequency-divided ratio of 1.5 to the phase detector and the voltage-controlled delay unit according to a pair of non-inverted and inverted clock signals, and the voltage-controlled delay unit outputs the frequency-divided signal to the phase detector after a certain time delay.

[0009] The phase detector performs logical operation on the frequency-divided signal and the time-delayed frequency-divided signal to form a frequency-divided signal with a duty cycle of 1 / 2 and convert the frequency-divided signal into a pair of differential signals.

[0010] The pair of differential signals are sequentially output to the voltage-controlled delay unit through the low-pass filter and the error amplifier.

[0011] In a preferred embodiment, the divide-by-1.5 divider comprises:

[0012] a divide-by-3 divider, the divide-by-3 divider comprising a first flip-flop, a second flip-flop and a first NAND logic, the pair of non-inverted and inverted clock signals being coupled to the first flip-flop and the second flip-flop, an output terminal of the first flip-flop being connected to a first input terminal of the first NAND logic, an output terminal of the first NAND logic being connected to an input terminal of the second flip-flop, an output terminal of the second flip-flop being connected to a second input terminal of the first NAND logic and an input terminal of the first flip-flop;

[0013] a frequency multiplier, the frequency multiplier comprising a third flip-flop, a latch, a first NOR logic, a second NOR logic and a third NOR logic, the pair of non-inverted and inverted clock signals being coupled to the third flip-flop and the latch, an output terminal of the first NAND logic being connected to an input terminal of the latch, an output terminal of the latch and the non-inverted clock signal being coupled to two input terminals of the second NOR logic, an output terminal of the second flip-flop being connected to an input terminal of the third flip-flop, an output terminal of the third flip-flop and the inverted clock signal being coupled to two input terminals of the first NOR logic, an output terminal of the first NOR logic and an output terminal of the second NOR logic being coupled to two input terminals of the third NOR logic, the third NOR logic outputting the frequency-divided signal with the duty cycle of 1 / 3 and the frequency-divided ratio of 1.5.

[0014] In a preferred embodiment, the first flip-flop, the second flip-flop and the third flip-flop are D flip-flops.

[0015] In one preferred embodiment, the phase detector comprises a second NAND logic, a first inverter, a second inverter and a single-ended to differential unit, the divided frequency signal and the delayed divided frequency signal are connected to two inputs of the second NAND logic respectively, an output of the second NAND logic is connected to an input of the first inverter, an output of the first inverter is connected to an input of the second inverter and an input of the single-ended to differential unit, the second inverter and the single-ended to differential unit output the pair of differential signals respectively.

[0016] In one preferred embodiment, the phase detector further comprises a third inverter and a fourth inverter, an output of the second inverter is connected to an input of the third inverter and an output of the fourth inverter, outputs of the third inverter and an input of the fourth inverter are connected to outputs of the single-ended to differential unit.

[0017] In one preferred embodiment, the low pass filter extracts a direct current component of the pair of differential signals, the differential amplifier amplifies a difference of the direct current component of the pair of differential signals and outputs a delay control signal to the voltage controlled delay unit.

[0018] In one preferred embodiment, the differential amplifier is an auto-zero amplifier, a chopper amplifier or a mismatch calibration amplifier.

[0019] In one preferred embodiment, the voltage controlled delay unit comprises first to fourth PMOS transistors and first to fourth NMOS transistors, sources of the first to third PMOS transistors are connected to a power supply terminal, a gate of the third PMOS transistor is connected to the power supply terminal, a gate and a drain of the first PMOS transistor are connected to a gate of the second PMOS transistor and a drain of the first NMOS transistor, drains of the second and third PMOS transistors are connected to a source of the fourth PMOS transistor, a gate of the fourth PMOS transistor and a gate of the fourth NMOS transistor are connected to the divided frequency signal, sources of the first to third NMOS transistors are connected to a ground terminal, a gate of the third NMOS transistor is connected to the ground terminal, gates of the first and second NMOS transistors are connected to the delay control signal, drains of the second and third NMOS transistors are connected to a source of the fourth NMOS transistor, a drain of the fourth PMOS transistor and a drain of the fourth NMOS transistor are connected to an input of a fifth inverter, an output of the fifth inverter outputs the delayed divided frequency signal.

[0020] In one preferred embodiment, the delay control signal controls a bias current of the voltage controlled delay unit.

[0021] In one preferred embodiment, the voltage controlled delay unit delays the divided frequency signal by 1 / 6 period.

[0022] Compared with the prior art, the 1.5 divider based on the delay-locked loop of the application has the following beneficial effects:

[0023] 1. Since the loop stability of the delay-locked loop is good, it is convenient for designers to design, and the delay-locked loop can have multiple implementation modes (such as being implemented through a digital control loop, or being implemented through an analog control loop, being allowed to work in a background calibration mode, or being allowed to work in a forward calibration mode), and can adapt to application requirements in different scenarios.

[0024] 2. Meanwhile, the delay-locked loop can be used in high-speed and high-precision applications, since only the delay unit and the phase discriminator module in the delay-locked loop need to work at a high frequency, the delay-locked loop can achieve a very high working frequency and a very low power consumption.

[0025] 3. The delay-locked loop can accurately achieve an output signal with a duty cycle of 50%.

[0026] 4. Since only one sixth of the duty cycle needs to be adjusted, the voltage-controlled delay unit does not introduce too much noise, and thus the output jitter can be relatively small.

[0027] 5. The circuit can be implemented using simple analog circuits, and does not need large-area passive capacitors and passive inductors, thus greatly reducing the area of the circuit and saving costs.

[0028] A large number of technical features are described in the specification and are distributed in various technical solutions. If all possible combinations (i.e., technical solutions) of technical features of the present application are listed, the specification will be too long. In order to avoid this problem, each technical feature disclosed in the above summary of the application, each technical feature disclosed in the following embodiments and examples, and each technical feature disclosed in the drawings can be freely combined to form various new technical solutions (which should be considered to have been described in the specification), unless such combination of technical features is technically infeasible. For example, features A+B+C are disclosed in one example, features A+B+D+E are disclosed in another example, features C and D are equivalent technical means that play the same role, and can only be used at a time, and feature E can be combined with feature C, then the solution of A+B+C+D should not be considered to have been described because it is technically infeasible, and the solution of A+B+C+E should be considered to have been described. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 A schematic diagram of a 1.5 divider based on a delay-locked loop in an embodiment of the application is shown.

[0030] Figure 2 A schematic diagram of a divide-by-1.5 divider in an embodiment of the application is shown.

[0031] Figure 3 A schematic diagram of a divide-by-3 divider in an embodiment of the application is shown.

[0032] Figure 4 A schematic diagram of a frequency multiplier in an embodiment of the application is shown.

[0033] Figure 5 A schematic diagram of a divide-by-1.5 divider in an embodiment of the application is shown.

[0034] Figure 6 A schematic diagram of a phase detector in an embodiment of the application is shown.

[0035] Figure 7 A schematic diagram of a phase detector in an embodiment of the application is shown.

[0036] Figure 8 A schematic diagram of a voltage-controlled delay unit in an embodiment of the application is shown. DETAILED DESCRIPTION

[0037] Various aspects and examples of the present application will now be described. The following description provides specific details for the purpose of providing a thorough understanding of, and an enabling

[0038] Additionally, some well-known structures or functions can not be shown or described in detail, in order to avoid unnecessarily obscuring the relevant description.

[0039] The terminology used in the description presented below is intended to be interpreted in its broadest reasonable manner, even though it is being used in conjunction with a detailed description of certain specific examples of the present application. Certain terms can even be emphasized below, but any terminology

[0040] An embodiment of the present application provides a 1.5 divider based on a delay-locked loop, Figure 1 A block diagram schematic of a 1.5 divider based on a delay-locked loop 100 is shown. The 1.5 divider 100 comprises a divide-by-1.5 divider 110 and a delay-locked loop 120. The delay-locked loop 120 comprises a voltage-controlled delay unit 121, a phase detector 122, a low-pass filter 123 and an error amplifier 124. The divide-by-1.5 divider 110 is connected to the voltage-controlled delay unit 121 and the phase detector 122, respectively. The voltage-controlled delay unit 121, the phase detector 122, the low-pass filter 123 and the error amplifier 124 are connected in sequence as a loop.

[0041] The divide-by-1.5 frequency divider 110 outputs a divide-by-1.5 frequency signal 1p5_out with a duty cycle of 1 / 3 and a frequency division ratio of 1.5 to the phase detector 122 and the voltage-controlled delay unit 121 according to a pair of non-inverted and inverted clock signals clk, clkb. The voltage-controlled delay unit 121 delays the divide-by-1.5 frequency signal 1p5_out for a certain time and outputs the delayed divide-by-1.5 frequency signal 1p5_delay to the phase detector 122.

[0042] The phase detector 122 performs a logical operation on the divide-by-1.5 frequency signal 1p5_out and the delayed divide-by-1.5 frequency signal 1p5_delay to form a divide-by-1.5 frequency signal with a duty cycle of 1 / 2 and converts the divide-by-1.5 frequency signal into a pair of differential signals outp, outn.

[0043] The pair of differential signals outp, outn are sequentially output to the voltage-controlled delay unit 121 through the low-pass filter 123 and the error amplifier 124.

[0044] In one embodiment, Figure 2 A block diagram of the divide-by-1.5 frequency divider 110 is shown. The divide-by-1.5 frequency divider 110 includes a divide-by-3 frequency divider 111 and a frequency multiplier 112. The divide-by-3 frequency divider 111 is coupled to a pair of non-inverted and inverted clock signals clk, clkb and generates three divide-by-3 frequency signals D1, D2, D3, and outputs two divide-by-3 frequency signals to the frequency multiplier 112. The frequency multiplier 112 performs a logical operation on the two divide-by-3 frequency signals according to the pair of non-inverted and inverted clock signals clk, clkb to form a divide-by-1.5 frequency signal 1p5_out with a duty cycle of 1 / 3 and a frequency division ratio of 1.5.

[0045] In one embodiment, Figure 3 A schematic diagram of the divide-by-3 frequency divider 111 is shown. The divide-by-3 frequency divider 111 includes a first flip-flop 1111, a second flip-flop 1112, and a first NAND logic 1113. The pair of non-inverted and inverted clock signals clk, clkb are coupled to the first flip-flop 1111 and the second flip-flop 1112. An output terminal of the first flip-flop 1111 is connected to a first input terminal of the first NAND logic 1113. An output terminal of the first NAND logic 1113 is connected to an input terminal of the second flip-flop 1112. An output terminal of the second flip-flop 1112 is connected to a second input terminal of the first NAND logic 1113 and an input terminal of the first flip-flop 1111.

[0046] In one embodiment, Figure 4A schematic diagram of the frequency multiplier 112 is shown. The frequency multiplier 112 includes a third flip-flop 1121, a latch 1122, a first NOR logic 1123, a second NOR logic 1124, and a third NOR logic 1125, the pair of non-inverted and inverted clock signals clk, clkb are coupled to the third flip-flop 1121 and the latch 1122, an output of the first NAND logic 1113 is connected to an input of the latch 1122 (i.e., the D2 path frequency-divided signal is output to the latch 1122), an output of the latch 1122 and the non-inverted clock signal clk are coupled to two inputs of the second NOR logic 1124, an output of the second flip-flop 1112 is connected to an input of the third flip-flop 1121 (i.e., the D3 path frequency-divided signal is output to the third flip-flop 1121), an output of the third flip-flop 1121 and the inverted clock signal clkb are coupled to two inputs of the first NOR logic 1123, an output of the first NOR logic 1123 and an output of the second NOR logic 1124 are coupled to two inputs of the third NOR logic 1125, the third NOR logic 1125 outputs the frequency-divided signal 1p5_out with a duty cycle of 1 / 3 and a frequency division ratio of 1.5. Figure 5 A waveform schematic diagram of the 1.5 frequency divider 110 is shown.

[0047] In one embodiment, the first flip-flop 1111, the second flip-flop 1112, and the third flip-flop 1121 are D flip-flops.

[0048] In one embodiment, Figure 6 A schematic diagram of the phase detector 122 is shown. The phase detector 122 includes a second NAND logic 1221, a first inverter 1222, a second inverter 12223, and a single-ended to differential unit 1224. The frequency-divided signal 1p5_out and the delayed frequency-divided signal 1p5_delay are connected to two inputs of the second NAND logic 1221, respectively, an output of the second NAND logic 1221 is connected to an input of the first inverter 1222, an output of the first inverter 1222 is connected to an input of the second inverter 1223 and an input of the single-ended to differential unit 1224, the second inverter 1223 and the single-ended to differential unit 1224 output the pair of differential signals outp, outn, respectively. Figure 7 A waveform schematic diagram of the phase detector 122 is shown.

[0049] In one embodiment, the phase detector 122 further comprises a third inverter 1225 and a fourth inverter 1226, an input of the third inverter 1225 and an output of the fourth inverter 1226 are connected to an output of the second inverter 1223, an output of the third inverter 1225 and an input of the fourth inverter 1226 are connected to an output of the single-ended to differential unit 1224.

[0050] With continued reference to Figure 1 As shown, the low pass filter 123 extracts the DC component of the pair of differential signals outp, outn, the differential amplifier 124 amplifies the difference of the DC component of the pair of differential signals outp, outn and outputs a delay control signal Vctrl to the voltage controlled delay unit 121.

[0051] In one embodiment, the differential amplifier 124 is an auto-zero amplifier, a chopper amplifier or a mismatch calibration amplifier. A general amplifier can also be used if it is insensitive to errors, the above are just typical low mismatch amplifiers.

[0052] In one embodiment, Figure 8A schematic diagram of the voltage-controlled delay unit 121 is shown. The voltage-controlled delay unit 121 includes a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4 and a fifth inverter 1211, the sources of the first PMOS transistor P1, the second PMOS transistor P2 and the third PMOS transistor P3 are connected to a power supply terminal, the gate of the third PMOS transistor P3 is connected to the power supply terminal, the gate and the drain of the first PMOS transistor P1 are connected to the gate of the second PMOS transistor P2 and the drain of the first NMOS transistor N1, the drains of the second PMOS transistor P2 and the third PMOS transistor P3 are connected to the source of the fourth PMOS transistor P4, the gate of the fourth PMOS transistor P4 and the gate of the fourth NMOS transistor N4 are connected to the divided frequency signal 1p5_out, the sources of the first NMOS transistor N1, the second NMOS transistor N2 and the third NMOS transistor N3 are connected to a ground terminal, the gate of the third NMOS transistor N3 is connected to the ground terminal, the gates of the first NMOS transistor N1 and the second NMOS transistor N2 are connected to the delay control signal Vctrl, the drains of the second NMOS transistor N2 and the third NMOS transistor N3 are connected to the source of the fourth NMOS transistor N4, the drain of the fourth PMOS transistor P4 and the drain of the fourth NMOS transistor N4 are connected to the input of the fifth inverter 1211, and the output of the fifth inverter 1211 outputs the delayed divided frequency signal 1p5_delay.

[0053] In one embodiment, the delay control signal Vctrl controls the bias current of the voltage-controlled delay unit 121.

[0054] In one embodiment, the voltage-controlled delay unit 121 delays the divided frequency signal 1p5_out by 1 / 6 period, i.e., the delayed divided frequency signal 1p5_delay is delayed by 1 / 6 period with respect to the divided frequency signal 1p5_out.

[0055] In this application, the delay-locked loop is applied to the 1.5 divider with an output duty cycle of 50%, and the output duty cycle of the 1.5 divider is adjusted to 50% by using the delay-locked loop.

[0056] The working process of the 1.5 divider based on the delay-locked loop in this application is described below.

[0057] As Figure 1As shown, the architecture of the circuit consists of a frequency divider with a frequency division ratio of 1.5 and a delay-locked loop, wherein the delay-locked loop comprises a voltage-controlled delay unit, a phase detector, a low-pass filter, and an error amplifier. Of course, the delay-locked loop in the figure can also be implemented by means of a digital loop control, and this article only provides an example of a delay-locked loop.

[0058] The frequency divider with a frequency division ratio of 1.5 and an output duty cycle of 1 / 3 is shown in FIG. 2. Figure 2 The module consists of two parts: one is a divide-by-3 frequency divider, and the other is a frequency multiplier. Among them Figure 3 is a specific implementation of the divide-by-3 frequency divider, Figure 4 is a specific implementation of the frequency multiplier. First, a signal with a frequency division ratio of 3 is generated by the divide-by-3 frequency divider, then the two re-timed signals with a frequency division ratio of 3 are selected by the non-inverted and inverted clocks respectively, and the two signals selected by the clock are combined by an OR-AND logic gate to generate an output signal with a frequency division ratio of 1.5 and a duty cycle of 1 / 3, which is equivalent to multiplying the signal with a frequency division ratio of 3. The signal waveforms of the nodes are shown in FIG. 3. Figure 5 , wherein T2, T4, T3, and T5 are the signals of the nodes in the frequency multiplier 112 of the output signal 1p5_out1. This article only provides an implementation example of a 1.5 frequency divider, and of course it is also feasible to implement the function of a 1.5 frequency divider by other logic circuits. The main idea of this article is to use a delay-locked loop to implement a high-speed 1.5 frequency divider with an output duty cycle of 50%. The effect of this article can be achieved by using other delay-locked loop structures.

[0059] The phase detector module is shown in FIG. 4. Figure 6 First, the 1p5_out signal obtained from the divide-by-1.5 frequency divider module is logically ANDed with the 1p5_delay signal, which is the delayed version of the signal. This can combine two signals with a duty cycle of 1 / 3 into a signal with a duty cycle of 1 / 2. Then the signal is converted from single-ended to differential. The differential output signal of this module is the output of the 1.5 frequency divider. The specific waveforms of the phase detector module are shown in FIG. 5. Figure 7 It should be understood that the use of single-ended implementation and differential implementation in specific circuits should be within the scope of protection of this article.

[0060] The differential signal output by the single-ended-to-differential module is low-pass filtered to obtain the DC component of the signal, from which the duty cycle information of the non-inverted and inverted output signals can be obtained. The DC components of the non-inverted and inverted signals are output to the non-inverted and inverted input terminals of the error amplifier, respectively, to amplify the difference between the duty cycles of the two signals. Assuming that the duty cycle of the non-inverted output signal is 50%, then the duty cycle of the inverted output signal is also 50%, i.e. the low-pass filtered DC components of the two signals are equal, achieving the function of an output duty cycle of 50%.

[0061] Since the offset voltage of the error amplifier will finally be reflected in the duty cycle error of the output signal in the form of the delay-locked loop, a low-offset-voltage error amplifier, such as an auto-zero amplifier, a chopping amplifier, an offset calibration amplifier, etc., is required to reduce the duty cycle error of the output signal, but this also depends on the application scenario (such as in an application environment with low requirements for the output duty cycle error).

[0062] The specific implementation of the voltage-controlled delay unit is shown in Figure 8 As shown in FIG. 5, the voltage-controlled delay module controls the size of the bias current in the voltage-controlled delay unit to achieve the adjustment of the delay size of the voltage-controlled delay unit. It should be understood that other delay unit modes can also be used in the present application, such as a digitally controlled delay unit, and the size of the bias current of the delay unit is adjusted by adjusting the load capacitance of the delay unit.

[0063] In the present application, the delay unit is used to achieve the function of 50% output duty cycle of the frequency divider with a frequency division ratio of 1.5.

[0064] It should be noted that in the application file of the present patent, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "including one" does not exclude the presence of another identical element in the process, method, article or device including the element. In the application file of the present patent, if it is mentioned that a certain action is performed according to a certain element, it means that the action is performed at least according to the element, which includes two cases: the action is performed only according to the element, and the action is performed according to the element and other elements. The expressions of multiple, multiple times, multiple varieties, etc. include 2, 2 times, 2 varieties and more than 2, more than 2 times, more than 2 varieties.

[0065] The term "coupled to" and its derivatives can be used herein. "Coupled" can mean that two or more elements are in direct physical or electrical contact. However, "coupled" can also mean that two or more elements are indirectly in contact with each other but still cooperate or interact with each other, and can mean that one or more other elements are coupled or connected between the elements referred to as being coupled to each other.

[0066] This specification includes combinations of the various embodiments described herein. References to an embodiment, or embodiments, e.g., "the embodiment" or "some embodiments" or "one embodiment" or "an exemplary embodiment", do not necessarily refer to the same embodiment; however, such embodiments are not mutually exclusive, unless otherwise indicated. It should be noted that the use of "or" herein is meant to encompass both a exclusive or and an inclusive or, unless otherwise indicated or required by the context.

[0067] All documents mentioned in this specification are hereby incorporated by reference in their entirety to provide additional description of the application. In addition, it should be noted that the language used in the specification has been principally selected for readability and instructional purposes and can not have been selected to delineate or circumscribe the patent rights of the application. Accordingly, the scope of the application is in accordance with the claims taken in their broadest interpretation.

Claims

1. A 1.5 frequency divider based on a time-delay locked loop, characterized in that, include: Besides the 1.5 frequency divider and the delay-locked loop, the delay-locked loop includes a voltage-controlled delay unit, a phase detector, a low-pass filter, and an error amplifier; wherein, The 1.5 divider outputs a frequency-divided signal with a duty cycle of 1 / 3 and a division ratio of 1.5 based on a pair of positive and negative clock signals to the phase detector and the voltage-controlled delay unit. The voltage-controlled delay unit delays the frequency-divided signal for a certain period of time before outputting it to the phase detector. The phase detector performs logical operations on the frequency division signal and the delayed frequency division signal to form a frequency division signal with a duty cycle of 1 / 2 and converts it into a pair of differential signals for output. The pair of differential signals are sequentially passed through the low-pass filter and the error amplifier and then output to the voltage-controlled delay unit; The divider-by-1.5 includes: The divider-by-3 includes a first flip-flop, a second flip-flop, and a first NAND logic. The pair of positive and negative clock signals are coupled to the first flip-flop and the second flip-flop. The output of the first flip-flop is connected to the first input of the first NAND logic, the output of the first NAND logic is connected to the input of the second flip-flop, and the output of the second flip-flop is connected to the second input of the first NAND logic and the input of the first flip-flop. A frequency multiplier, comprising a third flip-flop, a latch, a first NOR logic, a second NOR logic, and a third NOR logic, wherein a pair of positive and negative clock signals are coupled to the third flip-flop and the latch; the output of the first NOR logic is connected to the input of the latch; the output of the latch and the positive clock signal are coupled to the two inputs of the second NOR logic; the output of the second flip-flop is connected to the input of the third flip-flop; the output of the third flip-flop and the negative clock signal are coupled to the two inputs of the first NOR logic; the outputs of the first NOR logic and the second NOR logic are coupled to the two inputs of the third NOR logic; and the third NOR logic outputs a frequency divider signal with a duty cycle of 1 / 3 and a division ratio of 1.

5.

2. The 1.5 frequency divider based on a time-locked loop according to claim 1, characterized in that, The first flip-flop, the second flip-flop, and the third flip-flop are D flip-flops.

3. The 1.5 frequency divider based on a time-locked loop according to claim 1, characterized in that, The phase detector includes: a second NAND logic, a first inverter, a second inverter, and a single-ended to differential conversion unit. The frequency division signal and the delayed frequency division signal are respectively connected to the two input terminals of the second NAND logic. The output terminal of the second NAND logic is connected to the input terminal of the first inverter. The output terminal of the first inverter is connected to the input terminal of the second inverter and the input terminal of the single-ended to differential conversion unit. The second inverter and the single-ended to differential conversion unit respectively output the pair of differential signals.

4. The 1.5 frequency divider based on a time-locked loop according to claim 3, characterized in that, The phase detector further includes a third inverter and a fourth inverter. The input terminal of the third inverter and the output terminal of the fourth inverter are connected to the output terminal of the second inverter. The output terminal of the third inverter and the input terminal of the fourth inverter are connected to the output terminal of the single-ended to differential unit.

5. The 1.5 frequency divider based on a time-locked loop according to claim 1, characterized in that, The low-pass filter extracts the DC component of the pair of differential signals, and the error amplifier amplifies the difference between the DC components of the pair of differential signals and outputs a delay control signal to the voltage-controlled delay unit.

6. The 1.5 frequency divider based on a time-locked loop according to claim 5, characterized in that, The error amplifier is an automatic zeroing amplifier, a chopper amplifier, or an offset calibration amplifier.

7. The 1.5 frequency divider based on a time-locked loop according to claim 5, characterized in that, The voltage-controlled delay unit includes: first to fourth PMOS transistors and first to fourth NMOS transistors. The sources of the first to third PMOS transistors are all connected to the power supply terminal. The gate of the third PMOS transistor is connected to the power supply terminal. The gate and drain of the first PMOS transistor are connected to the gate of the second PMOS transistor and connected to the drain of the first NMOS transistor. The drains of the second and third PMOS transistors are all connected to the source of the fourth PMOS transistor. The gate of the fourth PMOS transistor and the gate of the fourth NMOS transistor are connected to the frequency division signal. The sources of the first to third NMOS transistors are all connected to the ground terminal. The gate of the third NMOS transistor is connected to the ground terminal. The gates of the first and second NMOS transistors are connected to the delay control signal. The drains of the second and third NMOS transistors are all connected to the source of the fourth NMOS transistor. The drain of the fourth PMOS transistor and the drain of the fourth NMOS transistor are connected to the input terminal of a fifth inverter. The output terminal of the fifth inverter outputs the delayed frequency division signal.

8. The 1.5 frequency divider based on a time-locked loop according to claim 7, characterized in that, The delay control signal controls the magnitude of the bias current of the voltage-controlled delay unit.

9. The 1.5 frequency divider based on a time-locked loop according to claim 1, characterized in that, The voltage-controlled delay unit delays the frequency division signal by 1 / 6 cycle.

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