Delay circuit and delay method

Abstract

A delay circuit and a delay method are provided. A phase detector is configured to receive a first clock signal and a second clock signal and generate a digital signal indicative of a relationship between a phase of the first clock signal and a phase of the second clock signal. A phase accumulator circuit is configured to receive the digital signal and generate a phase signal based on values of the digital signal over a plurality of clock cycles. A decoder is configured to receive the phase signal and generate a digital control word based on the phase signal. A delay element is configured to receive the digital control word. The delay element is further configured to change the relationship between the phase of the first clock signal and the phase of the second clock signal by modifying the phase of the second clock signal according to the digital control word.

Description

Technical Field

[0001] This disclosure relates to a delay circuit and a delay method. Background Technology

[0002] Delay-locked loop (LDL) circuits are commonly included in digital systems such as memory systems and are used to align the edges of multiple digital signals. For example, a LDL circuit can be used to align the rising and / or falling edges of a clock signal based on a reference clock signal to generate a synchronized output clock signal. Summary of the Invention

[0003] This disclosure includes a delay circuit. The delay circuit includes a phase detector, a phase accumulator circuit, a decoder, and a delay element. The phase detector is used to (i) receive a first clock signal and a second clock signal, and (ii) generate a digital signal indicating a relationship between a phase of the first clock signal and a phase of the second clock signal. The phase accumulator circuit is used to receive the digital signal and generate a phase signal based on the values ​​of the digital signal over multiple clock cycles. The decoder is used to receive the phase signal and generate a digital control word based on the phase signal. The delay element is used to receive the digital control word and change the relationship between the phases of the first clock signal and the second clock signal by modifying the phase of the second clock signal according to the digital control word. The delay element includes a coarse tuning element and a fine tuning element, the fine tuning element having a shorter programmable delay increment compared to the coarse tuning element. The decoder includes a coarse decoder element and a fine decoder element. The coarse decoder element generates a coarse control character to control a coarse tuning element, and the fine decoder element generates a fine control character to control a fine tuning element.

[0004] This disclosure includes a delay circuit. The delay circuit includes a phase detector, a digital control block, and delay elements. The phase detector is used to receive a first clock signal and a second clock signal, and to generate a digital signal indicating a relationship between a phase of the first clock signal and a phase of the second clock signal. The digital control block is used to receive the digital signal and generate a digital control word based on multiple values ​​of the digital signal over multiple clock cycles. The delay elements are used to (i) receive the digital control word and (ii) change the relationship between the phase of the first clock signal and the phase of the second clock signal by modifying the phase of the second clock signal according to the digital control word. The delay circuit further includes a delay generator. The delay generator is used to receive (i) an input periodic signal having a frequency equivalent to a desired frequency of the first clock signal and the second clock signal; and to receive (ii) a target phase periodic signal having a period equivalent to a target phase delay between the first clock signal and the second clock signal.

[0005] This disclosure includes a delay method comprising: receiving a first clock signal and a second clock signal; generating a digital signal indicating a relationship between a phase of the first clock signal and a phase of the second clock signal; generating a phase signal based on a plurality of values ​​accumulated by the digital signal over a plurality of clock cycles; generating a digital control word based on the phase signal; changing the relationship between the phase of the first clock signal and the phase of the second clock signal by modifying the phase of the second clock signal according to the digital control word; and receiving the digital control word and a reference clock at a lock detector, wherein the lock detector generates a phase lock signal after the digital control word remains below a threshold value for a predetermined number of clock cycles.

[0006] This disclosure includes a delay circuit. The delay circuit includes a phase accumulator circuit, a decoder, and delay elements. The phase accumulator circuit receives a digital signal and generates a phase signal indicating a relationship between a first clock signal and a second clock signal. The decoder receives the phase signal and generates a digital control word. The delay element receives the digital control word and changes the relationship between the first clock signal and the second clock signal, wherein the delay element includes one or more tuning elements, each of which has a unique programmable delay increment, and the decoder includes one or more decoder elements, each of which generates a control word corresponding to one of the tuning elements.

[0007] This disclosure includes a delay circuit. The delay circuit includes a digital control block, delay elements, and a delay generator. The digital control block receives a digital signal and generates a digital control word, the digital signal indicating a relationship between a first clock signal and a second clock signal. The delay element receives the digital control word and changes the relationship between the first clock signal and the second clock signal according to the digital control word. The delay generator receives an input periodic signal and a target phase periodic signal, and samples the input periodic signal at a rate inversely proportional to a period of the target phase periodic signal.

[0008] This disclosure includes a delay method comprising: generating a digital signal indicating a relationship between a first clock signal and a second clock signal; generating a phase signal based on a plurality of values ​​of the digital signal; generating a digital control word based on the phase signal; changing the relationship between the first clock signal and the second clock signal according to the digital control word; and receiving the digital control word at a lock detector, wherein the lock detector generates a phase lock signal after the digital control word remains below a threshold value for a predetermined number of clock cycles.

[0009] This disclosure includes a delay circuit. The delay circuit includes a phase detector, a phase accumulator circuit, a decoder, and a delay element. The phase detector is used to (i) receive a first clock signal and a second clock signal, and (ii) generate a digital signal indicating a relationship between the first clock signal and the second clock signal. The phase accumulator circuit is used to receive the digital signal and generate a phase signal. The decoder is used to receive the phase signal and generate a digital control word. The delay element is used to receive the digital control word and change the relationship between the first clock signal and the second clock signal. The delay element includes one or more tuning elements, each of which has a unique programmable delay increment. The decoder includes one or more decoder elements, each of which generates a control word corresponding to one of the tuning elements.

[0010] This disclosure includes a delay circuit. The delay circuit includes a phase detector, a digital control block, a delay element, and a delay generator. The phase detector receives a first clock signal and a second clock signal, and generates a digital signal indicating a relationship between the first clock signal and the second clock signal. The digital control block receives the digital signal and generates a digital control word. The delay element (i) receives the digital control word and (ii) changes the relationship between the first clock signal and the second clock signal according to the digital control word. The delay generator receives (i) an input periodic signal and (ii) a target phase periodic signal, and samples the input periodic signal at a rate inversely proportional to a period of the target phase periodic signal.

[0011] This disclosure includes a delay method comprising: receiving a first clock signal and a second clock signal; generating a digital signal indicating a relationship between the first clock signal and the second clock signal; generating a phase signal based on a plurality of values ​​of the digital signal; generating a digital control word based on the phase signal; changing the relationship between the first clock signal and the second clock signal according to the digital control word; and receiving the digital control word at a lock detector, wherein the lock detector generates a phase lock signal after the digital control word remains below a threshold value for a predetermined number of clock cycles. Attached Figure Description

[0012] The state of this disclosure is in relation to the accompanying documents. Figure 1 The best way to understand this text is by referring to the following detailed description. It should be noted that, according to industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features can be arbitrarily increased or decreased for clarity of explanation.

[0013] Figure 1 A block diagram of a delay lock loop (DLL) circuit according to some embodiments;

[0014] Figure 2 A block diagram illustrating the signals exchanged between the phase circuit and the decoder according to some embodiments;

[0015] Figure 3 A block diagram depicting details of the decoder according to some embodiments;

[0016] Figure 4 A block diagram depicting details of a delay element according to some embodiments;

[0017] Figure 5A A schematic diagram illustrating an example implementation of a DLL circuit according to some embodiments;

[0018] Figure 5B A timing diagram of the signal used by the target delay generator according to some embodiments;

[0019] Figure 5C A schematic diagram illustrating an example implementation of a timing element circuit according to some embodiments;

[0020] Figure 6 Details of a decoder having fine tuning and coarse tuning sections according to some embodiments are depicted;

[0021] Figure 7A and Figure 7B Details of a lock detector according to some embodiments are depicted;

[0022] Figure 8 Timing diagrams depicting DLL circuits implemented according to some embodiments of this disclosure;

[0023] Figure 9 Depicts the use of a clock tree for shifting the phase of a gate clock according to some embodiments;

[0024] Figure 10 Describes the operation of instance methods according to some embodiments.

[0025] Corresponding numbers and symbols in the various figures generally refer to corresponding parts, unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.

[0026] [Symbol Explanation]

[0027] 100: Phase circuit

[0028] 101: Phase signal

[0029] 102: Digital Control Character

[0030] 103: Second clock signal / Second control signal

[0031] 104: Digital Signal

[0032] 105: First clock signal

[0033] 110: Decoder

[0034] 120: Delay element

[0035] 130: Phase detector

[0036] 200: Phase Circuit

[0037] 201: Phase signal

[0038] 203: Reset accumulator signal

[0039] 204: Mode switching signal

[0040] 205: Clock Signal

[0041] 206: Digital Signals

[0042] 207: Clock Signal

[0043] 210: Pulse Generator

[0044] 220: Mode switching element

[0045] 230: Decoder

[0046] 240: Phase detector

[0047] 300: Phase circuit

[0048] 301: Phase signal

[0049] 302: Mode switching signal

[0050] 303: Reset accumulator signal

[0051] 304: Fine-grained delay control character

[0052] 305: Coarse Delay Control Character

[0053] 310: Pulse Generator

[0054] 315: Mode switching element

[0055] 320: Decoder

[0056] 321: Fine Decoder Section

[0057] 322: Coarse Decoder Section

[0058] 323: Coarse Mover

[0059] 330: Delay element

[0060] 400: Decoder

[0061] 401: Fine Decoder Section

[0062] 402: Coarse Decoder Section

[0063] 403: Coarse Mover

[0064] 404: Fine-grained delay control character

[0065] 405: Coarse Delay Control Character

[0066] 406: Signal

[0067] 407: Second clock signal

[0068] 408: Phase Comparison Signal

[0069] 409: First clock signal / Input periodic signal

[0070] 410: Delay element

[0071] 411: Fine-tuning section

[0072] 412: Coarse Tuning Section

[0073] 413: Target Delay Signal

[0074] 420: Target Delay Generator

[0075] 430: Phase detector

[0076] 502: Delay value signal

[0077] 503: Digital Low-Pass Filter

[0078] 504: Decoder

[0079] 505: Fine One-Element Converter

[0080] 506: Control Character

[0081] 507: Lock-on Detector

[0082] 508: Phase Circuit

[0083] 508a: Type D flip-flop

[0084] 508b: Multiplexer

[0085] 508c: Binary adder element

[0086] 508d: Type D flip-flop

[0087] 508e: Logic AND gate

[0088] 510: Mode switching signal

[0089] 511: Coarse Tuning

[0090] 512: Lock onto detection signal

[0091] 513: Phase Shift Signal

[0092] 514: Pulse Generator

[0093] 515: Mode Switching Circuit

[0094] 516: Coarse Mover

[0095] 517: Rough One-Element Converter

[0096] 518: Input periodic signal

[0097] 519: First Type D flip-flop

[0098] 520: Second Type D Flip-Flipper

[0099] 522: Phase Detector

[0100] 523: Output signal / periodic signal

[0101] 524: Unary fine-grained delay control character

[0102] 525: Target Delay Signal

[0103] 527: Unary coarse delay control character / thermometer code

[0104] 529: Coarse Tuning Section / Coarse Tuning Block

[0105] 530: Pre-delayed signal

[0106] 531: Phase Comparison Signal

[0107] 535: Fine tuning section / Fine tuning block

[0108] 536: Delay element

[0109] 537: Target Delay Generator

[0110] 538: Pre-delayed periodic signal

[0111] 540: Delay element

[0112] 541: Coarse Tuning Section

[0113] 542: Fine-tuning section

[0114] 543: Unit

[0115] 544: Transmission Gate

[0116] 545: Schematic diagram

[0117] 546: Input periodic signal

[0118] 547: Enable pin

[0119] 548: Thermometer code coarse tuning character

[0120] 549: Unit

[0121] 550: Chart

[0122] 551: Unit

[0123] 552: Array of unit cells for three-state inverters

[0124] 553: Thermometer code fine-tuning character

[0125] 600: Decoder

[0126] 610: Fine tuning section

[0127] 620: Coarse Tuning Section

[0128] 700: Lock-on Detector

[0129] 704: Comparison Results

[0130] 705: Value

[0131] 706: Signal

[0132] 707: Periodic Input Signal

[0133] 740: Flipper

[0134] 1220: Remote delay string

[0135] 1230: Clock Tree

[0136] 1000: Method

[0137] 1002: Operation

[0138] 1004: Operation

[0139] 1006: Operation

[0140] 1008: Operation

[0141] 1010: Operation Detailed Implementation

[0142] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, references to numbers and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0143] Additionally, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and similar terms may be used herein for ease of description to describe the relationship between one element or feature as illustrated in the figures and another element or feature(s). Spatial relative terms are intended to cover different orientations of the device in its use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0144] Some embodiments of this disclosure are described. Additional operations may be provided before, during, and / or after the stages described in these embodiments. Some of the stages described may be replaced or eliminated in different embodiments. Additional features may be added to the semiconductor device. Some of the features described below may be replaced or eliminated in different embodiments. Although some embodiments are discussed with reference to operations performed in a particular order, these operations may be performed in another logical order.

[0145] Delay-locked loop (DLL) circuits are used in digital systems to align the edges of multiple digital signals. A DLL circuit can be used, for example, to align the rising and / or falling edges of a clock signal based on a reference clock signal to generate a synchronized output clock signal. Known DLL circuits are implemented via analog circuitry and typically include a phase detector, charge pump, filter, and delay series. Such known DLL circuits have the disadvantage of being susceptible to unwanted delays introduced between the reference and output clock signals. Unwanted delays can be inherent characteristics of analog circuitry, including the result of current mismatches caused by environmental factors (e.g., exposure to high temperatures). These delays can become particularly significant at higher frequencies (e.g., 7 GHz or higher) and when using smaller feature sizes (e.g., 5 nm feature sizes).

[0146] The disclosed method provides DLL circuits and methods for operating DLL circuits that eliminate or mitigate unwanted delays and other defects of known DLL circuits. In some embodiments, the disclosed method achieves these advantages by using digital technology to control the DLL circuit. The digitally controlled DLL circuit of the disclosed method is less susceptible to errors introduced into the output and distortion caused by the target phase delay between the reference clock signal and the output clock signal. Therefore, compared to known analog DLL methods, the disclosed method provides higher accuracy, predictability, resilience, and reliability. Furthermore, the use of digitally controlled DLLs to mitigate errors enables their use in high-frequency applications and in embodiments with small feature sizes.

[0147] Figure 1This is a block diagram of a DLL circuit according to some embodiments. As shown in this figure, the DLL circuit includes a phase detector 130 that receives a first clock signal 105 and a second clock signal 103. Based on the received clock signals, the phase detector 130 generates a digital signal 104 indicating the relationship between the phase of the first clock signal 105 and the phase of the second clock signal 103. The phase detector 130 is used to compare the first clock signal 105 and the second clock signal 103 to determine the relative phase difference between the two signals. In some embodiments, the first clock signal 105 is a reference clock signal received by the DLL circuit, and the second clock signal 103 is an output clock signal generated by the DLL circuit. Figure 1 The DLL circuit can be used to align the edges of the second clock signal 103 (e.g., rising and / or falling edges) with the edges of the first clock signal 105 to generate a synchronized output clock signal.

[0148] The digital signal 104 generated by the phase detector 130 is received by the phase circuit 100. In some embodiments, the phase circuit 100 is a phase accumulator circuit that generates a phase signal 101 based on the received digital signal 104. In such embodiments, the phase circuit 100 is used to accumulate the values ​​of the digital signal 104 over multiple cycles to calculate the total phase shift delay required to align the phase of the first clock signal 105 with the phase of the second clock signal 103. This information is output as the phase signal 101 by the phase circuit 100.

[0149] In some embodiments, the digital signal 104 received by the phase circuit 100 includes digital values ​​(e.g., logic level high values ​​of "1" and logic level low values ​​of "0") that indicate whether the second clock signal 103 lags behind or leads the first clock signal 105. For example, in some embodiments, a digital signal 104 with a value of "1" indicates that the second clock signal 103 lags behind the first clock signal 105, and a digital signal 104 with a value of "0" indicates that the second clock signal 103 leads the first clock signal 105, or vice versa.

[0150] In some embodiments, the phase circuit 100 increases the value of the phase signal 101 based on the digital signal 104 having a first value (e.g., a logic level high of "1"), and decreases the value of the phase signal 101 based on the digital signal 104 having a second value (e.g., a logic level low of "0"). The phase signal 101 generated by the phase circuit 100 is received by a decoder 110, which generates a digital control character 102 based on the phase signal 101. In some embodiments, the decoder 110 performs one or more decoding functions to decode the phase signal 101, thereby generating the digital control character 102.

[0151] The delay element 120 receives the digital control character 102 from the decoder 110. In some embodiments, the delay element 120 is used to change the relationship between the phase of the first clock signal 105 and the phase of the second clock signal 103 by modifying the phase of the second clock signal 103 according to the digital control character 102. The phase-shifted signal is then output as a second control signal 103 through the delay element 120, and the second control signal 103 is fed back to the phase detector 130 as a feedback signal to repeat the above procedure.

[0152] See the following text. Figures 2 to 10 To further explain, the embodiments of this disclosure utilize a method of combining digital and analog circuits to improve known analog DLL circuits. In some embodiments, the digital circuitry includes a phase circuit 100 and a decoder 110, which together constitute part of the digital core of the DLL circuit. The digital signals used in the method according to this disclosure include the aforementioned digital signal 104 generated by the phase detector 130 and digital control characters 102 generated by the decoder 110. The use of such digital components and digital signals provides improvements over known DLL circuits, which are primarily based on analog technology. Such improvements are described throughout this disclosure. The structure and functionality of the components constituting the digital core are described in further detail below.

[0153] Along with the digital core, the DLL circuit disclosed herein includes analog components that interact with the digital components. These analog components include delay elements 120 and phase detectors 130, which together constitute a portion of the analog core of the DLL circuit. The structure and functionality of the components constituting the analog core are described in further detail below. The combination of analog and digital components described herein is used to provide DLL circuits and methods for operating DLL circuits that advantageously eliminate unnecessary delays and errors in known analog DLL circuits.

[0154] Figure 2 This is a block diagram depicting the signals exchanged between phase circuit 200 and decoder 230 according to some embodiments. Phase circuit 200, decoder 230, and phase detector 240 are provided respectively with respect to the above-described... Figure 1 The functionality of the phase circuit 100, decoder 110, and phase detector 130 is described herein. As described herein, some embodiments of this disclosure include delay elements (e.g., providing delay based on both fine-tuning and coarse-tuning modes). Figure 1 Delay element 120, Figure 4 (e.g., delay element 410). In some embodiments, fine-tuning mode and coarse-tuning mode are achieved using unique delay control characters generated by different parts of decoder 230. Figure 2Describe the state of the control mechanism used to select and switch between fine tuning mode and coarse tuning mode.

[0155] More specifically, in some embodiments, after the phase difference to be achieved has a precision unattainable by the coarse tuning mode of the delay element, a switch between the coarse tuning mode and the fine tuning mode occurs automatically. This event is detected by a phase detector 240, which outputs a digital signal 206 having a first logic value (e.g., a logic level high value of "1") that indicates the need for additional phase shift to be applied to the second clock signal 207. The digital signal 206 and the second clock signal 207 correspond respectively to the information described above regarding... Figure 1 The described digital signal 104 and second clock signal 103. Phase detector 240 outputs a digital signal 206 with a first logic value until the phase of the second clock signal 207 has been delayed and shifted beyond a target phase, thereby indicating that the phases of the first clock signal 205 and the second clock signal 207 are aligned to a degree less than the delay amount that can be provided by the coarse tuning mode of the delay element. Here, phase detector 240 generates a digital signal 206 with a second logic value (e.g., a low logic level of "0"), which indicates the need to switch to a fine tuning mode to further align the phases of clock signals 205 and 207.

[0156] Phase circuit 200 receives digital signal 206 from phase detector 240 and generates phase signal 201 based on the received signal 206. Phase signal 201 corresponds to... Figure 1 The phase signal 101 provides the same or similar functionality as described above for the phase signal 101. In some embodiments, the phase circuit 200 is configured to increase the numerical output of the phase signal 201 by one bit for each clock cycle, in which the phase circuit receives a digital signal 206 having a first logic value (e.g., a logic level high value of "1"), thus increasing the total delay to be applied to the second clock signal 207.

[0157] When the phase circuit 200 receives a digital signal 206 having a second logic value (e.g., a logic level low of "0"), this indicates that the phase of the second clock signal 207 is delayed beyond the target phase in the previous cycle. Based on this input, the phase circuit 200 reduces the numerical output of the phase signal 201 by one bit, causing the delay element (e.g., Figure 1 Delay element 120, Figure 4 The coarse tuning mode of the delay element 410 (etc.) delays the clock signal 207 so that the phase of the clock signal is aligned as closely as possible with the target phase allowed by the coarse tuning mode without causing the clock signal 207 to lag behind the target phase.

[0158] In some embodiments, mode switching element 220 is used to receive phase signal 201. After detecting a decrease in the value of phase signal 201, mode switching element 220 changes the value of mode switching signal 204 from a first logic level value (e.g., "0") to a second logic level value (e.g., "1"). Decoder 230 is used to receive phase signal 201 and mode switching signal 204. When mode switching signal 204 changes from the first logic level value to the second logic level value, decoder 230 freezes the current value of phase signal 201 and activates fine decoding mode.

[0159] In some embodiments, pulse generator 210 is also used to receive mode switching signal 204. Upon receiving mode switching signal 204 having a second logic level value (e.g., "1"), pulse generator 210 outputs a reset pulse on reset accumulator signal 203, which is received by phase circuit 200. Upon receiving reset accumulator signal 203, phase circuit 200 is reset, resetting phase signal 201 to an initial value (e.g., zero). This reset of phase signal 201 allows it to be used to calculate the phase delay to be applied in the fine-tuning mode of the delay element.

[0160] Figure 3 A block diagram depicting additional details of decoder 320 according to some embodiments. Figure 3 The phase circuit 300, pulse generator 310, mode switching element 315, decoder 320, and delay element 330 provide the above-mentioned... Figure 1 and Figure 2 The corresponding component describes some or all of the functionality. Similarly, Figure 3 The phase signal 301, mode switching signal 302, and reset accumulator signal 303 are similar to those described above. Figure 1 and Figure 2 The corresponding signal is described in the way it is used.

[0161] In some embodiments, the decoder 320 includes a fine decoder portion 321 and a coarse decoder portion 322. For example... Figure 2Generally, decoder 320 receives phase signal 301 and mode switching signal 302, which can be initialized to a first value (e.g., "0"). When mode switching signal 302 has the first value, coarse decoder section 322 is activated, and fine decoder section 321 is deactivated. Upon activation, coarse decoder section 322 receives phase signal 301 and converts phase signal 301 from a binary value to a corresponding unary coarse delay control word 305 to control the amount of delay applied by delay element 330. In some embodiments, coarse delay control word 305 is a 32-bit unary number initialized to the first value (e.g., "0"). Before conversion to unary number, a binary number equivalent to phase signal 301 is fed in via coarse shifter 323, which continuously outputs the previous non-zero binary number received by coarse shifter 323. In some embodiments, the coarse mover 323 is incorporated into the decoder 320 to be protected from changes in temperature and voltage.

[0162] In some embodiments, when the mode switching signal 302 changes from a first value (e.g., "0") to a second value (e.g., "1"), the decoder 320 receives this second value. Based on the received second value, the decoder 320 locks the coarse decoder section 322 and activates the fine decoder section 321. Locking the coarse decoder section 322 prevents the phase signal 301 from entering the coarse decoder section 322, thereby causing a specific value (e.g., "0") to propagate to the input of the coarse mover 323. The coarse mover 323 continues to output the received binary number equivalent to the phase signal 301, causing the coarse tuning section of the delay element 330 to continue applying the same delay amount. When the fine decoder section 321 of the decoder 320 is activated, the fine decoder section 321 receives the phase signal 301 as input and outputs a fine delay control word 304. In some embodiments, the fine delay control word 304 corresponds to the unary value of the phase signal 301 plus the initial value of the phase signal 301, which is equivalent to half of the maximum delay output of the fine tuning portion of the delay element 330. In some embodiments, the fine delay control word 304 is a 32-bit unary number.

[0163] Figure 4 A block diagram depicting details of delay element 410 according to some embodiments. Figure 4 The decoder 400, fine decoder section 401, coarse decoder section 402, coarse mover 403, delay element 410, and phase detector 430 provide the above-mentioned... Figures 1 to 3 The corresponding component describes some or all of the functionality. Similarly, Figure 4 The fine delay control character 404, the coarse delay control character 405, and the second clock signal 407 are similar to those described above. Figures 1 to 3 The corresponding signal is described in the way it is used.

[0164] In some embodiments, delay element 410 is configured to receive unary inputs of coarse delay control word 405 and fine delay control word 404, as well as a pre-shifted periodic signal 406. The unary coarse delay control word 405 is received via a coarse tuning portion 412 of delay element 410, whereby delay element 410 activates several coarse delay elements in coarse tuning portion 412 corresponding to the unary coarse delay control word 405. Similarly, the unary fine delay control word 404 is received via a fine tuning portion 411 of delay element 410, whereby delay element 410 activates several fine delay elements in fine tuning portion 411 corresponding to the unary fine delay control word 404. The delay element 410 then delays the pre-delayed periodic signal 406 by passing the pre-delayed periodic signal through several activated delay units of both the coarse tuning section 412 and the fine tuning section 411, and outputting a phase-delayed version of the pre-shifted periodic signal 406 as a second clock signal 407.

[0165] like Figure 4 As illustrated, the target delay generator 420 is used to receive the first clock signal 409 and the target delay signal 413. The first clock signal 409 corresponds to the one described above. Figures 1 to 3 The first clock signal described is (e.g., first clock signal 105, first clock signal 205). In some embodiments, the target delay signal 413 is a periodic signal having a period size corresponding to the desired phase shift to be applied to the first clock signal 409. In some embodiments, the target delay generator 420 samples the first clock signal 409 at a rate equal to the reciprocal of the length of the desired phase delay.

[0166] In some embodiments where the target delay signal 413 is a periodic signal with a period size corresponding to a desired phase shift to be applied to a signal having the same frequency as the first clock signal 409, this is achieved by sampling the input periodic signal 409 using the frequency of the target delay signal 413. This results in the target delay generator 420 outputting a pre-delayed periodic signal 406 with a resolution of the desired phase delay length, and the period of the pre-delayed periodic signal 406 being an integer multiple of the desired phase delay. The target delay generator 420 also outputs a phase comparison signal 408. In some embodiments, the phase comparison signal 408 is generated by passing a sampled periodic signal equivalent to the pre-delayed signal 406 through an additional D-type flip-flop, wherein the clock (CLK) of the D-type flip-flop is driven by the same periodic signal used to sample the input periodic signal 409 to generate the pre-delayed periodic signal 406. This results in the phase comparison signal 408 also having the desired phase delay resolution and a period equal to an integer multiple of the desired phase delay. However, because the phase comparison signal 408 has passed through an additional D-type flip-flop, the phase comparison signal 408 has a phase that lags behind the pre-delay periodic signal 406 by exactly one target phase delay length.

[0167] Phase detector 430 receives phase comparison signal 408 and second clock signal 407. After the second clock signal 407 is delayed by the delay element 410 for a programmed amount of time, the second clock signal 407 is equivalent to the pre-delayed periodic signal 406. Phase detector 430 then compares these two signals to determine whether the delay applied by delay element 410 should be increased or decreased to align the phases of phase comparison signal 408 and second clock signal 407. Because the phase of phase comparison signal 408 lags behind the exact target delay length of the pre-delayed periodic signal 406, the delay applied to the pre-delayed periodic signal 406 by delay element 410 must be equal to the target delay. Delay element 410 aligns the phase of pre-delayed periodic signal 406 with the phase of phase comparison signal 408.

[0168] Figure 5A This is a schematic diagram illustrating an example implementation of a DLL circuit according to some embodiments. In some embodiments, Figure 5A The DLL circuit is used to generate a phase delay, thereby delaying the input periodic signal 518 by the target delay amount indicated by the period length of the target delay signal 525. Figure 5AIn this circuit, a target delay generator 537 receives an input periodic signal 518 and a target delay signal 525. The input periodic signal 518 and the target delay signal 525 have a period length equal to the desired phase shift to be applied to the periodic signal, and the periodic signal has a frequency equal to the frequency of the input periodic signal 518. The target delay generator 537 first samples the input periodic signal 518 through a first D-type flip-flop (DF) 519 at the frequency of the target delay signal 525. The first D-type flip-flop 519 receives the target delay signal 525 as its clock value.

[0169] The first D-type flip-flop 519 outputs a pre-delayed signal 530, which is equivalent to the input periodic signal 518 expressed in terms of the target phase delay magnitude, wherein the period of the pre-delayed signal 530 is an integer multiple of the full number of the target phase delay. The second D-type flip-flop 520 accepts the pre-delayed signal 530 as input and the target delay signal 525 as its clock. The second D-type flip-flop 520 generates a phase comparison signal 531 as its output. The target delay generator 537 outputs the pre-delayed signal 530 to be received as input to the delay element 536 and outputs the phase comparison signal 531 to be received as input to the phase detector 522. Figure 5B A timing diagram of the signals used by the target delay generator 537 according to some embodiments.

[0170] See again Figure 5AIn some embodiments, the phase detector 522 includes a single D-type flip-flop that accepts the output signal 523 as its input and a phase comparison signal 531 as its clock (CLK). The phase comparison signal 531 is equivalent to the pre-delayed signal 538, but is phase-shifted precisely backward by a target delay after the pre-delayed signal 538 by a second D-type flip-flop 520. The output signal 523 is equivalent to the pre-delayed signal plus a delay applied to the output signal 523 via a delay element 536. The delay applied to the output periodic signal 523 via the delay element 536 is modified to make the phase magnitude of the output periodic signal 523 equivalent to the target delay. Therefore, in some embodiments, the D-type flip-flop including phase detector 522 outputs a logic 1 signal to phase shift signal 513, while the phase of phase comparison signal 531 lags behind the phase of output periodic signal 523, thereby indicating that the delay applied by delay element 536 needs to be increased by an amount to match the target delay. Conversely, if the phase of output periodic signal 523 lags behind phase comparison signal 531, the D-type flip-flop including phase detector 522 outputs a logic 0 to phase shift signal 513, thereby indicating that the delay applied by delay element 536 needs to be reduced by an amount to match the target delay.

[0171] Phase circuit 508 acts as a phase accumulator by receiving a phase shift signal 513 as input once per clock cycle, the clock being synchronized to the input periodic signal 518. The value of phase shift signal 513 is read once per clock cycle by receiving phase shift signal 513 as input to D-type flip-flop 508a, where the clock is synchronized to the input periodic signal 518. The output of D-type flip-flop 508a acts as a control bit for multiplexer 508b, which outputs a binary value of 1 when its control bit is 1 and a binary value of -1 when the control bit is 0. This binary value is received by binary adder element 508c, which also receives a delay value signal 502 as input once per clock cycle by sending its output through D-type flip-flop 508d, where the clock is synchronized to the input periodic signal 518 before returning to receive the delay value signal 502 as input. The accumulated value of the delay signal 502 is output through the phase circuit 508, indicating the amount of phase delay to be applied by the phase delay element 536.

[0172] In some embodiments, the delay magnitude signal is transmitted through a digital low-pass filter 503 to reduce noise in the signal before being transmitted to the decoder 504. The decoder 504 accepts the delay magnitude signal 502 as input and converts it into a unary control word to control the amount of delay applied via the delay element 536. In some embodiments of the circuit, the delay element 536 includes multiple functional modes, such as a coarse tuning section 529 and a fine tuning section 535, and the decoder 504 has multiple operating modes for the purpose of performing coarse delay changes or fine tuning delay adjustments applied to the output periodic signal 523 via the delay element 536. In some embodiments, the decoder is used to receive a mode switching signal 510 as output. When the mode switching signal 510 is set to an initial value of logic 0, the decoder operates in coarse mode. In this case, the delay value signal is ultimately converted into a coarse delay control word 527 by the coarse unary converter 517, thereby controlling the amount of coarse delay applied to the output periodic signal 523 through the coarse tuning section 529 of the delay element 536. Before reaching the coarse unary converter 517, a coarse mover 516 is implemented. In the coarse mode, this ensures the continuity of the control signal sent to the coarse tuning section 529 of the delay element 536 by having the decoder 504 continuously output the previous non-zero value for coarse tuning 511.

[0173] In some embodiments, the mode switching circuit 515 receives the delay value signal 502 and, after receiving a decrease in the value of the delay value signal 502, outputs a logic 1 signal to the mode switching signal 510, which is initially initialized to logic 0. The pulse generator 514 receives the mode switching signal 510 and outputs a phase accumulator reset signal 509. The phase accumulator reset signal 509 is combined with the binary adder element 508c via a logic AND gate 508e before reaching the D-type flip-flop 508d. The phase accumulator reset signal 509 resets the value of the delay value signal 502 to 0 to begin accumulating the delay value to be applied to the output signal 523 via the fine-tuning portion 535 of the delay element 536.

[0174] After the mode switching signal 510 receives a logic 1 signal as input, the decoder 504 switches from the coarse switching mode to the fine tuning mode. The unary coarse control word 527 is locked to its current value, so that the implemented coarse delay continues during and after the fine tuning delay adjustment. The decoder 504 outputs the delay amount signal to the fine unary converter 505, which outputs the unary fine delay control word 524 to control the amount of delay applied to the output periodic signal 523 through the fine tuning portion 535 of the delay element 536.

[0175] In some embodiments, the lock detector 507 is configured to receive a binary delay control word 506 and a periodic input signal equivalent to an input periodic signal 518 via a decoder 504. In some embodiments, the control word 506 corresponds to a finely tuned delay control word. The lock detector 507 receives the control word 506 once per clock cycle and compares the control word 506 with a set threshold value. If the control word 506 has not exceeded the threshold value for a predetermined number of cycles, the control word 506 outputs a logic 1 signal on the lock detection signal 512, which has been previously initialized to logic 0.

[0176] Delay element 536 is used to receive a pre-delayed periodic signal 538 as input. In some embodiments, delay element 536 includes a coarse tuning portion 529 and a fine tuning portion 535. The coarse tuning portion 529 receives a unary coarse delay control word 527 that controls the amount of coarse delay increment applied through delay element 536. The fine tuning portion 535 receives a unary fine delay control word 524, inverting half of the most significant bits to shift the initial preset delay by 50% of the total fine tuning delay capacity to allow shifting in both directions if necessary. The pre-delayed periodic signal 538 is then fed through all delay elements that are activated by receiving a portion of the received unary control code (a logic 1 bit) and output a periodic signal 523, which receive portions of the unary control code from both the coarse and fine tuning portions of delay element 536.

[0177] In some embodiments, delay element 536 has a unit cell structure to reduce the delay variation between coarse tuning block 529 and fine tuning block 535, and also to reduce circuit complexity. In some embodiments, the unit cell structure of delay element 536 is implemented using a three-state inverter with a controlled pin (EN). Figure 5A In one example, coarse tuning block 529 is a 32-level delay string controlled by thermometer code 527. Each level of the coarse tuning block can be implemented with two unit cells and a transmission gate. In some embodiments, fine tuning block 535 is implemented using a phase interpolator with a delay range of eight unit cells. In some embodiments, fine tuning block includes thirty-two (32) steps to produce finer resolution.

[0178] Figure 5CA delay element 540 according to some embodiments is depicted. In some embodiments, the delay element 540 has a coarse tuning portion 541 and a fine tuning portion 542. Both portions of the delay element 540 are configured with a unit cell structure. An example coarse unit cell is depicted by a coarse unit cell 543. The coarse unit cell 543 is implemented using two three-state inverter unit cells 549 and a transmission gate 544. An example transistor level schematic diagram 545 of the three-state inverter unit cell 549 is illustrated by schematic diagram 545. Figure 5C In this example, the coarse tuning section 541 is a 32-level delay string controlled by the thermometer code coarse tuning character 548. Each level of the coarse tuning block can be implemented as a coarse unit 543.

[0179] Each unit has a delayed input periodic signal 546 and an enable pin 547. The enable pin 547 is electrically coupled to a single bit of the thermometer code coarse unit 543. Each unit 543 has the following two characteristics: the three-state inverter unit receives the same bit from the thermometer code coarse tuning word 548, and each unit 543 receives a different bit from the thermometer code coarse tuning word 548 as the enable signal for the enable pin 547 compared to other units. In this way, the thermometer code coarse tuning word 548 controls the number of coarse unit 543 activated by receiving a logic 1 input to the enable pin 547, or disconnects several unit 543 by setting the enable pin to logic low, thereby causing unit 549 to have high impedance and disconnect the delay section from the coarse tuning section 541.

[0180] The fine-tuning section 542 is implemented in units containing a phase interpolator, which in some embodiments has a delay range of eight (8) bit units 551 and thirty-two (32) steps for fine resolution. As depicted in Table 550, each of the eight (8) units implements four steps for fine resolution. This fine resolution is achieved by an array 552 of three-state inverter units, each of which turns the delay steps on or off according to a thermometer code fine-tuning word 553, which the three-state inverter units receive on an enable pin 547 in the same manner as in the case of the coarse-tuning section 541.

[0181] Figure 6Details of a decoder 600 having a fine-tuning section 610 and a coarse-tuning section 620 according to some embodiments are depicted. As described herein, the decoder 600 converts phase information of a digital filter into operational tuning characters used by delay elements. The fine-tuning characters generated by the fine-tuning section 610 are fixed at an intermediate value when the coarse-tuning section 620 is activated. Similarly, the coarse-tuning characters generated by the coarse-tuning section 620 are fixed at a value when the fine-tuning section 610 is activated.

[0182] like Figure 6 As illustrated, an embodiment of decoder 600 includes an overflow / underbite detector (labeled "OV_UD detector") embedded in both fine tuning section 610 and coarse tuning section 620. When an overflow / underbite of either the coarse or fine tuning character is triggered, the tuning characters of both fine tuning section 610 and coarse tuning section 620 are locked to previous values. In addition to the overflow / underbite detector, embodiments of fine tuning section 610 and coarse tuning section 620 also include logic components and a coarse mover for providing fine and coarse decoding of the received PHE and TPK signals. These components and the coarse mover are described in further detail in U.S. Patent Application No. 10,439,794, which is incorporated herein by reference in its entirety.

[0183] Figure 7A and Figure 7B Details of a lock detector 700 according to some embodiments are described below. As described above, the lock detector 700 is configured to receive a binary delayed control word output from a decoder and a periodic input signal 707 equivalent to a periodic input signal. The lock detector 700 receives the control word once per clock cycle and compares the control word with a set threshold value. If the control word does not exceed the threshold value for a predetermined number of cycles, the lock detector 700 outputs a logic 1 signal on the lock detection signal, which was previously initialized to logic 0.

[0184] In addition, such as Figure 7A and Figure 7B As illustrated, the lock detector 700 samples the fine-tuning character (fine_bin) every 256 reference clock cycles after the signal TRK goes high. The lock detector 700 compares the difference in fine_bin to check if the difference is within ±7 codes. If the comparison result 704 is within this criterion, the 3-bit counter is triggered to increment the value 705. The LD signal 706 output by the flip-flop 740 goes high until the 3-bit counter reaches 3, indicating that the DLL circuit is locked. In some embodiments, the total wait time is 768 reference cycles, such as... Figure 7B shown in.

[0185] Figure 8 Timing diagrams of DLL circuits implemented according to some embodiments of this disclosure are depicted. As illustrated in the figures, when the DLL circuit is in its initial state, the coarse tuning word and the fine tuning word are at intermediate values ​​of 0 and 16, respectively. The clock of D-type flip-flop 1 (e.g., DF1) is the input clock, and the clock of D-type flip-flop 2 (e.g., DF2) is the delay clock. Initially, the coarse tuning word increases to follow the target delay, and the fine tuning word is locked at an intermediate value. The switch from coarse to fine tuning is determined by a SWOVER block, as determined herein. The SWOVER block is described in further detail in U.S. Patent Application No. 10,644,869, which is incorporated herein by reference in its entirety.

[0186] The method disclosed herein can be used in clock trees to shift the phase of a gated clock (e.g., a sampling clock) to the center of the data. Figure 9 An example of this scenario is illustrated. The delay string at the top of the analog circuit is controlled by a digital signal, and therefore this block can be replicated as a remote delay string 1220 and embedded within the chip's clock tree. The advantage of this architecture is that the remote delay string 1220 has a compact size and can be applied to multiple clock trees 1230. More generally, the method disclosed herein can be used to replace known analog DLL circuits and thereby remove variations attributable to current and device mismatch, as described above.

[0187] Figure 10 The operation of an example method 1000 according to some embodiments is described. For ease of understanding... Figure 10 Please refer to the above. Figure 1 To describe. But Figure 10 The procedure is also applicable to other circuits. At operation 1002, a first clock signal and a second clock signal (e.g., first clock signal 105, second clock signal 103) are received. At operation 1004, a digital signal (e.g., digital signal 104) is generated, indicating the relationship between the phases of the first clock signal and the second clock signal. Figure 1 In this example, the first clock signal and the second clock signal are received by the phase detector 130, and the phase detector 130 generates a digital signal. At operation 1006, a phase signal (e.g., phase signal 101) is generated based on the accumulated value of the digital signal over multiple clock cycles. Figure 1 In this example, the phase signal is generated by phase circuit 100, which can be implemented using phase accumulator circuitry. At operation 1008, digital control characters (e.g., digital control character 102) are generated based on the phase signal. Figure 1In this example, the digital control characters are generated by decoder 110. At operation 1010, the relationship between the phases of the first and second clock signals is changed by modifying the phase of the second clock signal according to the digital control characters. Figure 1 In this instance, the relationship is changed by delay element 120.

[0188] This disclosure relates to a digital delay-locked circuit and a method for operating the digital delay-locked circuit. An example delay circuit includes a phase detector for (i) receiving a first clock signal and a second clock signal, and (ii) generating a digital signal indicating a relationship between a phase of the first clock signal and a phase of the second clock signal. A phase accumulator circuit receives the digital signal and generates a phase signal based on the values ​​of the digital signal over a plurality of clock cycles. A decoder receives the phase signal and generates a digital control word based on the phase signal. A delay element receives the digital control word and changes the relationship between the phases of the first clock signal and the second clock signal by modifying the phase of the second clock signal according to the digital control word. In some embodiments, the delay element includes a coarse-tuning element and a fine-tuning element, the fine-tuning element having a shorter programmable delay increment compared to the coarse-tuning element. In some embodiments, the decoder includes a coarse decoder element and a fine decoder element, the coarse decoder element generating a coarse control word to control a coarse tuning element, and the fine decoder element generating a fine control word to control a fine tuning element. In some embodiments, the circuit further includes a switching mode element. The switching mode element is configured to receive a phase signal and to switch from modifying a delay amount applied by the coarse tuning element to modifying a delay amount applied by the fine tuning element after the phase signal indicates that a difference between the phase of a first clock signal and the phase of a second clock signal is less than a delay change amount that can be applied by the coarse tuning element. In some embodiments, the circuit further includes a delay generator. The delay generator is configured to receive (i) an input periodic signal having a frequency equivalent to a desired frequency of the first clock signal and the second clock signal; and to receive (ii) a target phase periodic signal having a period equivalent to a target phase delay between the first clock signal and the second clock signal. In some embodiments, the delay generator is further configured to generate (i) a pre-shifted periodic signal, which is an input periodic signal sampled from a target phase periodic signal; and to generate (ii) a phase comparison signal, which is a pre-shifted periodic signal sampled from a target phase periodic signal. In some embodiments, the circuit further includes a delay generator. The delay generator is configured to receive a first clock signal and a target delay signal representing a target phase delay change of the first clock signal, and the delay generator is configured to generate a second clock signal by sampling the first clock signal at a frequency inversely proportional to the target phase delay change. In some embodiments, the target delay signal is a periodic signal having a period, the period indicating the target phase delay change. In some embodiments, the circuit further includes a lock-on detector.The lock detector is used to (i) receive a digital delay control word and a reference clock, and (ii) generate a phase-locked signal after the digital delay control word has remained below a threshold value for a predetermined number of clock cycles. In some embodiments, a phase accumulator circuit is used to accumulate the value of the digital signal in the clock cycle.

[0189] Another example circuit includes a phase detector for receiving a first clock signal and a second clock signal, and generating a digital signal indicating a relationship between a phase of the first clock signal and a phase of the second clock signal. The example circuit further includes a digital control block for receiving the digital signal and generating a digital control word based on the values ​​of the digital signal over a plurality of clock cycles. A delay element is used to (i) receive the digital control word and (ii) change the relationship between the phases of the first clock signal and the second clock signal by modifying the phase of the second clock signal according to the digital control word. In some embodiments, the delay element includes a coarse tuning element and a fine tuning element, the fine tuning element having a shorter programmable delay increment compared to the coarse tuning element. In some embodiments, the digital control block includes a coarse decoder element and a fine decoder element, the coarse decoder element generating a coarse control word to control the coarse tuning element, and the fine decoder element generating a fine control word to control the fine tuning element. In some embodiments, the circuit further includes a mode switching element. A switching mode element is configured to switch from modifying a delay applied by a coarse tuning element to modifying a delay applied by a fine tuning element when a difference between the phase of the first clock signal and the phase of the second clock signal is less than a delay change amount that can be applied by a coarse tuning element. In some embodiments, the circuit further includes a delay generator. The delay generator is configured to receive (i) an input periodic signal having a frequency equivalent to a desired frequency of the first clock signal and the second clock signal; and to receive (ii) a target phase periodic signal having a period equivalent to a target phase delay between the first clock signal and the second clock signal. In some embodiments, the delay generator is further configured to generate (i) a pre-shifted periodic signal, the pre-shifted periodic signal being an input periodic signal sampled by the target phase periodic signal; and to generate (ii) a phase comparison signal, the phase comparison signal being a pre-shifted periodic signal sampled by the target phase periodic signal. In some embodiments, the circuit further includes a delay generator. A delay generator is used to receive a first clock signal and a target delay signal representing a target phase delay change of the first clock signal. The delay generator is used to generate a second clock signal by sampling the first clock signal at a frequency inversely proportional to the target phase delay change. In some embodiments, the target delay signal is a periodic signal having a period indicating the target phase delay change. In some embodiments, the circuit further includes a lock-in detector. The lock-in detector is used to (i) receive a digital control word and a reference clock, and to (ii) generate a phase lock signal after the digital control word remains below a threshold value for a predetermined number of clock cycles.

[0190] In an example method for operating a delay-locked loop circuit, a first clock signal and a second clock signal are received. A digital signal is generated indicating a relationship between a phase of the first clock signal and a phase of the second clock signal. A phase signal is generated based on the accumulated value of the digital signal over multiple clock cycles. A digital control word is generated based on the phase signal. The relationship between the phases of the first and second clock signals is changed by modifying the phase of the second clock signal according to the digital control word.

[0191] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. A delay circuit, characterized in that, Include: A phase detector is configured to (i) receive a first clock signal and a second clock signal, and (ii) generate a digital signal indicating a relationship between a phase of the first clock signal and a phase of the second clock signal; A phase accumulator circuit is used to receive the digital signal and generate a phase signal based on multiple values ​​of the digital signal over multiple clock cycles; A decoder for receiving the phase signal and generating a digital control character based on the phase signal; and A delay element is provided for receiving the digital control character and for changing the relationship between the phase of the first clock signal and the phase of the second clock signal by modifying the phase of the second clock signal according to the digital control character. The delay element includes a coarse tuning element and a fine tuning element, the fine tuning element having a shorter programmable delay increment compared to the coarse tuning element. The decoder includes a coarse decoder element and a fine decoder element. The coarse decoder element generates a coarse control character to control the coarse tuning element, and the fine decoder element generates a fine control character to control the fine tuning element.

2. The delay circuit according to claim 1, characterized in that, Further includes: A switching mode element is configured to receive the phase signal and, after the phase signal indicates that a difference between the phase of the first clock signal and the phase of the second clock signal is less than a delay change that can be applied by the coarse tuning element, switch from modifying a delay applied by the coarse tuning element to modifying a delay applied by the fine tuning element.

3. The delay circuit according to claim 1, characterized in that, Further includes: A delay generator is configured to receive (i) an input periodic signal having a frequency equivalent to a desired frequency of the first clock signal and the second clock signal; and to receive (ii) a target phase periodic signal having a period equivalent to a target phase delay between the first clock signal and the second clock signal.

4. The delay circuit according to claim 3, characterized in that, The delay generator is further used to generate (i) a pre-shifted periodic signal, which is the input periodic signal sampled by the target phase periodic signal; and to generate (ii) a phase comparison signal, which is the pre-shifted periodic signal sampled by the target phase periodic signal.

5. The delay circuit according to claim 1, characterized in that, Further includes: A delay generator is used to receive the first clock signal and a target delay signal representing a target phase delay change of the first clock signal, the delay generator being used to generate the second clock signal by sampling the first clock signal at a frequency inversely proportional to the target phase delay change.

6. The delay circuit according to claim 5, characterized in that, The target delay signal is a periodic signal with a period of one period, which indicates the change in the target phase delay.

7. The delay circuit according to claim 1, characterized in that, Further includes: A lock detector is configured to (i) receive a digital delay control word and a reference clock, and (ii) generate a phase lock signal after the digital delay control word has been held below a threshold for a predetermined number of clock cycles.

8. The delay circuit according to claim 1, characterized in that, The phase accumulator circuit is used to cyclically accumulate the multiple values ​​of the digital signal in the multiple clock cycles.

9. A delay circuit, characterized in that, Include: A phase detector is used to receive a first clock signal and a second clock signal, and to generate a digital signal indicating a relationship between a phase of the first clock signal and a phase of the second clock signal. A digital control block is used to receive the digital signal and generate a digital control character based on multiple values ​​of the digital signal over multiple clock cycles. A delay element is configured to (i) receive the digital control character and (ii) change the relationship between the phase of the first clock signal and the phase of the second clock signal by modifying the phase of the second clock signal according to the digital control character; and A delay generator is configured to receive (i) an input periodic signal having a frequency equivalent to a desired frequency of the first clock signal and the second clock signal; and to receive (ii) a target phase periodic signal having a period equivalent to a target phase delay between the first clock signal and the second clock signal.

10. The delay circuit according to claim 9, characterized in that, The delay element includes a coarse tuning element and a fine tuning element, the fine tuning element having a shorter programmable delay increment compared to the coarse tuning element.

11. The delay circuit according to claim 10, characterized in that, The digital control block includes a coarse decoder element and a fine decoder element. The coarse decoder element generates a coarse control character to control the coarse tuning element, and the fine decoder element generates a fine control character to control the fine tuning element.

12. The delay circuit according to claim 10, characterized in that, Further includes: A switching mode element is configured to switch from modifying a delay amount applied by the coarse tuning element to modifying a delay amount applied by the fine tuning element when the difference between the phase of the first clock signal and the phase of the second clock signal is less than a delay change amount that can be applied by the coarse tuning element.

13. The delay circuit according to claim 9, characterized in that, The delay generator is further used to generate (i) a pre-shifted periodic signal, which is the input periodic signal sampled by the target phase periodic signal; and to generate (ii) a phase comparison signal, which is the pre-shifted periodic signal sampled by the target phase periodic signal.

14. The delay circuit according to claim 9, characterized in that, in: The delay generator is further used to receive the first clock signal and a target delay signal representing a target phase delay change of the first clock signal. The delay generator is used to generate the second clock signal by sampling the first clock signal at a frequency inversely proportional to the target phase delay change.

15. The delay circuit according to claim 14, characterized in that, The target delay signal is a periodic signal with one period, which indicates the change in the target's phase delay.

16. The delay circuit according to claim 9, characterized in that, Further includes: A lock detector is configured to (i) receive a digital control character and a reference clock, and (ii) generate a phase lock signal after the digital control character has been held below a threshold value for a predetermined number of clock cycles.

17. A delay method, characterized in that, Include: Receive a first clock signal and a second clock signal; A digital signal is generated that indicates a relationship between a phase of the first clock signal and a phase of the second clock signal; A phase signal is generated based on the multiple values ​​accumulated over multiple clock cycles of the digital signal; A digital control character is generated based on this phase signal; The relationship between the phase of the first clock signal and the phase of the second clock signal is changed by modifying the phase of the second clock signal according to the digital control character; and A lock detector receives a digital control word and a reference clock, wherein the lock detector generates a phase lock signal after the digital control word remains below a threshold value for a predetermined number of clock cycles.

18. A delay circuit, characterized in that, Include: A phase accumulator circuit is used to receive a digital signal and generate a phase signal, the digital signal indicating a relationship between a first clock signal and a second clock signal; A decoder is used to receive the phase signal and generate a digital control character; and A delay element is provided for receiving the digital control word and changing the relationship between the first clock signal and the second clock signal, wherein the delay element includes a plurality of tuning elements, one of the plurality of tuning elements having a first programmable delay increment, and another of the plurality of tuning elements having a second programmable delay increment different from the first programmable delay increment, and the decoder includes one or more decoder elements, each of the one or more decoder elements generating a control word corresponding to one of the one or more tuning elements.

19. The delay circuit according to claim 18, characterized in that, Further includes: A switching mode element is configured to receive the phase signal and, after the phase signal indicates that a difference between the first clock signal and the second clock signal is less than a delay change amount that can be applied by a coarse tuning element, switch from modifying a delay amount applied by the coarse tuning element to modifying a delay amount applied by a fine tuning element.

20. The delay circuit according to claim 18, characterized in that, Further includes: A delay generator is configured to receive (i) an input periodic signal and (ii) a target phase periodic signal, the input periodic signal having a frequency equivalent to a desired frequency of the first clock signal and the second clock signal, and the target phase periodic signal having a period equivalent to a target phase delay between the first clock signal and the second clock signal.

21. The delay circuit according to claim 20, characterized in that, The delay generator is further used to generate (i) a pre-shifted periodic signal and (ii) a phase comparison signal, wherein the pre-shifted periodic signal is the input periodic signal sampled by the target phase periodic signal, and the phase comparison signal is the pre-shifted periodic signal sampled by the target phase periodic signal.

22. The delay circuit according to claim 18, characterized in that, Further includes: A delay generator is used to receive the first clock signal and a target delay signal representing a target phase delay change of the first clock signal, the delay generator being used to generate the second clock signal by sampling the first clock signal at a frequency inversely proportional to the target phase delay change.

23. The delay circuit according to claim 22, characterized in that, The target delay signal is a periodic signal with a period of one period, which indicates the change in the target phase delay.

24. The delay circuit according to claim 18, characterized in that, Further includes: A lock detector is used to receive a digital delay control word and a reference clock, and to generate a phase lock signal after the digital delay control word has been kept below a threshold value for a predetermined number of clock cycles.

25. The delay circuit according to claim 18, characterized in that, The phase accumulator circuit is used to accumulate a value of the digital signal in multiple clock cycles.

26. A delay method, characterized in that, Include: A digital signal is generated that indicates a relationship between a first clock signal and a second clock signal; A phase signal is generated based on multiple values ​​of the digital signal; A digital control character is generated based on this phase signal; The relationship between the first clock signal and the second clock signal is changed according to the digital control character; and A digital control word is received at a lock detector, wherein the lock detector generates a phase lock signal after the digital control word remains below a threshold value for a predetermined number of clock cycles.

27. A delay circuit, characterized in that, Include: A phase detector is configured to (i) receive a first clock signal and a second clock signal, and (ii) generate a digital signal indicating a relationship between the first clock signal and the second clock signal. A phase accumulator circuit is used to receive the digital signal and generate a phase signal; A decoder is used to receive the phase signal and generate a digital control character; and A delay element is used to receive the digital control character and change the relationship between the first clock signal and the second clock signal. The delay element includes a coarse-tuning element and a fine-tuning element. The coarse-tuning element has a first programmable delay increment, and the fine-tuning element has a second programmable delay increment different from the first programmable delay increment. The decoder includes one or more decoder elements, each of which generates a control character corresponding to one of the one or more tuning elements.

28. The delay circuit according to claim 27, characterized in that, Further includes: A switching mode element is configured to receive the phase signal and, after the phase signal indicates that a difference between the first clock signal and the second clock signal is less than a delay change that can be applied by the coarse tuning element, switch from modifying a delay applied by the coarse tuning element to modifying a delay applied by the fine tuning element.

29. The delay circuit according to claim 27, characterized in that, Further includes: A delay generator is configured to receive (i) an input periodic signal and (ii) a target phase periodic signal, the input periodic signal having a frequency equivalent to a desired frequency of the first clock signal and the second clock signal, and the target phase periodic signal having a period equivalent to a target phase delay between the first clock signal and the second clock signal.

30. The delay circuit according to claim 29, characterized in that, The delay generator is further used to generate (i) a pre-shifted periodic signal and (ii) a phase comparison signal, wherein the pre-shifted periodic signal is the input periodic signal sampled by the target phase periodic signal, and the phase comparison signal is the pre-shifted periodic signal sampled by the target phase periodic signal.

31. The delay circuit according to claim 27, characterized in that, Further includes: A delay generator is used to receive the first clock signal and a target delay signal representing a target phase delay change of the first clock signal, the delay generator being used to generate the second clock signal by sampling the first clock signal at a frequency inversely proportional to the target phase delay change.

32. The delay circuit according to claim 31, characterized in that, The target delay signal is a periodic signal with a period of one period, which indicates the change in the target phase delay.

33. The delay circuit according to claim 27, characterized in that, Further includes: A lock detector is configured to (i) receive a digital delay control word and a reference clock, and (ii) generate a phase lock signal after the digital delay control word has been held below a threshold for a predetermined number of clock cycles.

34. The delay circuit according to claim 27, characterized in that, The phase accumulator circuit is used to accumulate a value of the digital signal in multiple clock cycles.

35. A delay circuit, characterized in that, Include: A phase detector is used to receive a first clock signal and a second clock signal, and to generate a digital signal indicating a relationship between the first clock signal and the second clock signal. A digital control block is used to receive the digital signal and generate a digital control character; A delay element is used to (i) receive the digital control character and (ii) change the relationship between the first clock signal and the second clock signal according to the digital control character; and A delay generator is used to receive (i) an input periodic signal and (ii) a target phase periodic signal, and to sample the input periodic signal at a rate inversely proportional to a period of the target phase periodic signal.

36. The delay circuit according to claim 35, characterized in that, The delay element includes a coarse tuning element and a fine tuning element, the fine tuning element having a shorter programmable delay increment compared to the coarse tuning element.

37. The delay circuit according to claim 36, characterized in that, The digital control block includes a coarse decoder element and a fine decoder element. The coarse decoder element generates a coarse control character to control the coarse tuning element, and the fine decoder element generates a fine control character to control the fine tuning element.

38. The delay circuit according to claim 36, characterized in that, Further includes: A switching mode element is used to switch from modifying a delay amount applied by the coarse tuning element to modifying a delay amount applied by the fine tuning element when the difference between the first clock signal and the second clock signal is less than a delay change amount that can be applied by the coarse tuning element.

39. The delay circuit according to claim 35, characterized in that, The delay generator is further used to generate (i) a pre-shifted periodic signal and (ii) a phase comparison signal, wherein the pre-shifted periodic signal is the input periodic signal sampled from the target phase periodic signal, and the phase comparison signal is the pre-shifted periodic signal sampled from the target phase periodic signal.

40. The delay circuit according to claim 35, characterized in that, The delay generator is also used to receive the first clock signal and a target delay signal representing a target phase delay change of the first clock signal. The delay generator is used to generate the second clock signal by sampling the first clock signal at a frequency inversely proportional to the target phase delay change.

41. The delay circuit according to claim 40, characterized in that, The target delay signal is a periodic signal with one period, which indicates the change in the target's phase delay.

42. The delay circuit according to claim 35, characterized in that, Further includes: A lock detector is configured to (i) receive a digital control character and a reference clock, and (ii) generate a phase lock signal after the digital control character has been held below a threshold value for a predetermined number of clock cycles.

43. A delay method, characterized in that, Include: Receive a first clock signal and a second clock signal; A digital signal is generated that indicates a relationship between the first clock signal and the second clock signal; A phase signal is generated based on multiple values ​​of the digital signal; A digital control character is generated based on this phase signal; The relationship between the first clock signal and the second clock signal is changed according to the digital control character; and A digital control word is received at a lock detector, wherein the lock detector generates a phase lock signal after the digital control word remains below a threshold value for a predetermined number of clock cycles.

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