Method and system for scanning a MEMS cantilever

Abstract

A method for fabricating a cantilever having a device surface, a tapered surface, and an end region includes providing a semiconductor substrate having a first side surface and a second side surface opposite the first side surface, and etching a predetermined portion of the second side surface to form a plurality of recesses in the second side surface. Each of the plurality of recesses includes an etch stop surface. The method also includes anisotropically etching the etch stop surface to form the tapered surface of the cantilever, and etching a predetermined portion of the device surface to release the end region of the cantilever.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority to U.S. Provisional Patent Application No. 63 / 029,258, filed May 22, 2020, entitled “METHOD AND SYSTEM FOR SCANNING MEMS CANTILEVERS,” the entire contents of which are incorporated herein by reference for all purposes. Background Art

[0003] Modern computing and display technologies have facilitated the development of systems for so-called "virtual reality" or "augmented reality" experiences, in which digitally reproduced images, or portions thereof, are presented to a user in such a way that they appear to be real or can be perceived as real. A virtual reality or "VR" scene typically involves the presentation of digital or virtual image information that is opaque to other actual real-world visual input; an augmented reality or "AR" scene typically involves the presentation of digital or virtual image information as an enhancement to the visualization of the real world around the user.

[0004] Regardless of the advances made in these display technologies, there is a need in the art for improved methods and systems relating to augmented reality systems, and particularly display systems. Summary of the Invention

[0005] The present invention generally relates to methods and systems for fabricating scanning microelectromechanical system (MEMS) cantilevers. More particularly, embodiments of the present invention provide a method and system for fabricating a scanning MEMS cantilever having a tapered profile. The present invention is suitable for various applications in computer vision and image display systems.

[0006] According to an embodiment of the present invention, a method for manufacturing a cantilever is provided. The method includes providing a semiconductor substrate including a first semiconductor layer, a first dielectric layer coupled to the first semiconductor layer, and a second semiconductor layer coupled to the first dielectric layer, forming the second dielectric layer coupled to the first semiconductor layer, forming a third dielectric layer coupled to the second semiconductor layer, and forming a first hard mask layer coupled to the second dielectric layer. The first hard mask layer includes a first set of openings that expose a first surface portion of the second dielectric layer. The method also includes etching the second dielectric layer using the first hard mask layer as a mask, etching the first semiconductor layer using the first hard mask layer as a mask, and etching the first dielectric layer using the first hard mask layer as a mask. The method also includes etching the second semiconductor layer using the first hard mask layer as a mask to form a plurality of recesses, each having a tapered surface. Each of the plurality of recesses includes a first depth at a first region and a second depth greater than the first depth at a second region. Then, the first hard mask layer is removed.

[0007] Furthermore, the method includes forming a second hard mask layer coupled to the third dielectric layer. The second hard mask layer includes a second set of openings that expose a second surface portion of the third dielectric layer, the second surface portion of the third dielectric layer being aligned with at least a portion of the second region of each of the plurality of recesses. The method also includes etching the third dielectric layer and the second semiconductor layer using the second hard mask layer as a mask to extend into the plurality of recesses, removing the second hard mask layer, removing the third dielectric layer, and removing the second dielectric layer.

[0008] In some embodiments, the method further includes forming a chromium layer coupled to the second semiconductor layer.

[0009] In some embodiments, forming the second dielectric layer includes using a low pressure chemical vapor deposition (LPCVD) process.

[0010] In some embodiments, etching the third dielectric layer includes using a reactive ion etching (RIE) process.

[0011] In some embodiments, etching the first semiconductor layer includes using a deep RIE (DRIE) process.

[0012] In some embodiments, the first semiconductor layer is characterized by a (110) crystal orientation.

[0013] In some embodiments, the second semiconductor layer is characterized by a (111) crystal orientation.

[0014] In some embodiments, where the first semiconductor layer and the second semiconductor layer are characterized by different crystal orientations, the first semiconductor layer and the second semiconductor layer are formed separately and then connected together using a bonding process.

[0015] In some embodiments, etching the second semiconductor layer includes using a potassium hydroxide (KOH) process for a predetermined period of time.

[0016] In some embodiments, the method further includes forming a protective dielectric layer coupled to the tapered surfaces of the plurality of recesses and the second dielectric layer.

[0017] In some embodiments, forming the protection dielectric layer is performed after etching the second semiconductor layer.

[0018] According to another embodiment of the present invention, a method for manufacturing a cantilever having a device surface, a tapered surface, and an end region is provided. The method includes providing a semiconductor substrate having a first side surface and a second side surface opposite the first side surface, and etching a predetermined portion of the second side surface to form a plurality of recesses in the second side surface. Each of the plurality of recesses includes an etch stop surface. The method also includes anisotropically etching the etch stop surface to form the tapered surface of the cantilever, and etching a predetermined portion of the device surface to release the end region of the cantilever.

[0019] In some embodiments, the method further includes: anisotropically etching the conical surface of the cantilever to form a first lateral conical surface perpendicular to the first side of the semiconductor substrate, wherein the first lateral conical surface gradually narrows along the conical direction of the conical surface of the cantilever.

[0020] In some embodiments, the method further includes: anisotropically etching the tapered surface of the cantilever to form a second lateral tapered surface perpendicular to the first side surface of the semiconductor substrate, wherein the second lateral tapered surface is formed opposite to the first lateral tapered surface, and wherein the second lateral tapered surface gradually narrows along the tapered direction of the tapered surface of the cantilever.

[0021] In some embodiments, the tapering of the first transverse tapered surface is more rapid than the tapering of the second transverse tapered surface.

[0022] In some embodiments, the tapering of the first transverse tapered surface is more gradual than the tapering of the second transverse tapered surface.

[0023] In some embodiments, the tapering of the first transverse tapered surface is the same as the tapering of the second transverse tapered surface.

[0024] In some embodiments, the method further includes forming a chromium layer coupled to the first side of the semiconductor substrate.

[0025] In some embodiments, the method further includes forming a second dielectric layer coupled to the semiconductor substrate using a low pressure chemical vapor deposition (LPCVD) process.

[0026] In some embodiments, etching the predetermined portion of the second side includes using a RIE process.

[0027] In some embodiments, anisotropically etching the etch stop surface includes using a potassium hydroxide (KOH), ethylenediamine and catechol (EDP), or tetramethylammonium hydroxide (TMAH) process.

[0028] In some embodiments, the semiconductor substrate includes a first semiconductor layer characterized by a (110) crystal orientation and a second semiconductor layer characterized by a (111) crystal orientation.

[0029] In some embodiments, etching the predetermined portion of the device surface includes using a RIE process.

[0030] According to a specific embodiment of the present invention, a method for manufacturing a semiconductor cantilever is provided. The method includes providing a semiconductor substrate. The semiconductor substrate includes a first semiconductor layer, a first dielectric layer coupled to the first semiconductor layer, a second semiconductor layer coupled to the first dielectric layer, a second dielectric layer coupled to the second semiconductor layer, and a third dielectric layer coupled to the second dielectric layer. The method also includes forming a fourth dielectric layer coupled to the first semiconductor layer, forming a fifth dielectric layer coupled to the third dielectric layer, and forming a first hard mask layer coupled to the fourth dielectric layer. The first hard mask layer includes a first set of openings that expose a first surface portion of the fourth dielectric layer.

[0031] The method further includes etching the fourth dielectric layer using the first hardmask layer as a mask, etching the first semiconductor layer using the first hardmask layer as a mask, and etching the first dielectric layer using the first hardmask layer as a mask. The method further includes etching the second semiconductor layer using the first hardmask layer as a mask to form a plurality of recesses, each having a tapered surface. Each of the plurality of recesses includes a first depth at a first region and a second depth greater than the first depth at a second region. The method includes removing the first hardmask layer. Furthermore, the method includes forming a second hardmask layer coupled to the fifth dielectric layer. The second hardmask layer includes a second set of openings exposing a second surface portion of the fifth dielectric layer, the second surface portion of the fifth dielectric layer being aligned with at least a portion of the second region of the tapered surface. Furthermore, the method includes etching the fifth dielectric layer, the third dielectric layer, and the second semiconductor layer using the second hardmask layer as a mask to extend into the plurality of recesses, removing the second hardmask layer, removing the fifth dielectric layer, and removing the fourth dielectric layer.

[0032] In some embodiments, the method further includes forming a chromium layer coupled to the third dielectric layer.

[0033] In some embodiments, forming the fourth dielectric layer includes using an LPCVD process.

[0034] In some embodiments, etching the fourth dielectric layer includes using a RIE process.

[0035] In some embodiments, etching the first semiconductor layer includes using a DRIE process.

[0036] In some embodiments, the semiconductor substrate includes the first semiconductor layer characterized by a (110) crystal orientation and the second semiconductor layer characterized by a (111) crystal orientation.

[0037] In some embodiments, etching the second semiconductor layer includes using a KOH process for a predetermined period of time.

[0038] In some embodiments, the method further includes forming a protective dielectric layer coupled to the tapered surface and the fourth dielectric layer.

[0039] In some embodiments, forming the protective dielectric layer is performed after etching the semiconductor layer.

[0040] The present invention achieves numerous benefits over conventional techniques. For example, embodiments of the present invention provide methods and systems for manufacturing cantilevers that can be integrated into fiber-optic scanning display systems. The methods implemented by embodiments of the present invention can provide cantilevers with uniform quality. Cantilevers manufactured using embodiments of the present invention can include a finely tunable tapered profile. The dimensions of the cantilever's tapered tip can be finely controlled during the manufacturing process to accommodate different fiber-optic scanning display systems.

[0041] These and other embodiments of the present invention, as well as many of their advantages and features, are described in more detail below and in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 is a simplified side view showing a cantilever according to an embodiment of the present invention.

[0043] Figures 2A to 2K is a partial cross-sectional view illustrating an intermediate stage of a method of manufacturing a cantilever according to an embodiment of the present invention.

[0044] Figure 2L is a perspective view showing a cantilever according to an embodiment of the present invention.

[0045] Figure 2M Yes Figure 2K A partial bottom view of the cantilever is shown.

[0046] Figure 2N is a perspective view showing another cantilever according to an embodiment of the present invention.

[0047] Figure 2O FIG. 1 is a partial bottom view showing a cantilever according to another embodiment of the present invention.

[0048] Figure 2P and Figure 2Q is a simplified top view illustrating a cantilever according to an embodiment of the present invention.

[0049] Figure 3 is a simplified flow chart illustrating a method of manufacturing a cantilever according to an embodiment of the present invention.

[0050] Figure 4 is a simplified side view showing a cantilever according to an embodiment of the present invention.

[0051] Figures 5A to 5K is a partial cross-sectional view illustrating a method of manufacturing a cantilever according to an embodiment of the present invention.

[0052] Figure 5L is a perspective view showing a cantilever according to an embodiment of the present invention.

[0053] Figure 5M Yes Figure 5KA partial bottom view of the cantilever is shown.

[0054] Figure 5N is a perspective view showing another cantilever according to an embodiment of the present invention.

[0055] Figure 5O FIG. 1 is a partial bottom view showing a cantilever according to another embodiment of the present invention.

[0056] Figure 5P and Figure 5Q is a simplified top view illustrating a cantilever according to an embodiment of the present invention.

[0057] Figure 6 is a simplified flow chart illustrating a method of manufacturing a cantilever according to an embodiment of the present invention. DETAILED DESCRIPTION

[0058] Embodiments of the present invention relate to methods and systems for fabricating a cantilever for a fiber-optic scanning display system. In some fiber-optic scanning display systems, the scanning tip of the scanning element has a significantly reduced cross-section compared to the normal cross-section of the optical fiber. A cantilever with a tapered scanning tip can be used as a scanning element in a fiber-optic scanning display system. Embodiments of the present invention provide such a cantilever fabricated on a semiconductor substrate.

[0059] Figure 1 1 is a simplified side view showing a cantilever 100 according to an embodiment of the present invention. Figure 1 The cantilever 100 may include a first semiconductor layer 110, a first dielectric layer 120 coupled to the first semiconductor layer 110, and a second semiconductor layer 130 coupled to the first dielectric layer 120. In one embodiment, the cantilever 100 may be fabricated using a silicon-on-insulator (SOI) wafer. In this case, the first semiconductor layer 110 may include silicon and may have a thickness of approximately 300 μm. The first dielectric layer 120 may be a buried oxide (BOX) layer including SiO2 and may have a thickness of approximately 1 μm. The second semiconductor layer 130 may be a device layer including silicon and may have a thickness of approximately 115 μm. The second semiconductor layer 130 may include a device surface 132 in which a MEMS device may be fabricated or attached, and a tapered surface 134 opposite the device surface 132. The second semiconductor layer 130 is substantially divided into a base portion 130 a aligned with the first semiconductor layer 110 and the first dielectric layer 120, and a cantilever portion 130 b protruding from the first semiconductor layer 120. The cantilever portion 130 b may include a tapered surface 134 and an end tip 136 .

[0060] refer to Figures 2A to 2L , a method of manufacturing the cantilever 200 according to an embodiment of the present invention is described. Figure 2A1 is a partial cross-sectional view showing a semiconductor substrate (e.g., an SOI wafer) including a first semiconductor layer 110, a first dielectric layer 120 coupled to the first semiconductor layer 120, and a second semiconductor layer 130 coupled to the first dielectric layer 120. For clarity of description, one side of the second semiconductor layer 130 is designated as the first side of the semiconductor substrate, and one side of the first semiconductor layer 110 is designated as the second side of the semiconductor substrate. In one embodiment, the first semiconductor layer 110 includes silicon having a thickness of approximately 300 μm. The first dielectric layer 120 can be a buried oxide (BOX) layer, such as a SiO2 layer, having a thickness of approximately 1 μm. The second semiconductor layer 130 can include single crystal silicon having a thickness of approximately 115 μm. It should be noted that the thicknesses of the first semiconductor layer 110, the first dielectric layer 120, and the second semiconductor layer 130 can vary to suit a particular application. In one embodiment, the first semiconductor layer 110 is characterized by a (100) or (110) crystal orientation, and the second semiconductor layer 130 is characterized by a (111) crystal orientation. In some embodiments, where the first semiconductor layer 110 and the second semiconductor layer 130 are characterized by different crystal orientations, they can be formed separately and then joined together using a bonding process. The second semiconductor layer 130 includes a device surface 132 in which a MEMS device can be fabricated or attached to the device surface 132. For example, a metal layer (e.g., chromium) can be deposited on the device surface 132. A lift-off process can then be performed to pattern the metal layer.

[0061] refer to Figure 2B , a second dielectric layer 210 is formed on the first semiconductor layer 110, and a third dielectric layer 220 is formed on the second semiconductor layer 130. In one embodiment, the second dielectric layer 210 and the third dielectric layer 220 may include silicon nitride (Si3N4) having a thickness in the range of about 0.5-2 μm. In one embodiment, a low pressure chemical vapor deposition (LPCVD) process may be used to form the second dielectric layer 210 and the third dielectric layer 220. In some embodiments of the present invention, as described more fully below, a cantilever may be formed in which the device surface 132 serves as the device surface of the cantilever. Therefore, the third dielectric layer 220 may protect the device surface 132 from undergoing subsequent etching processes. In some embodiments, suitable for specific applications, the second dielectric layer 210 and / or the third dielectric layer 220 may not be utilized.

[0062] refer to Figure 2C A first hard mask layer 230 is formed on the second dielectric layer 210. The first hard mask layer 230 is patterned to have a first set of openings 232 through which the first surface portion 212 of the second dielectric layer 210 is exposed.

[0063] Figures 2D to 2F An intermediate stage of etching a predetermined portion of the second side of the semiconductor substrate to form a plurality of recesses in the second side is shown, wherein each of the plurality of recesses includes an etch stop surface. Figure 2D An etching process is performed on the second dielectric layer 210 using the first hard mask layer 230 as a mask to form a plurality of recesses 240. In one embodiment, the etching process may include a RIE process.

[0064] refer to Figure 2E An etching process is performed on the first hard mask layer 230 using the first hard mask layer 230 as a mask. In one embodiment, the etching process may include a DRIE process that extends the recess 240 through the first semiconductor layer 110 .

[0065] refer to Figure 2F An etching process is performed on the first dielectric layer 120 using the first hard mask layer 230 as a mask. In one embodiment, the etching process may include an RIE process that forms a recess 240 through the first dielectric layer 120 and forms an etch stop surface 242. Thereafter, the first hard mask layer 230 is removed.

[0066] refer to Figure 2G , the etching stop surface 242 ( Figure 2F An etching process is performed on the second semiconductor layer 130 to form a tapered surface 134 within the second semiconductor layer 130. In one embodiment, the first semiconductor layer 110 is characterized by a (110) crystal orientation, and the second semiconductor layer 130 is characterized by a (111) crystal orientation. The etching process may include a KOH-based etching process. In another embodiment, the etching process may include an EDP process or a TMAH process. In one embodiment, the etching process is performed for a predetermined time period, such as 30 minutes. It should be noted that the time period may vary to suit a particular application depending on the thickness of the second semiconductor layer 130 and the particular etching process employed. In each of the recesses 240, the tapered surface 134 progresses from a base region 137 where the thickness h1 of the second semiconductor layer 130 remains substantially constant to an end region 135 where the thickness h2 of the second semiconductor layer 130 is substantially reduced to a predetermined thickness (such as 10 μm).

[0067] refer to Figure 2H A protective dielectric layer 250 is formed on the tapered surface 134 and the second dielectric layer 210. In one embodiment, the protective dielectric layer 250 may include a SiO2 layer or a photoresist layer having a thickness in the range of approximately 0.5-2 μm. In some embodiments of the present invention, the protective dielectric layer 250 may protect the tapered surface 134 from subsequent etching processes. In other embodiments, depending on the specific application, the method may omit the process of forming the protective dielectric layer 250.

[0068] Figure 2I to Figure 2J An intermediate stage of etching a predetermined portion of the device surface of the semiconductor substrate to release the end region 135 of the cantilever is shown. Figure 2I , a second hard mask layer 260 is formed on the third dielectric layer 220. In one embodiment, the second hard mask layer 260 is patterned to define a second set of openings 262, through which the second surface portion 222 of the third dielectric layer 220 is exposed. In one embodiment, the second surface portion 222 is aligned with at least a portion of the end region 135 of the tapered surface 134 so that the etching process (as defined by the second set of openings 262) can separate the end region 135 of the cantilever from the remaining portion of the second semiconductor layer 130. In one embodiment, the size of the second set of openings 262 is determined so that the thickness h2 at the separated end region 135 is a predetermined value, such as 10 μm.

[0069] refer to Figure 2J , an etching process is performed on the third dielectric layer 220 using the second hard mask layer 260 as a mask. In one embodiment, the etching process may include an RIE process. Then, an additional etching process is performed on the second semiconductor layer 130 using the second hard mask layer 260 as a mask. In one embodiment, the additional etching process may include a buffered oxide etch (BOE) process. After the additional etching process, an end tip 136 is formed at the end region 135. In one embodiment, the thickness of the end tip 136 may be 10 μm.

[0070] refer to Figure 2K , remove the second hard mask layer 260, the third dielectric layer 220, the protective dielectric layer 250 and the second dielectric layer 210. Figure 2K As shown, the cantilever 200 is divided into a base portion 130 a aligned with the first dielectric layer 120 and the first semiconductor layer 110 , and a cantilever portion 130 b having a tapered surface 134 and an end tip 136 .

[0071] Figure 2L 2 is a perspective view showing a cantilever 200 according to an embodiment of the present invention. Figure 2L The cantilever 200 may include a first semiconductor layer 110, a first dielectric layer 120, and a second semiconductor layer 130. The second semiconductor layer 130 includes a device surface 132, a tapered surface 134, and an end tip 136. In addition, the second semiconductor layer 130 may also include Figure 2L Transverse surfaces 134b and 134c are depicted as being parallel to one another.

[0072] Figure 2M Yes Figure 2K A partial bottom view of the cantilever 200 is shown. Figure 2M , as a reference Figure 2G As a result of the KOH etching process described, a tapered structure defined by tapered surfaces 138a, 138b, and 138c is formed within the second semiconductor layer 130. The shaded rectangle marked by the tapered surface 134 represents the Figure 2K 13. The length and width of the cantilever portion 130b are shown. In one embodiment, an additional anisotropic etching process, such as a DRIE process, can be performed to remove portions of the second semiconductor layer 130 represented by the tapered surfaces 138a, 138b, and 138c and to form lateral surfaces 134b and 134c perpendicular to the first side of the semiconductor substrate. In one embodiment, the lateral surfaces 134b and 134c are parallel to each other. In one embodiment, an etching process (such as a DRIE process) can be used to form channels 140a and 140b to provide a passage between the first semiconductor layer 110 and the second semiconductor layer 130.

[0073] Figure 2N is a perspective view illustrating another cantilever 201 according to an embodiment of the present invention. Figure 2N The cantilever 201 shown is Figure 2L The cantilever shown differs in that the cantilever portion 130b ( Figure 2K The three conical surfaces provided by Figure 2N The cantilever 201 includes a first semiconductor layer 110, a first dielectric layer 120, and a second semiconductor layer 130. The second semiconductor layer 130 includes a device surface 132, an end tip 136, a tapered surface 134, and transverse tapered surfaces 134b and 134c. The cantilever 201 having three tapered surfaces 134, 134b, and 134c provides flexibility in adjusting the size of the end tip 136. As discussed below, the positioning of the end tip 136 with respect to the longitudinal axis L1 can be adjusted by controlling the tapering of the transverse tapered surfaces 134b and 134c.

[0074] Figure 2O FIG is a partial bottom view showing a cantilever 201 according to another embodiment of the present invention. Figure 2OWhen etching the portion of the second semiconductor layer 130 represented by the tapered surface 138a to form the lateral surfaces 134b and 134c, the width of the cantilever portion 130b gradually narrows from the base region 137 to the end region 135 to form the two lateral tapered surfaces 134b and 134c. In one embodiment, the tapered surfaces 134b and 134c taper symmetrically about the longitudinal axis L1 of the cantilever 201. In another embodiment, the tapered surfaces 134b and 134c taper asymmetrically about the longitudinal axis L1. For example, the tapered surface 134b may taper more rapidly than the tapered surface 134c. In another embodiment, the tapered surface 134b may taper more slowly than the tapered surface 134c. The tapered taper of the tapered surfaces 134b and / or 134c may vary to suit a particular application.

[0075] Figure 2P and Figure 2Q is a simplified top view showing a cantilever 201 according to an embodiment of the present invention. Figure 2P , the transverse tapered surface 134c gradually narrows more rapidly than the transverse tapered surface 134b. Therefore, the end tip 136 is positioned in a manner such that the center of the end tip is set to the left of the longitudinal axis L1. Therefore, when the end tip 136 is viewed along the direction V1 perpendicular to the device surface 132 and perpendicular to the longitudinal axis L1, as shown in FIG. Figure 2N As shown, the end tip 138 is offset to Figure 2N To the left of the longitudinal axis L1. Figure 2Q , the transverse tapered surface 134c gradually narrows more slowly than the transverse tapered surface 134b. Therefore, the end tip 136 is offset to the right. Therefore, when the end tip 136 is observed along the direction V1 perpendicular to the device surface 132 and perpendicular to the longitudinal axis L1, as shown in FIG. Figure 2N As shown, the end tip 138 is offset to Figure 2N to the right of the longitudinal axis L1.

[0076] The flexibility of adjusting the end tip 136 by controlling the three tapered surfaces 134, 134b and 134c individually or in combination can provide many benefits. For example, cantilever 201 with different configurations of end tips 136 can be used to accommodate different optical configurations of scanning fiber display devices.

[0077] Figure 3 is a simplified flow chart illustrating a method 300 of manufacturing a cantilever according to an embodiment of the present invention. Figure 3The method 300 includes providing a semiconductor substrate including a first semiconductor layer, a first dielectric layer, and a second semiconductor layer (302). In the embodiment shown, the semiconductor substrate may include an SOI substrate including a first semiconductor layer (e.g., Si), a first dielectric layer (e.g., SiO2) coupled to the first semiconductor layer, and a second semiconductor layer (e.g., Si) coupled to the first dielectric layer. In one embodiment, the first semiconductor layer may include a Si layer having a thickness of approximately 300 μm, the first dielectric layer may include a SiO2 layer having a thickness of approximately 1 μm, and the second semiconductor layer may include a Si layer having a thickness of approximately 115 μm.

[0078] Method 300 may further include forming a second dielectric layer coupled to the first semiconductor layer, and forming a third dielectric layer coupled to the second semiconductor layer (302). In one embodiment, the second dielectric layer and the third dielectric layer may include silicon nitride (Si3N4) to protect the upper and lower surfaces of the semiconductor substrate during subsequent etching processes. In some embodiments, method 300 may omit the process of forming the second dielectric layer.

[0079] The method 300 may also include forming a first hard mask layer coupled to the second dielectric layer (306). The first hard mask layer may include a first set of openings exposing a first surface portion of the second dielectric layer.

[0080] The method 300 further includes etching the second dielectric layer, the first semiconductor layer, and the first dielectric layer using the first hard mask layer as a mask (308). In an embodiment, the etching of the second dielectric layer may use a reactive ion etching (RIE) process. In another embodiment, the etching of the first semiconductor layer may use a deep RIE (DRIE) process, which may provide highly anisotropic etching and produce steep side-etched recesses. In one embodiment, the etching of the first dielectric layer may use a RIE process.

[0081] The method 300 further includes: etching the second semiconductor layer using the first hard mask layer as a mask to form a plurality of recesses (310) each having a tapered surface. After the etching process is completed, the method may further include removing the first hard mask layer. Each of the plurality of recesses includes a first depth at a first region and a second depth greater than the first depth at a second region. In one embodiment, the first semiconductor layer is characterized by a (110) crystal orientation, and the second semiconductor layer is characterized by a (111) crystal orientation. Etching the second semiconductor layer may use a potassium hydroxide (KOH) process, which exhibits an etching rate selectivity of 400 times higher for the (100) crystal orientation than for the (111) crystal orientation. In another embodiment, etching the second semiconductor layer may utilize an ethylenediamine and catechol (EDP) process and a tetramethylammonium hydroxide (TMAH) process to etch the second semiconductor layer to form a tapered surface.

[0082] The method 300 may further include forming a protective dielectric layer (312) coupled to the tapered surface of the plurality of recesses and the second dielectric layer. In one embodiment, the protective dielectric layer may include SiO2 or a resist material.

[0083] The method 300 may further include forming a second hard mask layer coupled to the third dielectric layer (314). The second hard mask layer may include a second set of openings that expose a second surface portion of the third dielectric layer. Thus, the second surface portion of the third dielectric layer may be aligned with at least a portion of each of the plurality of recesses.

[0084] Then, the method 300 may further include etching the third dielectric layer and the second semiconductor layer into the plurality of recesses using the second hard mask layer as a mask (316). Thus, because the openings in the hard mask are aligned with a portion of the recesses, the etched area may extend into the recesses. Thereafter, the method may include removing the second hard mask layer, the third dielectric layer, and the second dielectric layer (318).

[0085] It should be understood that Figure 3 The specific steps shown in provide a specific method of manufacturing a cantilever according to an embodiment of the present invention. Other sequences of steps may also be performed according to alternative embodiments. For example, alternative embodiments of the present invention may perform the above steps in a different order. Moreover, Figure 3 The individual steps shown may include multiple sub-steps that can be performed in various orders suitable for the individual steps. In addition, additional steps may be added or removed depending on the specific application. Those skilled in the art will recognize many variations, modifications, and substitutions.

[0086] Figure 4 is a simplified side view showing a cantilever according to an embodiment of the present invention. Figure 4The cantilever 400 may include a first semiconductor layer 410, a first dielectric layer 420 coupled to the first semiconductor layer 420, a second semiconductor layer 430 coupled to the first dielectric layer 420, a second dielectric layer 440 coupled to the second semiconductor layer 430, and a third dielectric layer 450 coupled to the second dielectric layer 440. In one embodiment, the cantilever 400 may be made using a semiconductor substrate, such as a silicon-on-insulator (SO-SOI) wafer. In this case, the first semiconductor layer 410 may include silicon and may have a thickness of approximately 400 μm. The first dielectric layer 120 may be a buried oxide (BOX) layer including SiO2 and may have a thickness of approximately 1 μm. The second semiconductor layer 130 may be a first device layer including silicon and may have a thickness of approximately 105 μm. The second dielectric layer 440 may be another BOX layer including SiO2 and may have a thickness of 1 μm. The third dielectric layer 450 may be a second device layer including silicon and may have a thickness of 10 μm. The third dielectric layer 450 may include a device surface 452 in which a MEMS device may be fabricated or attached. The second semiconductor layer 430, the second dielectric layer 440, and the third dielectric layer 450 are horizontally divided into a base portion 430a and a cantilever portion 430b. The cantilever portion 430b of the second semiconductor layer 430 may include a tapered surface 434 and an end tip 436.

[0087] refer to Figures 5A to 5K , a method of manufacturing a cantilever 500 according to an embodiment of the present invention is described. Figure 5A1 is a partial cross-sectional view illustrating a semiconductor substrate (e.g., an SO-SOI wafer) including a first semiconductor layer 510, a first dielectric layer 520 coupled to the first semiconductor layer 520, a second semiconductor layer 530 coupled to the first dielectric layer 520, a second dielectric layer 540 coupled to the second semiconductor layer 530, and a third dielectric layer 550 coupled to the second dielectric layer 540. For clarity of description, one side of the third dielectric layer 550 is designated as the first side of the semiconductor substrate, and one side of the first semiconductor layer 510 is designated as the second side of the semiconductor substrate. In one embodiment, the first semiconductor layer 510 may include silicon having a thickness of approximately 400 μm. The second semiconductor layer 520 may be a BOX layer, such as a SiO2 layer, and may have a thickness of approximately 1 μm. The second semiconductor layer 530 may be a first device layer including single crystal silicon and may have a thickness of approximately 105 μm. The second dielectric layer 540 may be another BOX layer, such as a SiO2 layer, and may have a thickness of approximately 1 μm. The third dielectric layer 550 can be a second device layer comprising single crystal silicon and can have a thickness of about 10 μm. It should be noted that the thickness of the respective semiconductor layers including the first semiconductor layer 510, the first dielectric layer 520, the second semiconductor layer 530, the second dielectric layer 540, and the third dielectric layer 550 can vary to suit a particular application. In one embodiment, the first semiconductor layer 510 is characterized by a (100) or (110) crystal orientation, the second semiconductor layer 530 is characterized by a (111) crystal orientation, and the third dielectric layer is characterized by a (100) crystal orientation. The third dielectric layer 550 can include a device surface 552 in which a MEMS device can be fabricated or to which a MEMS device can be attached. For example, a metal layer (e.g., chromium) can be deposited on the device surface 552. A lift-off process can then be performed to pattern the metal layer.

[0088] refer to Figure 5B , a fourth dielectric layer 560 is formed on the first semiconductor layer 510, and a fifth dielectric layer 570 is formed on the third dielectric layer 550. In one embodiment, the fourth dielectric layer 560 and the fifth dielectric layer 570 may include silicon nitride (Si3N4) having a thickness in the range of about 0.5-2 μm. In one embodiment, the fourth dielectric layer 560 and the fifth dielectric layer 570 may be formed using an LPCVD process. In some embodiments of the present invention, as described more fully below, a cantilever may be formed in which the device surface 552 serves as the device layer of the cantilever. Therefore, the fifth dielectric layer 570 may protect the device surface 552 during subsequent etching processes. In some embodiments, suitable for specific applications, the fourth dielectric layer 560 and / or the fifth dielectric layer 570 may not be used.

[0089] refer to Figure 5CA first hard mask layer 580 is formed on the fourth dielectric layer 560. The first hard mask layer 580 is patterned to have a first set of openings 582 through which the first surface portion 562 of the fourth dielectric layer 560 is exposed.

[0090] Figures 5D to 5F An intermediate stage of etching a predetermined portion of the second side of the semiconductor substrate to form a plurality of recesses in the second side is shown, wherein each of the plurality of recesses may include an etch stop surface. Figure 5D , an etching process is performed on the fourth dielectric layer 560 using the first hard mask layer 580 as a mask to form a plurality of recesses 512. In one embodiment, the etching process may include a RIE process.

[0091] refer to Figure 5E An etching process is performed on the first semiconductor layer 510 using the first hard mask layer 580 as a mask. In one embodiment, the etching process may include a DRIE process that extends the recess 512 through the first semiconductor layer 510 .

[0092] refer to Figure 5F An etching process is performed on the first dielectric layer 520 using the first hard mask layer 580 as a mask. In one embodiment, the etching process may include an RIE process that forms a recess 512 through the first dielectric layer 520 and forms an etch stop surface 514. Thereafter, the first hard mask layer 580 is removed.

[0093] refer to Figure 5G , an etching process is performed on the second semiconductor layer 530 to form a tapered surface 534 within each of the recesses 512. In one embodiment, the first semiconductor layer 510 is characterized by a (110) crystal orientation, and the second semiconductor layer 530 is characterized by a (111) crystal orientation. The etching process may include a KOH-based etching process, an EDP process, or a TMAH process. In one embodiment, the etching process is performed for a predetermined time period, such as 30 minutes. It should be noted that the time period may vary to suit a particular application depending on the thickness of the second semiconductor layer 530 and the specific etching process employed. In each of the recesses 512, the tapered surface 534 progresses from a base region 537 where the thickness h1 of the second semiconductor layer 530 remains substantially constant to an end region 535 where the thickness h2 of the second semiconductor layer 530 is substantially reduced to a predetermined thickness (such as 10 μm).

[0094] refer to Figure 5H, a protective dielectric layer 526 is formed on the tapered surface 534 and the fourth dielectric layer 560. In one embodiment, the protective dielectric layer 526 may include SiO2 or a photoresist layer having a thickness in the range of approximately 0.5-2 μm. In some embodiments of the present invention, the protective dielectric layer 526 may protect the tapered surface 534 from subsequent etching processes. In some other embodiments, depending on the specific application, the method may omit the process of forming the protective dielectric layer 526.

[0095] Figures 5I to 5J An intermediate stage of etching a predetermined portion of the device surface of the semiconductor substrate to release the end region 535 of the cantilever is shown. Figure 5I , a second hard mask layer 590 is formed on the fifth dielectric layer 570. In one embodiment, the second hard mask layer 590 is patterned to define a second set of openings 592, through which the second surface portion 572 of the fifth dielectric layer 570 is exposed. In one embodiment, the second surface portion 572 is aligned with at least a portion of the end region 535 of the tapered surface 534 so that the etching process (as defined by the second set of openings 592) can separate the end region 535 of the cantilever from the remaining portion of the second semiconductor layer 530. In one embodiment, the size of the third set of openings 592 is determined so that the thickness h2 at the end region 535 after separation is a predetermined value, such as 10 μm.

[0096] refer to Figure 5J , an etching process is performed on the fifth dielectric layer 570 using the second hard mask layer 590 as a mask. In one embodiment, the etching process may include an RIE process. Then, an additional etching process is performed on the third dielectric layer 550, the second dielectric layer 540, and the second semiconductor layer 530 using the second hard mask layer 590 as a mask. In one embodiment, the additional etching process may include a BOE process. After the additional etching process, an end tip 536 is formed at the end region 535. In one embodiment, the thickness of the end tip 536 may be 10 μm.

[0097] refer to Figure 5K , remove the second hard mask layer 590, the fifth dielectric layer 570, the protective dielectric layer 526 and the fourth dielectric layer 560. Figure 5KAs shown, cantilever 500 is divided into a base portion 530a and a cantilever portion 530b. In one embodiment, first semiconductor layer 510 and first dielectric layer 520 may include only base portion 530a, while second semiconductor layer 530, second dielectric layer 540, and third dielectric layer 550 may include base portion 530a and cantilever portion 530b. In one embodiment, cantilever portion 530b of second semiconductor layer 530 includes a tapered surface 534 and an end tip 536, cantilever portion 520b of second dielectric layer 540 includes an end surface 546, and cantilever portion 530b of third dielectric layer 550 includes an end surface 556. In some embodiments, end tip 536, end surface 546, and end surface 556 may be configured in combination to function as a light emitting tip for a scanning fiber optic display device. In other embodiments, it is possible that only end tip 536 functions as the light emitting tip for a scanning fiber optic display device.

[0098] Figure 5L is a perspective view showing a cantilever 500 according to an embodiment of the present invention. Figure 5L , the cantilever 500 may include a first semiconductor layer 510, a first dielectric layer 520, a second semiconductor layer 530, a second dielectric layer 540, and a third dielectric layer 550. The second semiconductor layer 530 includes a tapered surface 534 and an end tip 536. The second dielectric layer 540 includes an end surface 546. The third dielectric layer 550 includes a device surface 552 and an end surface 556. In addition, the second semiconductor layer 530, the second dielectric layer 540, and the third dielectric layer 550 may include lateral surfaces 534b and 534c that are parallel to each other as described below.

[0099] Figure 5M Yes Figure 5K A partial bottom view of the cantilever 500 is shown. Figure 5M , as a reference Figure 5G As a result of the described KOH etching process, a tapered structure defined by tapered surfaces 538a, 538b, and 538c is formed within the second semiconductor layer 530. The shaded rectangle marked by the tapered surface 534 represents the length and width of the cantilever portion 530b, as shown in FIG. Figure 5LAs shown. In one embodiment, an additional anisotropic etching process, such as a DRIE process, can be performed to remove portions of the second semiconductor layer 530, the second dielectric layer 540, and the third dielectric layer 550, represented by the tapered surfaces 538a, 538b, and 538c, and to form lateral surfaces 534b and 534c perpendicular to the first side of the semiconductor substrate. In one embodiment, the lateral surfaces 534b and 534c are parallel to each other. In one embodiment, an etching process, such as a DRIE process, can be used to form channels 539a and 539b to provide a passage between the first semiconductor layer 510, the second semiconductor layer 530, and the third dielectric layer 550.

[0100] Figure 5N is a perspective view showing another cantilever 501 according to another embodiment of the present invention. Figure 5N The cantilever 501 includes a first semiconductor layer 510, a first dielectric layer 520, a second semiconductor layer 530, a second dielectric layer 540, and a third dielectric layer 550. The second semiconductor layer 530 includes a tapered surface 534 and an end tip 536. The second dielectric layer 540 includes an end surface 546, and the third dielectric layer 550 includes an end surface 556. The second semiconductor layer 530, the second dielectric layer 540, and the third dielectric layer 550 include transverse tapered surfaces 534b and 534c at the cantilever portion 530b. The cantilever 501 having three tapered surfaces 534, 534b, and 534c provides flexibility in adjusting the dimensions of the end tip 536, the end surface 546, and the end surface 556. As discussed below, the positioning of the end tip 536, the end surface 546, and the end surface 556 with respect to the longitudinal axis L1 can be adjusted by controlling the tapering of the transverse tapered surfaces 534b and 534c.

[0101] Figure 5O FIG. 5 is a partial bottom view showing a cantilever 501 according to another embodiment of the present invention. Figure 5O The cantilever 501 shown is Figure 5M The cantilever shown differs in that the cantilever portion 530b ( Figure 5N The three conical surfaces provided by Figure 5OWhen etching the portion of the second semiconductor layer 530, the second dielectric layer 540, and the third dielectric layer 550 represented by the tapered surface 538a, the width of the cantilever portion 530b gradually narrows from the base region 537 to the end region 535 to form two transverse tapered surfaces 534b and 534c. In one embodiment, the tapered surfaces 534b and 534c taper symmetrically about the longitudinal axis L1 of the cantilever 501. In another embodiment, the tapered surfaces 534b and 534c may taper asymmetrically about the longitudinal axis L1. For example, the tapered surface 534b may taper more rapidly than the tapered surface 534c. In another embodiment, the tapered surface 534b may taper more slowly than the tapered surface 534c. The tapered surfaces 534b and 534c may taper to suit a particular application.

[0102] Figure 5P and Figure 5Q is a simplified top view showing a cantilever 501 according to an embodiment of the present invention. Figure 5P , the transverse tapered surface 534c tapers more rapidly than the transverse tapered surface 534b. Therefore, the end tip 536, the end surface 546 (not shown), and the end surface 556 (not shown) are positioned in a manner such that the center of the end tip is set to the left of the longitudinal axis L1. Therefore, when the end tip 536 is viewed along a direction V1 perpendicular to the device surface 552 and perpendicular to the longitudinal axis L1, as shown in FIG. Figure 5N As shown, the end tip 138, the end surface 546 and the end surface 556 can be offset to Figure 5N To the left of the longitudinal axis L1. Figure 5Q , the transverse tapered surface 534c gradually narrows more slowly than the transverse tapered surface 534b. Figure 5N When viewing the end tip 536 in the direction V1 shown perpendicular to the device surface 552 and perpendicular to the longitudinal axis L1, the end tip 138, the end surface 546, and the end surface 556 may be offset to Figure 5N to the right of the longitudinal axis L1.

[0103] The flexibility of adjusting the end tip 536, end surface 546, and end surface 556 by controlling the three tapered surfaces 534, 534b, and 534c individually or in combination can provide many benefits. For example, cantilever 501 with different configurations of end tip 536, end surface 546, and end surface 556 can be used to accommodate different optical configurations of scanning fiber display devices.

[0104] Figure 6 is a simplified flow chart illustrating a method 600 of manufacturing a cantilever according to an embodiment of the present invention. Figure 6, method 600 includes providing a semiconductor substrate comprising a first semiconductor layer, a first dielectric layer, a second semiconductor layer, a second dielectric layer, and a third dielectric layer (602). In the embodiment shown, the semiconductor substrate may include an SO-SOI substrate comprising a first semiconductor layer (e.g., Si), a first dielectric layer (e.g., SiO2) coupled to the first semiconductor layer, a second semiconductor layer (e.g., Si) coupled to the first dielectric layer, a second dielectric layer (e.g., Si) coupled to the second semiconductor layer, and a third dielectric layer (e.g., Si) coupled to the second dielectric layer. In one embodiment, the first semiconductor layer may include a Si layer having a thickness of approximately 400 μm, the first dielectric layer may include a SiO2 layer having a thickness of approximately 1 μm, the second semiconductor layer may include a Si layer having a thickness of approximately 105 μm, the second dielectric layer may include a SiO2 layer having a thickness of approximately 1 μm, and the third dielectric layer may include a Si layer having a thickness of approximately 10 μm.

[0105] Method 600 may also include forming a fourth dielectric layer coupled to the first semiconductor layer; and forming a fifth dielectric layer coupled to the third dielectric layer (604). In one embodiment, the fourth and fifth dielectric layers may include Si3N4 to protect the lower and upper surfaces of the semiconductor substrate during subsequent etching processes. In some embodiments, method 600 may omit the process of forming the fourth dielectric layer.

[0106] The method 600 may also include forming a first hard mask layer coupled to the fourth dielectric layer (606).The first hard mask layer may include a first set of openings exposing a first surface portion of the fourth dielectric layer.

[0107] The method 600 may further include etching the fourth dielectric layer, the first semiconductor layer, and the first dielectric layer using the first hard mask layer as a mask (608). In one embodiment, the etching of the fourth dielectric layer may use a RIE process. In another embodiment, the etching of the first semiconductor layer may use a DRIE process. In one embodiment, the etching of the first dielectric layer may use a RIE process.

[0108] The method 600 further includes: etching the second semiconductor layer using the first hard mask layer as a mask to form a plurality of recesses (610) each having a tapered surface. Each of the plurality of recesses may include a first depth at a first region and a second depth greater than the first depth at a second region. After the etching process is completed, the method may further include: removing the first hard mask layer. In one embodiment, the first semiconductor layer is characterized by a (110) crystal orientation, and the second semiconductor layer is characterized by a (111) crystal orientation. Etching the second semiconductor layer may use a KOH-based process. In another embodiment, etching the second semiconductor layer may utilize an EDP process and a TMAH process to etch the second semiconductor layer to form a tapered surface.

[0109] The method 600 may further include forming a protective dielectric layer (612) coupled to the tapered surfaces of the plurality of recesses and the fourth dielectric layer. In one embodiment, the protective dielectric layer may include SiO2 or a resist material.

[0110] Method 600 may also include forming a second hard mask layer coupled to the fifth dielectric layer (614). The second hard mask layer may include a second set of openings that expose a second surface portion of the fifth dielectric layer. Thus, the second surface portion of the fifth dielectric layer may be aligned with at least a portion of the second region of each of the plurality of recesses.

[0111] The method may then further include etching the fifth dielectric layer, the third dielectric layer, and the second semiconductor layer using the second hard mask layer as a mask and etching into the plurality of recesses (616). Thereafter, the method may include removing the second hard mask layer, the fifth dielectric layer, and the fourth dielectric layer (618).

[0112] It should be understood that Figure 6 The specific steps shown in provide a specific method of manufacturing a cantilever according to an embodiment of the present invention. Other sequences of steps may also be performed according to alternative embodiments. For example, alternative embodiments of the present invention may perform the above steps in a different order. Moreover, Figure 6 The individual steps shown may include multiple sub-steps that may be performed in various orders suitable for the individual steps. In addition, additional steps may be added or removed depending on the specific application. Those skilled in the art will recognize many variations, modifications, and substitutions.

[0113] Embodiments of the present invention are described herein with reference to the accompanying drawings. However, the present invention can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present invention will be exhaustive and complete, and to fully convey the scope of the present invention to those skilled in the art. Features may not be drawn to scale, and for clarity, some details may be exaggerated relative to other elements. Like numbers refer to like elements throughout.

[0114] It should be understood that the drawings are not drawn to scale and that like reference numerals are used to represent like elements. As used herein, the terms "example embodiment," "exemplary embodiment," and "present embodiment" do not necessarily refer to a single embodiment, although they can, and the various example embodiments can be easily combined and interchanged without departing from the scope or spirit of the invention.

[0115] Furthermore, the terms used herein are for the purpose of describing example embodiments only and are not intended to limit the present invention. In this regard, as used herein, the term "in" may include "in" and "on," and the terms "a," "an," and "the" may include singular and plural references. Furthermore, as used herein, depending on the context, the term "by" may also mean "from." Furthermore, as used herein, depending on the context, the term "if" may also mean "when" or "at." Furthermore, as used herein, the word "and / or" may be any possible combination that indicates and includes one or more of the associated list items.

[0116] It should be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another region, layer, or portion. Thus, a first element, component, region, layer, or portion discussed below may be referred to as a second element, component, region, layer, or portion without departing from the teachings of the present invention.

[0117] The term "horizontal" as used in this application is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer and substrate. The term "vertical" refers to a direction perpendicular to the horizontal as defined above. Prepositions such as "on...", "side" (as in "sidewall"), "below...", "above...", "higher", "lower", "above..." and "below..." are defined relative to a conventional plane or surface on the top surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. It should be understood that these terms are intended to encompass different orientations of the device in addition to the orientation shown in the accompanying drawings.

[0118] It should be understood that the appended claims are not limited to the precise configuration shown in the drawings. Those skilled in the art will recognize that various modifications, substitutions and changes may be made to the arrangements and steps of the above-described methods and apparatus without departing from the scope of the present invention.

Claims

1. A method for manufacturing a cantilever, the method comprising: providing a semiconductor substrate comprising a first semiconductor layer, a first dielectric layer coupled to the first semiconductor layer, and a second semiconductor layer coupled to the first dielectric layer; forming a second dielectric layer coupled to the first semiconductor layer; forming a third dielectric layer coupled to the second semiconductor layer; forming a first hard mask layer coupled to the second dielectric layer, wherein the first hard mask layer includes a first set of openings exposing a first surface portion of the second dielectric layer; etching the second dielectric layer using the first hard mask layer as a mask; etching the first semiconductor layer using the first hard mask layer as a mask; etching the first dielectric layer using the first hard mask layer as a mask; etching the second semiconductor layer using the first hard mask layer as a mask to form a plurality of recesses each having a tapered surface, wherein each of the plurality of recesses includes a first depth at a first region and a second depth greater than the first depth at a second region; removing the first hard mask layer; forming a second hard mask layer coupled to the third dielectric layer, wherein the second hard mask layer includes a second set of openings exposing a second surface portion of the third dielectric layer, wherein the second surface portion of the third dielectric layer is aligned with at least a portion of the second region of each of the plurality of recesses; etching the third dielectric layer and the second semiconductor layer to extend into the plurality of recesses using the second hard mask layer as a mask; removing the second hard mask layer; removing the third dielectric layer; and The second dielectric layer is removed.

2. The method according to claim 1, further comprising: A chromium layer is formed coupled to the second semiconductor layer.

3. The method according to claim 1, wherein Forming the second dielectric layer includes using a low pressure chemical vapor deposition (LPCVD) process.

4. The method according to claim 1, wherein Etching the third dielectric layer includes using a reactive ion etching (RIE) process.

5. The method according to claim 1, wherein Etching the first semiconductor layer includes using a deep RIE (DRIE) process.

6. The method according to claim 1, wherein The first semiconductor layer is characterized by a (1 1 0) crystal orientation.

7. The method according to claim 1, wherein The second semiconductor layer is characterized by a (1 1 1) crystal orientation.

8. The method according to claim 1, wherein Etching the second semiconductor layer includes using a potassium hydroxide (KOH) process for a predetermined period of time.

9. The method according to claim 1, further comprising: A protective dielectric layer coupled to the tapered surfaces of the plurality of recesses and the second dielectric layer is formed.

10. The method according to claim 9, wherein: Forming the protective dielectric layer is performed after etching the second semiconductor layer.

11. A method for manufacturing a semiconductor cantilever, the method comprising: Providing a semiconductor substrate, wherein the semiconductor substrate includes a first semiconductor layer, a first dielectric layer coupled to the first semiconductor layer, a second semiconductor layer coupled to the first dielectric layer, a second dielectric layer coupled to the second semiconductor layer, and a third dielectric layer coupled to the second dielectric layer; forming a fourth dielectric layer coupled to the first semiconductor layer; forming a fifth dielectric layer coupled to the third dielectric layer; forming a first hard mask layer coupled to the fourth dielectric layer, wherein the first hard mask layer includes a first set of openings exposing a first surface portion of the fourth dielectric layer; etching the fourth dielectric layer using the first hard mask layer as a mask; etching the first semiconductor layer using the first hard mask layer as a mask; etching the first dielectric layer using the first hard mask layer as a mask; etching the second semiconductor layer using the first hard mask layer as a mask to form a plurality of recesses each having a tapered surface, wherein each of the plurality of recesses includes a first depth at a first region and a second depth greater than the first depth at a second region; forming a second hard mask layer coupled to the fifth dielectric layer, wherein the second hard mask layer includes a second set of openings exposing a second surface portion of the fifth dielectric layer, wherein the second surface portion of the fifth dielectric layer is aligned with at least a portion of the second region in the tapered surface; etching the fifth dielectric layer, the third dielectric layer, and the second semiconductor layer to extend into the plurality of recesses using the second hard mask layer as a mask; removing the second hard mask layer; removing the fifth dielectric layer; and The fourth dielectric layer is removed.

12. The method according to claim 11, further comprising: A chromium layer is formed coupled to the third dielectric layer.

13. The method according to claim 11, wherein Forming the fourth dielectric layer includes using an LPCVD process.

14. The method according to claim 11, wherein Etching the fourth dielectric layer includes using a RIE process.

15. The method according to claim 11, wherein Etching the first semiconductor layer includes using a DRIE process.

16. The method according to claim 11, wherein The first semiconductor layer is characterized by a (1 1 0) crystal orientation, and the second semiconductor layer is characterized by a (1 1 1) crystal orientation.

17. The method according to claim 11, wherein The second semiconductor layer is characterized by a (1 1 1) crystal orientation.

18. The method according to claim 11, wherein Etching the second semiconductor layer includes using a potassium hydroxide (KOH) process for a predetermined period of time.

19. The method according to claim 11, further comprising: A protective dielectric layer is formed that is coupled to the tapered surface and the fourth dielectric layer.

20. The method according to claim 19, wherein Forming the protective dielectric layer is performed after etching the second semiconductor layer.

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