Semiconductor inspection method and semiconductor inspection apparatus

Abstract

A semiconductor inspection method of an embodiment of the present invention includes the steps of: acquiring, for each irradiation position of a laser, characteristic information indicating a characteristic of an electrical signal of a semiconductor device corresponding to irradiation of the laser by scanning the laser against the semiconductor device; generating a first pattern image of the semiconductor device based on the characteristic information for each irradiation position; generating a second pattern image of the semiconductor device based on a layout image of the semiconductor device and current path information indicating a current path of the semiconductor device; and acquiring matching information indicating a relative relationship between the first pattern image and the layout image based on a result of position alignment of the first pattern image and the second pattern image.

Description

Technical Field

[0001] This disclosure relates to a semiconductor inspection method and a semiconductor inspection apparatus. Background Technology

[0002] Previously, techniques for fault analysis based on images of semiconductor devices (DUTs) that are the objects of inspection were known. For example, Patent Documents 1 and 2 disclosed methods for aligning an optical image obtained by capturing reflected light from a semiconductor device as a pattern image representing the pattern of the semiconductor device with a layout image (design image) such as a CAD image showing the layout of the semiconductor device. By performing such alignment, for example, an overlapping image can be obtained that coincides with a fault analysis image of the semiconductor device obtained by an inspection device (e.g., a light-emitting image showing the fault location of the semiconductor device by emitting light) and the layout image of the semiconductor device. By utilizing such an overlapping image, fault analysis of the semiconductor device can be easily performed.

[0003] [Existing technical documents]

[0004] [Patent Literature]

[0005] Patent Document 1: Japanese Patent Application Publication No. 2007-00306

[0006] Patent Document 2: International Publication No. 2015 / 098342 Summary of the Invention

[0007] [The problem the invention aims to solve]

[0008] However, in recent years, the miniaturization of semiconductor device patterns has made it difficult to obtain optical images that can accurately identify the patterns of semiconductor devices. Therefore, there are situations where it is difficult to accurately align the pattern image obtained from the semiconductor device with the layout image.

[0009] Therefore, one aspect of this disclosure aims to provide a semiconductor inspection method and apparatus that can precisely align a pattern image obtained from a semiconductor device with a layout image of the semiconductor device.

[0010] [Technical means to solve the problem]

[0011] A semiconductor inspection method of one aspect disclosed herein includes the following steps: scanning light onto a semiconductor device, obtaining characteristic information representing the characteristics of an electrical signal of the semiconductor device corresponding to the light irradiation at each irradiation position, generating a first pattern image of the semiconductor device based on the characteristic information at each irradiation position; generating a second pattern image of the semiconductor device based on a layout image representing the layout of the semiconductor device and current path information representing the current path of the semiconductor device; and obtaining matching information representing the relative relationship between the first pattern image and the layout image based on the positional alignment result of the first pattern image and the second pattern image.

[0012] It is known that light illuminating a semiconductor device (e.g., laser light) has a certain degree of spread, and the full width at half maximum (FWHM) of the reflected light from the semiconductor device is greater than that of the incident light (FWHM) towards the semiconductor device. Here, the resolution of an optical image obtained based on reflected light depends on the observed FWHM of the reflected light, while the resolution of a first pattern image not based on reflected light depends on the FWHM of the incident light towards the semiconductor device. Furthermore, the smaller the FWHM of the light, the lower the resolution of the obtained image. Therefore, by generating a first pattern image based on the characteristics of the electrical signal of the semiconductor device corresponding to the light irradiation, a higher resolution image than an optical image obtained based on reflected light can be obtained. Furthermore, based on the positional alignment result of a second pattern image obtained from the layout image and the current path of the semiconductor device with the first pattern image, highly accurate matching information between the first pattern image and the layout image can be obtained. Based on the above description, the semiconductor inspection method described above can precisely align the pattern image (first pattern image) obtained from the semiconductor device with the layout image of the semiconductor device.

[0013] The step of generating the second pattern image may include: a first process, which classifies at least one of at least a portion of the diffusion layer and at least one of the component separation layer contained in the semiconductor device based on current path information, and sets a color corresponding to the classification for at least one of the at least a portion of the diffusion layer and at least one of the component separation layer in the layout image; and a second process, which generates the second pattern image based on the colored image generated by the first process. According to the above configuration, a second pattern image that can be aligned with the first pattern image with high precision can be obtained from the colored image colored based on current path information.

[0014] The second process may include blurring the colored image. Based on the above configuration, a second pattern image similar to the first pattern image can be obtained through blurring. As a result, a second pattern image that can be precisely aligned with the first pattern image can be obtained.

[0015] The second process may include the following steps: learning a transformation process for the shading image using machine learning on teaching data, the teaching data including the shading image to be learned and a first pattern image corresponding to the shading image to be learned; and transforming the shading image using the transformation process determined by the learning process, thereby generating the second pattern image. According to the above configuration, a second pattern image similar to the first pattern image can be obtained through the transformation process based on the results of machine learning. As a result, the positional alignment of the first pattern image and the second pattern image can be performed with high precision.

[0016] The step of obtaining matching information may include the following processing: prompting the user with a first pattern image and a second pattern image; and obtaining matching information based on information specified by the user indicating the correspondence between the first pattern image and the second pattern image. According to the above configuration, the user can perform visual alignment of the first and second pattern images.

[0017] The step of obtaining matching information may include the following processing: learning the positional alignment process of a first pattern image and a second pattern image using machine learning on teaching data, wherein the teaching data includes the first pattern image for learning, the second pattern image corresponding to the first pattern image for learning, and the matching results of these images; and performing positional alignment of the first pattern image and the second pattern image using the positional alignment process determined by learning, thereby obtaining matching information. According to the above configuration, the positional alignment of the first pattern image and the second pattern image can be performed with high precision through positional alignment processing based on the results of machine learning.

[0018] The semiconductor inspection method may further include the following steps: generating an overlap image that overlaps the layout image and the first pattern image based on matching information. According to the above configuration, an overlap image that accurately overlaps the layout image and the first pattern image can be obtained based on the matching information. As a result, fault analysis using the overlap image can be performed with high precision.

[0019] The semiconductor inspection method may further include the following steps: based on matching information, identifying the fault location determined through fault analysis of the semiconductor device and its location on the layout image, or setting the detection location of the semiconductor device. According to the above configuration, by utilizing matching information, fault analysis (determination of the fault location on the layout image or setting of the detection location) can be performed with high precision.

[0020] In the step of generating the first pattern image, a measured value of the photovoltaic current generated by irradiating light onto the semiconductor device can be obtained as characteristic information. Based on the above configuration, an OBIC (Optical Beam Induced Current) image with a hue (depth) set to correspond to the measured value of the photovoltaic current can be obtained as the first pattern image.

[0021] The semiconductor device may have a semiconductor substrate having a main surface on which transistors are formed and a back surface opposite to the main surface. In the step of generating the first pattern image, light transmitted from the back surface to the main surface can be irradiated onto the back surface of the semiconductor substrate. This light may have an energy higher than the band gap of the semiconductor substrate material. Based on this configuration, OBICs can be preferably generated in the transistors on the main surface of the semiconductor substrate by generating single-photon absorption (SPA).

[0022] The semiconductor device may have a semiconductor substrate having a main surface on which transistors are formed and a back surface opposite to the main surface. In the step of generating the first pattern image, pulsed light, i.e., light transmitted from the back surface to the main surface, may be irradiated onto the back surface of the semiconductor substrate. The light may have energy lower than the band gap of the semiconductor substrate material. According to the above configuration, OBIC can be preferably generated in the transistors on the main surface side of the semiconductor substrate by generating multiphoton absorption (MPA).

[0023] One aspect of the semiconductor inspection apparatus disclosed herein includes: a light source; a scanning unit that scans light from the light source onto a semiconductor device; a measuring unit electrically connected to the semiconductor device that measures the characteristics of an electrical signal of the semiconductor device corresponding to the irradiation of light at each irradiation position; a first generating unit that generates a first pattern image of the semiconductor device based on characteristic information representing the characteristics of the electrical signal at each irradiation position measured by the measuring unit; a second generating unit that generates a second pattern image of the semiconductor device based on a layout image representing the layout of the semiconductor device and current path information representing the current path of the semiconductor device; and a processing unit that obtains matching information representing the relative relationship between the first pattern image and the layout image based on the result of the positional alignment of the first pattern image and the second pattern image.

[0024] The semiconductor inspection apparatus described above can preferably be used to perform the semiconductor inspection method described above.

[0025] The second generation unit can perform: a first process, which classifies at least one of at least a portion of the diffusion layer and at least one of the component separation layer contained in the semiconductor device based on current path information, and sets a color corresponding to the classification for at least one of the at least a portion of the diffusion layer and at least one of the component separation layer in the layout image; and a second process, which generates a second pattern image based on the color image generated by the first process. According to the above configuration, a second pattern image that can be precisely aligned with the position of the first pattern image can be obtained from the color image colored based on current path information.

[0026] The second process may include blurring the colored image. Based on the above configuration, a second pattern image similar to the first pattern image can be obtained through blurring. As a result, a second pattern image that can be precisely aligned with the first pattern image can be obtained.

[0027] The second process can perform the following steps: learning a transformation process for the shading image using machine learning on teaching data, which includes the shading image to be learned and a first pattern image corresponding to the shading image; and transforming the shading image using the transformation process determined through learning, thereby generating the second pattern image. Based on the above configuration, a second pattern image similar to the first pattern image can be obtained through the transformation process based on the results of machine learning. As a result, the positions of the first and second pattern images can be aligned with high precision.

[0028] The processing unit can perform the following processes: prompting the user with a first pattern image and a second pattern image; and obtaining matching information based on information specified by the user indicating the correspondence between the first pattern image and the second pattern image. According to the above configuration, the user can perform visual alignment of the first pattern image and the second pattern image.

[0029] The processing unit can perform the following processes: learning the positional alignment process of a first pattern image and a second pattern image using machine learning on teaching data, wherein the teaching data includes the first pattern image for learning, the second pattern image corresponding to the first pattern image for learning, and the matching results of these images; and performing positional alignment of the first pattern image and the second pattern image using the positional alignment process determined by learning, thereby obtaining matching information. Based on the above configuration, the positional alignment of the first pattern image and the second pattern image can be performed with high precision through positional alignment processing based on the results of machine learning.

[0030] The processing unit can generate an overlapping image that overlaps the layout image and the first pattern image based on matching information. According to the above configuration, an overlapping image that accurately overlaps the layout image and the first pattern image can be obtained based on the matching information. As a result, fault analysis and other tasks using the overlapping image can be performed with high precision.

[0031] The processing unit can, based on the matching information, determine the location of the fault, as determined by fault analysis of the semiconductor device, and its location on the layout image, or set the detection location of the semiconductor device. According to the above configuration, by utilizing the matching information, fault analysis (determination of the fault location on the layout image or setting of the detection location) can be performed with high precision.

[0032] The measurement unit can acquire a measurement value of the photovoltaic current generated by irradiating light onto the semiconductor device as characteristic information. Based on the above configuration, an OBIC (Optical Beam Induced Current) image with a hue (depth) corresponding to the measured value of the photovoltaic current can be obtained as the first pattern image.

[0033] The semiconductor device may have a semiconductor substrate having a main surface on which transistors are formed and a back surface opposite to the main surface. A scanning unit can scan light transmitted from the back surface to the main surface of the semiconductor substrate, and the light may have energy higher than the band gap of the semiconductor substrate material. Based on this configuration, OBIC can be preferably generated in the transistors on the main surface of the semiconductor substrate by generating single-photon absorption (SPA).

[0034] The semiconductor device may have a semiconductor substrate having a main surface on which transistors are formed and a back surface opposite to the main surface. A scanning unit can scan the back surface of the semiconductor substrate with pulsed light transmitted from the back surface to the main surface. The light may have energy lower than the band gap of the semiconductor substrate material. Based on this configuration, multiphoton absorption (MPA) can be generated in the transistors on the main surface of the semiconductor substrate, thus enabling better generation of OBICs.

[0035] [The effects of the invention]

[0036] According to one aspect of this disclosure, a semiconductor inspection method and a semiconductor inspection apparatus are provided that can precisely align a pattern image obtained from a semiconductor device with a layout image of the semiconductor device. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of a semiconductor inspection apparatus according to one embodiment.

[0038] Figure 2 A schematic diagram showing an example of the configuration of a semiconductor device.

[0039] Figure 3 (A) and (B) are schematic diagrams showing an example of the layout of a portion of a semiconductor device.

[0040] Figure 4 This is a diagram showing an example of a layout image.

[0041] Figure 5 This is a diagram showing an example of an OBIC image (the first pattern image).

[0042] Figure 6 A graph showing the relationship between the wavelength of the laser and the resolution of the OBIC image, and the relationship between the wavelength of the laser and the transmittance of the silicon substrate.

[0043] Figure 7 An example of setting an image for a display box.

[0044] Figure 8 A diagram showing an example of a colored image.

[0045] Figure 9 This is a diagram showing an example of a blurred image (the second pattern image).

[0046] Figure 10 A flowchart illustrating an example of the operation of a semiconductor inspection device.

[0047] Figure 11 A diagram showing the relationship between the images generated by the semiconductor inspection device.

[0048] Figure 12 A schematic diagram showing a first configuration example for obtaining OBIC signals.

[0049] Figure 13 A schematic diagram showing a second configuration example for obtaining OBIC signals.

[0050] Figure 14 (A) is a schematic diagram showing a third configuration example for obtaining OBIC signals. Figure 14 (B) is a schematic diagram showing the fourth configuration example used to obtain the OBIC signal.

[0051] Figure 15 This is a schematic diagram showing a fifth configuration example for obtaining OBIC signals. Detailed Implementation

[0052] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. Furthermore, in the description of the drawings, the same symbols are assigned to the same elements, and repeated descriptions are omitted.

[0053] Figure 1 This is a schematic diagram of a semiconductor inspection apparatus 1 according to one embodiment. Figure 2 This is a schematic diagram of a configuration example of a semiconductor device 10, which is the object of inspection. The semiconductor device 10 may be, for example, an IC (integrated circuit) such as a logic LSI, memory, or analog circuit, or a power device. As an example, the semiconductor device 10 includes a semiconductor chip 11 and a packaging substrate 12. The semiconductor chip 11 includes a semiconductor substrate 11A, a wiring layer 11B, and bumps B.

[0054] The semiconductor substrate 11A has a main surface 11a for forming a transistor T, such as a MOS transistor, and a back surface 11b opposite to the main surface 11a. The semiconductor substrate 11A is, for example, a silicon substrate. However, the material of the semiconductor substrate 11A is not limited to silicon. For example, when the semiconductor device 10 is a high-frequency device, a photonic device, or the like, compound semiconductors such as GaAs and GaP can be used as the material of the semiconductor substrate 11A. Furthermore, when the semiconductor device 10 is a power device, materials such as SiC and GaN can be used as the material of the semiconductor substrate 11A.

[0055] Wiring layer 11B is a layer on the main surface 11a side of semiconductor substrate 11A where metal wiring W electrically connected to transistor T is disposed. Bumps B are disposed on the surface of wiring layer 11B opposite to the semiconductor substrate 11A side. Package substrate 12 is a wiring substrate on which semiconductor chip 11 is mounted. Package substrate 12 is electrically connected to the metal wiring W disposed on wiring layer 11B of semiconductor chip 11 via bumps B. A power supply (V) for transistor T is disposed on package substrate 12. DD ) or ground (V SS The corresponding terminal 12a.

[0056] Figure 3 This is a schematic diagram showing an example of the layout of a portion of the semiconductor device 10 (the portion near the main surface 11a of the semiconductor substrate 11A). Figure 3 (A) is a schematic top view of the semiconductor substrate 11A viewed from the direction opposite to the main surface 11a. Figure 3 (B) is along Figure 3 A schematic cross-sectional view of the BB line of (A). Figure 3 (C) is along Figure 3 A schematic cross-sectional view of the CC line of (A). Figure 3As shown in (A), (B), and (C), a first conductivity type diffusion layer 11c1, 11c2 (11c) and an insulating layer 11d for separating the diffusion layer 11c are formed on the main surface 11a of the semiconductor substrate 11A. The diffusion layer 11c is the region where impurities are diffused. Here, as an example, the diffusion layer 11c1 is the region where n-type impurities are diffused, and the diffusion layer 11c2 is the region where p-type impurities are diffused. Figure 3 The pattern shown is a pattern of a single cell column extracted from semiconductor device 10. Insulating layer 11d contains elements that will be disposed in conjunction with... Figure 3 The component element separation layer 11d1 separates the component elements between each component element in the unit column direction corresponding to the lateral direction. The insulating layer 11d is formed of, for example, SiO2. Figure 3 As shown in (C), the diffusion layer 11c has a multi-peak shape generally referred to as a fin. Impurities different from those in the diffusion layer 11c are implanted onto the upper part of the fins via ion implantation or the like. Here, as an example, a specific concentration of p-type impurities is implanted onto the upper part of the diffusion layer 11c1, and a specific concentration of n-type impurities is implanted onto the upper part of the diffusion layer 11c2. Thus, fin portions 14a and 14b (14) of the second conductivity type are formed. In this embodiment, as an example, the semiconductor device 10 is a device manufactured using a 7nm process (7nm device), and the adjacent gates 13 are spaced apart by, for example, several tens of nm. By applying a voltage to the gates 13 formed across the fin portions 14 as described above, the portion including the fin portions 14 and the gates 13 functions as a transistor T of the semiconductor device 10. A transistor T having such a structure is called a FinFET (Fin Field-Effect Transistor). The diffusion layer 11c1 (the region where n-type impurities are diffused) and the fin portion 14a formed thereon (the region where p-type impurities are implanted) operate as a p-type transistor (PMOS). On the other hand, the diffusion layer 11c2 (the region where p-type impurities are diffused) and the fin portion 14b formed thereon (the region where n-type impurities are implanted) operate as an n-type transistor (NMOS). Although a gate 13a is also formed on the component element separation layer 11d1 in addition to the gate 13 spanning the fin portion 14, this gate 13a does not function as a regular gate and is called a dummy gate. The fin portion 14 is electrically connected to the metal wiring W (metal layer 1) via a via V (also called a contact). Thus, each fin portion 14 is electrically connected to the power supply (V) via the via V (contact) and the metal wiring W. DD ), grounding (V) SS ), or constitute the gate 13 of other transistors T.

[0057] The semiconductor inspection apparatus 1 includes: a laser source 2 (light source), a laser scanning unit 3 (scanning unit), an amplifier 4 (measuring unit), a computer 5, an input device 6, and a display device 7. The laser source 2 and the laser scanning unit 3 constitute an optical system for irradiating and scanning the semiconductor device 10 with a laser L as a stimulus light. The laser source 2 is the light source that emits the laser L. The laser scanning unit 3 performs two-dimensional scanning of the laser L emitted from the laser source 2 onto the semiconductor device 10. The laser scanning unit 3 is constructed from, for example, a galvanometer mirror or a MEMS mirror. The laser scanning unit 3 is configured to scan the laser L transmitted from the back surface 11b of the semiconductor substrate 11A towards the main surface 11a. The focal point of the laser L is adjusted to be near the main surface 11a of the semiconductor substrate 11A (i.e., the area where the transistor T is formed). Figure 1 As shown, a solid immersion lens (SIL) 8 can be disposed on the back surface 11b of the semiconductor substrate 11A. That is, the laser L can irradiate the back surface 11b of the semiconductor substrate 11A through the solid immersion lens 8. When the solid immersion lens 8 is disposed, the numerical aperture (NA) of the laser L irradiating the back surface 11b of the semiconductor substrate 11A can be increased compared to the case where the solid immersion lens 8 is not disposed.

[0058] The laser source 2 can, for example, be configured to emit a laser L with an energy higher than that of the material of the semiconductor substrate 11A (silicon in this embodiment, 1.12 eV in the case of silicon). That is, the laser L can be light with a wavelength shorter than the wavelength (1107 nm) corresponding to the band gap (energy gap) of silicon. In this case, photovoltaic current (OBIC, optical beam induced current) can be preferably generated in the transistor T (e.g., pn junction) on the main surface 11a side of the semiconductor substrate 11A by generating single photon absorption (SPA).

[0059] Alternatively, the laser source 2 can be configured to emit pulsed light, i.e., laser L, having an energy lower than the bandgap of the material of the semiconductor substrate 11A. That is, laser L can be pulsed light with a wavelength longer than the wavelength corresponding to the bandgap of silicon (1107 nm). In this case, OBIC can be generated more effectively in the transistor T (e.g., pn junction) on the main surface 11a side of the semiconductor substrate 11A by generating multiphoton absorption (MPA) as described, for example, in Japanese Patent Application Publication No. 10-332794.

[0060] For each irradiation position of the laser L, amplifier 4 measures the characteristics of the electrical signal of the semiconductor device 10 corresponding to the irradiation of the laser L. In this embodiment, amplifier 4 obtains the measured value (OBIC signal) of the OBIC generated by the semiconductor device 10 corresponding to the irradiation of the laser L, as a characteristic of the aforementioned electrical signal. Amplifier 4 has a pair of terminals 4a and 4b. One terminal 4a of amplifier 4 is electrically connected to the power supply (V) on the drain side of transistor T. DD The corresponding terminal 12a of the package substrate 12. The other terminal 4b of the amplifier 4 is electrically connected to ground (V) on the source side of the transistor T. SS The corresponding terminal 12a of the packaging substrate 12. The amplifier 4 inputs the measured value (OBIC signal) obtained by detecting and amplifying the OBIC generated by the laser L to the computer 5.

[0061] Computer 5 is a device that performs various image processing tasks described later, processes OBIC signals input from the self-amplifier 4, and controls the various parts constituting the semiconductor inspection device 1. Computer 5 includes, for example, a processor (e.g., CPU), built-in memory (e.g., ROM, RAM), and storage media (e.g., HDD, SSD). As functional components, computer 5 includes: a storage unit 51, a first generation unit 52, a second generation unit 53, an image processing unit 54 (processing unit), and a control unit 55. Furthermore, computer 5 is connected to input devices 6 such as a mouse and keyboard for inputting data into computer 5, and a display device 7 such as a monitor for displaying (outputting) the processing results (images, etc.) of computer 5. The various functions of computer 5 are implemented, for example, by the processor executing computer programs stored in the built-in memory or the storage media.

[0062] The storage unit 51 stores a layout image of the semiconductor device 10 to be inspected. Figure 4 This is a diagram showing an example of a layout image (layout image P1). Layout image P1 is, for example, a design image showing a pattern of a semiconductor device 10 obtained from external CAD data, etc. Additionally, the storage unit 51 stores current path information representing the current paths corresponding to layout image P1. The current path information is, for example, information representing objects (connection objects) connected to each area shown in layout image P1 via metal wiring W of wiring layer 11B. As an example of such a classification of current paths (connection objects), for example, power supply (V... DD ), grounding (V) SS There are four types: gate, no connection destination, etc. In addition, the storage unit 51 is suitable for storing the OBIC signal transmitted by the self-amplifier 4, the processing results (data such as images) of the first generation unit 52, the second generation unit 53, and the image processing unit 54, which will be described later.

[0063] The first generation unit 52 generates a first pattern image of the semiconductor device 10 based on characteristic information representing the characteristics of the electrical signal obtained at each irradiation position. In this embodiment, the characteristic information is the OBIC signal measured by the amplifier 4. Furthermore, the first pattern image is an OBIC image obtained based on the OBIC signal. The OBIC image is an image obtained by establishing a correspondence between the value of the OBIC signal and the position of the irradiated laser L and then visualizing it (i.e., converting the value of the OBIC signal into pixel values). In this embodiment, the OBIC image has pixel values ​​set such that areas with higher OBIC current are brighter. Figure 5 This is a schematic diagram of the OBIC image of semiconductor device 10 (7nm device) (OBIC image P2). Specifically, Figure 5 The OBIC image P2 shown is an image created by the inventors by analogy based on the OBIC image of a semiconductor device manufactured using a 40nm process.

[0064] Figure 6 This is a graph showing the relationship between the wavelength of laser L and the resolution of the obtained OBIC image, and the relationship between the wavelength of laser L and the transmittance of the silicon substrate. Figure 6 In the diagram, the dashed line represents the wavelength (1107 nm) corresponding to the band gap of silicon. Curve G1 represents the resolution of the OBIC image obtained when single-photon absorption (SPA) is generated. Curve G2 represents the resolution of the OBIC image obtained when multiphoton absorption (MPA) is generated. Figure 6As shown, the resolution (G2) for MPA generation is 1 / √2 of the resolution (G1) for SPA generation. Furthermore, curve G3 represents the relationship between the wavelength of laser L and the transmittance of the silicon substrate (here, as an example, a silicon substrate with a thickness of 100 μm). As shown in curve G3, in MPA using a laser L with a wavelength longer than the bandgap of silicon, since approximately 100% of laser L is transmissible through the silicon substrate, highly efficient laser L irradiation can be achieved. Specifically, in SPA using a laser L with a wavelength of 1000 nm, the resolution is approximately 160 nm, and the transmittance of laser L through the silicon substrate is approximately 50%. In contrast, in MPA using a laser L (pulsed light) with a wavelength of 1300 nm, a resolution equal to or greater than that of SPA using a laser L with a wavelength of 1000 nm (approximately 150 nm) is obtained, and the transmittance of laser L through the silicon substrate becomes approximately 100%. Therefore, based on the viewpoints of seeking both improved resolution and improved irradiation efficiency of the laser L, it is preferable to use a laser L that generates MPA (i.e., pulsed light with energy lower than the band gap of silicon) compared to using a laser L that generates SPA. On the other hand, the pulsed laser used for MPA must have a high peak value. Such a pulsed laser can be exemplified by, for example, an ultrashort pulse laser known as a femtosecond laser. When using such a special laser, limitations are imposed on stability and the range of wavelength selection. In addition, the laser itself is also more expensive. Therefore, based on the viewpoint of seeking to reduce the device price (manufacturing cost) of the semiconductor device 10, it is preferable to use SPA compared to using MPA. However, there are also cases where resolution must be prioritized for sufficient resolution. Therefore, the choice between a device equipped with SPA or MPA depends on the user's requirement for a certain level of detailed resolution of the semiconductor device 10.

[0065] Here, the pn junction is where electron-hole pairs are generated by laser L irradiation. Then, the part of the pn junction most easily carrying the OBIC is connected to the power supply (V). DD ) or ground (V SS In the pn junction where the current is connected to the gate, some OBICs flow due to leakage from the gate. On the other hand, in the pn junction where the current is not connected to any part, almost no OBICs flow. Furthermore, in a portion of the element separation layer 11d1 where the dummy gate 13a is provided (excluding the portion overlapping with the dummy gate 13a), even if OBICs flow, it is very small. Thus, in the semiconductor device 10, the amount of OBIC current differs for each category of the aforementioned current paths. Moreover, due to this difference in current amount, a difference in the depth of each region is generated in the OBIC image P2.

[0066] Therefore, based on the properties of the aforementioned OBIC image, the second generation unit 53 generates an image similar to the OBIC image P2 (a second pattern image) from the layout image P1. That is, the second generation unit 53 generates a second pattern image of the semiconductor device 10 based on the layout image P1 of the semiconductor device 10 and the current path information of the semiconductor device 10 (in this embodiment, the classification of current paths (connection objects) in each region). For example, the second generation unit 53 performs the first and second processes described later.

[0067] (Process 1)

[0068] The first process includes classification processing and color setting processing. The classification processing is a process of classifying at least a portion of the diffusion layer 11c and at least a portion of the element separation layer 11d1 contained in the semiconductor device 10 based on current path information. The color setting processing is a process of setting colors corresponding to the classification of the current path for at least a portion of the diffusion layer 11c and at least a portion of the element separation layer 11d1 in the layout image P1. Figure 7 A diagram for displaying the frame setting image P3 generated by the first processing of the layout image P1.

[0069] (Categorized processing)

[0070] As an example, during the classification process, the second generation unit 53 sets rectangular frame regions BA (BA1, BA2, BA3) between adjacent gates 13 in the diffusion layer 11c (the region where the diffusion layer 11c is disposed when viewed from the thickness direction of the semiconductor substrate 11A). Similarly, the second generation unit 53 sets rectangular frame regions BA (BA4) between adjacent gates 13a in the element separation layer 11d1. Frame regions BA1 to BA4 are classified according to the current path described above. Specifically, frame region BA1 is connected to the power supply (V... DD ) or ground (V SS The regions are as follows: BA2 is the region connected to the gate; BA3 is the region without a connection destination (an isolated region in the diffusion layer 11c); and BA4 is the region isolated in the element separation layer 11d1.

[0071] (Color settings processing)

[0072] Subsequently, in the color setting process, the second generation unit 53 sets colors corresponding to the classification of current paths for each frame region BA1 to BA4. As described above, the magnitude relationship of the current of the OBIC corresponding to each frame region BA1 to BA4 is "BA1 > BA2 > BA3 > BA4". Therefore, in the OBIC image P2, the area corresponding to frame region BA2 becomes darker than the area corresponding to frame region BA1. In addition, the area corresponding to frame region BA3 becomes darker than the area corresponding to frame region BA2. In addition, the area corresponding to frame region BA4 becomes darker than the area corresponding to frame region BA3. For this reason, the second generation unit 53 sets the brightest color (e.g., a color close to white) for frame region BA1, sets a color darker than frame region BA1 (e.g., light gray) for frame region BA2, sets a color darker than frame region BA2 (e.g., dark gray) for frame region BA3, and sets a color darker than frame region BA3 (e.g., a color close to black) for frame region BA4. Furthermore, the second generation unit 53 removes the pattern outside the frame area BA1 to BA4 from the frame-set image P3. Thus, as... Figure 8 As shown, a colored image P4 is obtained containing only the colored bounding box regions BA.

[0073] (Second Process)

[0074] The second process is the generation of a second pattern image based on the colored image P4. As an example, the second generation unit 53 generates the second pattern image by performing blurring processing on the colored image P4. As blurring processing, well-known blurring methods can be used. The blurring parameters (blurring degree) can be determined, for example, based on the OBIC image P2. For example, while the operator (user) checks the OBIC image P2 displayed on the display device 7, the operator determines the blurring degree of the colored image P4 in a manner that generates a second pattern image as similar as possible to the OBIC image P2. Furthermore, the second generation unit 53 generates the second pattern image (blurred image) by performing blurring processing on the colored image P4 based on the blurring degree input by the operator via the input device 6. Alternatively, the second generation unit 53 can perform blurring processing on the colored image P4 based on a pre-set blurring degree without manual intervention. Figure 9 A diagram showing an example of a blurred image P5 obtained through blurring processing.

[0075] Furthermore, the process of generating a blurred image P5 from the colored image P4 can be performed using a transformation process learned through machine learning instead of the aforementioned blurring process. For example, the second generation unit 53 can learn the transformation process of the colored image in advance using machine learning with teaching data, wherein the teaching data includes a colored image for learning and an OBIC image corresponding to the colored image for learning. Then, the second generation unit 53 can transform the colored image P4 using the transformation process determined by the aforementioned machine learning, thereby generating the blurred image P5.

[0076] For example, the second generation unit 53 can pre-create a learned model (hereinafter referred to as the "transformation model") with parameters (learned parameters) corresponding to the above-described transformation process, and store it in the storage unit 51. The transformation model, for example, is configured to use machine learning based on the above-described teaching data, input a colorized image, and output an image similar to the OBIC image (an image corresponding to the image generated by the above-described blurring process). The teaching data (the colorized image for learning and the OBIC image corresponding to the colorized image for learning) can, for example, be a colorized image and an OBIC image obtained from a semiconductor device previously designated as an inspection target. Furthermore, the second generation unit 53 can acquire the image output by the transformation model after inputting the colorized image P4 into the transformation model, as a blurred image P5. The transformation model can, for example, be a multi-layer neural network constructed using neural networks or deep learning. Examples of transformation models include CNN (Convolutional Neural Network), FCN (Fully Convolutional Networks), U-Net, and ResNet (Residual Network). However, the transformation model is not limited to a specific model. In addition, the number of nodes and layers in the transformation model can be set arbitrarily.

[0077] Image processing unit 54 based on OBIC image P2 (reference) Figure 5 ) and blurred image P5 (reference) Figure 9 The result of the alignment is used to obtain an image representing the OBIC image P2 and the layout image P1 (refer to the image P1). Figure 4Matching information regarding the relative relationship (correspondence) between OBIC image P2 and blurred image P5. For example, the position alignment of OBIC image P2 and blurred image P5 is performed by determining three or more corresponding points between OBIC image P2 and blurred image P5. Such position alignment can be performed using well-known pattern matching methods or by an operator. For example, image processing unit 54 can display OBIC image P2 and blurred image P5 to the user via display device 7, and obtain information indicating the correspondence between OBIC image P2 and blurred image P5 (e.g., information indicating three or more corresponding points) specified by the operator via input device 6. As described above, since blurred image P5 is an image generated based on colored image P4 in a manner as similar as possible to OBIC image P2, the position alignment of blurred image P5 and OBIC image P2 can be performed with corresponding accuracy by the operator's visual inspection. In addition, since blurred image P5 is an image generated based on layout image P1, the correspondence between the coordinates set in blurred image P5 and the coordinates set in layout image P1 is known in advance. Therefore, based on the alignment result of the OBIC image P2 and the blurred image P5, the image processing unit 54 can obtain matching information between the OBIC image P2 and the layout image P1. The obtained matching information is stored, for example, in the storage unit 51.

[0078] The matching information is used to determine which coordinate position of any coordinate position of the OBIC image P2 corresponds to which coordinate position of the layout image P1 (or, to determine which coordinate position of any coordinate position of the layout image P1 corresponds to which coordinate position of the OBIC image P2). The matching information may, for example, be information (e.g., a function) used to convert between the coordinates of the OBIC image P2 and the coordinates associated with the layout image P1. Here, the coordinates of the OBIC image P2 are coordinates associated with the irradiation position of the laser L, and are coordinates used for the operation control of the semiconductor inspection device 1 (i.e., coordinates of the coordinate system in which the semiconductor inspection device 1 performs identification). However, the information contained in the matching information is not limited to the above. For example, the matching information may include: angular information indicating the rotation angle of the layout image P1 relative to the OBIC image P2, or information such as the magnification of the layout image P1 relative to the OBIC image P2. To summarize the above, there exists a two-dimensional first coordinate system defining the layout image P1 and a two-dimensional second coordinate system defining the OBIC image P2. Here, the horizontal and vertical scales and angles may differ between the first and second coordinate systems. However, the coordinate planes of both systems are set to be flat and undistorted. In this case, three points (X1, Y1), (X2, Y2), and (X3, Y3) in the first coordinate system and three corresponding points (x1, y1), (x2, y2), and (x3, y3) in the second coordinate system are specified. With no distortion in the first and second coordinate systems, a correspondence is established between the points in the first and second coordinate systems through a single transformation. Based on this correspondence, a transformation formula is obtained to convert any point in one coordinate system to its corresponding point in the other. The function described above is equivalent to this transformation formula. Additionally, angle information or magnification can also be included in this transformation formula. The transformation formula can be simplified when specific conditions (e.g., the two coordinate systems lie on the same plane) hold between the two coordinate systems. For example, the conversion between the first coordinate system and the second coordinate system can be performed simply by rotating or offsetting the coordinates.

[0079] The image processing unit 54 can generate an overlapping image P6 (see reference) based on the matching information obtained as described above, which overlaps the layout image P1 with the OBIC image P2. Figure 11 In addition, in Figure 11For convenience, the overlapping image P6 is represented in solid color. In reality, the overlapping image P6 is formed by overlaying another image with a set transmittance onto one of the layout image P1 and the OBIC image P2. By using the matching information described above, an overlapping image P6 that precisely overlaps the layout image P1 and the OBIC image P2 can be obtained. As a result, fault analysis using the overlapping image P6 can be performed with high precision. Furthermore, the image processing unit 54 can generate an image that overlaps images other than the layout image P1 and the OBIC image P2 (e.g., frame setting image P3, colored image P4, blurred image P5, etc.) as needed, as the overlapping image P6. For example, the image processing unit 54 allows the operator to select the images to be overlapped, the order of overlap, the transmittance of each image, etc., and generates the overlapping image based on the selected content.

[0080] Alternatively, the image processing unit 54 can arrange and display the layout image P1 and the OBIC image P2 on the display of the display device 7. In this case, when an operator operates the input device 6 via a mouse or the like to point the cursor to any position on one of the images, the image processing unit 54 can display another cursor at a position on the other image corresponding to the cursor position on the first image, based on matching information. Through such a side-by-side display, the operator can easily grasp the correspondence between the layout image P1 and the OBIC image P2.

[0081] Furthermore, the image processing unit 54 can determine the location of the fault, as determined by fault analysis of the semiconductor device 10, and its location on the layout image P1, or set the detection location of the semiconductor device 10, based on the matching information. For example, the image processing unit 54 applies a specific electrical signal test pattern, a specific voltage, or a specific current to the semiconductor device 10 using a tester (not shown) provided with the semiconductor inspection apparatus 1, and captures images (not shown) of the heat or light emitted due to the fault of the semiconductor device 10. As described above, the coordinates of the fault location (reaction location) shown in the heat or light emission image captured by the camera are used as the coordinates of the OBIC image P2 (i.e., the coordinates used for operation control of the semiconductor inspection apparatus 1). Therefore, the image processing unit 54 can determine the fault location on the layout image P1 by using the matching information. Furthermore, the fault analysis method is not limited to a specific method. For example, in addition to the above-mentioned heat analysis or light emission analysis, other fault analysis methods include OBIRCH (Optical Beam Induced Resistance Current) analysis, SDL (Soft Defect Localization) analysis, LADA (Laser Assisted Device Alteration) analysis, and EOFM (Electro-Optical Frequency Mapping) analysis.

[0082] Furthermore, by using matching information, any coordinate on the layout image P1 can be converted into coordinates on the corresponding OBIC image P2 (i.e., coordinates used for operation control of the semiconductor inspection device 1). In other words, by using matching information, any coordinate on the layout image P1 can be specified, thereby specifying the detection position performed by the semiconductor inspection device 1. For example, the image processing unit 54 displays the operator prompt icon layout image P1 via the display device 7 and obtains the position (coordinates) on the layout image P1 specified by the operator via the input device 6. Then, the image processing unit 54 converts the coordinates obtained as described above into coordinates used for operation control of the semiconductor inspection device 1 based on the matching information, and can set the detection position performed by the semiconductor inspection device 1 (e.g., the detection position during EOP (Electro Optical Probing) analysis). As described above, by utilizing matching information, fault analysis (determination of fault locations on the layout image or setting of detection positions) can be performed with high precision.

[0083] The control unit 55 controls the data processing of the computer 5 and the operation of various devices connected to the computer 5 (laser light source 2, laser scanning unit 3, amplifier 4, input device 6, display device 7, etc.).

[0084] Secondly, refer to Figure 10 and Figure 11 An example of the processing sequence of the semiconductor inspection method performed by the semiconductor inspection apparatus 1 will be described.

[0085] In step S1, the semiconductor inspection apparatus 1 (mainly consisting of a laser light source 2, a laser scanning unit 3, and an amplifier 4) scans the laser L over the semiconductor device 10 and acquires characteristic information (in this embodiment, an OBIC signal) representing the characteristics of the electrical signal of the semiconductor device 10 corresponding to the irradiation of the laser L at each irradiation position of the laser L. Then, the semiconductor inspection apparatus 1 (mainly consisting of a first generation unit 52) ​​generates a first pattern image of the semiconductor device 10 (in this embodiment, an OBIC image P2) based on the characteristic information of each irradiation position (see reference). Figure 5 ).

[0086] In step S2, the semiconductor inspection device 1 (mainly the second generation unit 53) generates a second pattern image (in this embodiment, a blurred image P5) based on the layout image P1 and current path information. As an example, the second generation unit 53, as described above, generates a frame setting image P3 (see reference 1) based on the layout image P1 and current path information. Figure 7 Based on the frame setting image P3, a colored image P4 is generated (refer to...). Figure 8 Based on the colored image P4, generate the blurred image P5 (refer to...). Figure 9 In addition, step S2 can be executed earlier than step S1, or steps S1 and S2 can be executed in parallel.

[0087] In step S3, the semiconductor inspection device 1 (mainly the image processing unit 54) obtains matching information based on the positional alignment result of the first pattern image (OBIC image P2) and the second pattern image (blurred image P5).

[0088] In step S4, the semiconductor inspection device 1 (mainly the image processing unit 54) generates an overlapping image P6 that overlaps the first pattern image (OBIC image P2) with the layout image P1 by using matching information.

[0089] In step S5, the semiconductor inspection device 1 (mainly the image processing unit 54) uses matching information to perform fault analysis. For example, the semiconductor inspection device 1 can, as described above, determine the fault location determined by the fault analysis of the semiconductor device 10 and its location on the layout image P1, or set the detection location for the semiconductor device 10. Furthermore, when performing the processing in step S5, it is not necessarily necessary to perform the processing to generate the overlapping image P6 of step S4, but by generating the overlapping image P6 and showing it to the operator, the convenience of the operator performing fault analysis can be improved.

[0090] [Effects]

[0091] It is known that light (e.g., laser light) illuminating a semiconductor device 10 has a certain degree of spread, and the full width at half maximum (FWHM) of the reflected light from the semiconductor device 10 is greater than the full width at half maximum (FWHM) of the incident light toward the semiconductor device 10. Here, the resolution of an optical image obtained based on reflected light depends on the observed full width at half maximum (FWHM), while the resolution of a first pattern image (OBIC image P2) not based on reflected light depends on the full width at half maximum (FWHM) of the incident light toward the semiconductor device 10. Furthermore, the smaller the full width at half maximum (FWHM) of the light, the smaller the resolution of the obtained image. Therefore, by generating the first pattern image (OBIC image P2) based on the characteristics of the electrical signal (OBIC signal) of the semiconductor device 10 corresponding to the illumination of light, an image with a higher resolution than an optical image obtained based on reflected light can be obtained. Furthermore, based on the alignment result of the second pattern image (fuzzy image P5) obtained from the layout image P1 and the current path of the semiconductor device 10 with the first pattern image (OBIC image P2), high-precision matching information between the first pattern image (OBIC image P2) and the layout image P1 can be obtained. According to the above description, based on the semiconductor inspection apparatus 1 and the semiconductor inspection method described above, the first pattern image (OBIC image P2) obtained from the semiconductor device 10 can be aligned with the layout image P1 of the semiconductor device 10 with high precision. As a result, the fault location of the semiconductor device 10 determined through fault analysis can be displayed on the layout image P1, or the detection position can be easily set by specifying a position on the layout image P1.

[0092] Furthermore, the second generation unit 53 can perform: a first process, which classifies at least one of at least a portion of the diffusion layer 11c and at least one of at least a portion of the element separation layer 11d1 contained in the semiconductor device 10 (both in this embodiment) based on current path information, and sets a color corresponding to the classification for at least one of at least a portion of the diffusion layer 11c and at least one of at least a portion of the element separation layer 11d1 in the layout image P1; and a second process, which generates a second pattern image (blurred image P5) based on the colored image P4 generated by the first process. According to the above configuration, a second pattern image (blurred image P5) that can be aligned with the position of the layout image P1 with high precision can be obtained from the colored image P4 colored based on current path information.

[0093] Furthermore, the second process described above may include blurring the colored image P4. According to the above configuration, through blurring, a second pattern image (blurred image P5) similar to the first pattern image (OBIC image P2) can be obtained. As a result, a second pattern image (blurred image P5) that can be precisely aligned with the position of the first pattern image (OBIC image P2) can be obtained.

[0094] Furthermore, the second process described above can be performed as follows: a process of learning the transformation process of the tinted image P4 using machine learning with teaching data, wherein the teaching data includes the tinted image P4 for learning and a first pattern image (OBIC image P2) corresponding to the tinted image P4 for learning; and a process of transforming the tinted image P4 using the transformation process determined by learning, thereby generating a second pattern image (blurred image P5). According to the above configuration, through the transformation process based on the results of machine learning, a second pattern image (blurred image P5) similar to the first pattern image (OBIC image P2) can be obtained. As a result, the positions of the first pattern image (OBIC image P2) and the second pattern image (blurred image P5) can be aligned with high precision.

[0095] Furthermore, the image processing unit 54 can perform: processing of the first pattern image (OBIC image P2) and the second pattern image (blurred image P5) shown to the user; and processing of obtaining matching information based on information specified by the user indicating the correspondence between the first pattern image (OBIC image P2) and the second pattern image (blurred image P5). According to the above configuration, the user can perform visual alignment of the first pattern image (OBIC image P2) and the second pattern image (blurred image P5).

[0096] Additionally, amplifier 4 can acquire a measured value (OBIC signal) of the photovoltaic current (OBIC) generated by the irradiation of semiconductor device 10 by laser L, as characteristic information. Based on the above configuration, an OBIC image with a hue (depth) set to correspond to the measured value of the photovoltaic current can be obtained as a first pattern image.

[0097] [Example of variation]

[0098] While one embodiment of this disclosure has been described above, this disclosure is not limited to the described embodiment. The materials and shapes of each component are not limited to those described above, and various materials and shapes may be used.

[0099] For example, although in the above embodiment, the blurred image P5 obtained by blurring the colored image P4 (or by transformation processing through a transformation model) is used as the second pattern image, the colored image P4 can be used as the second pattern image.

[0100] Furthermore, the aforementioned process of obtaining matching information can be performed using position alignment processing learned through machine learning. For example, the image processing unit 54 can perform machine learning in advance using teaching data to learn position alignment processing between a first pattern image (OBIC image P2) and a second pattern image (colored image P4 or blurred image P5), wherein the teaching data includes the first pattern image (OBIC image P2) for learning, the second pattern image (colored image P4 or blurred image P5) corresponding to the first pattern image (OBIC image P2) for learning, and the matching results (position alignment results) of these images. For example, the image processing unit 54 can prepare a completed learning model (hereinafter referred to as "position alignment model") with parameters (learning parameters) corresponding to the aforementioned position alignment processing in advance and store it in the storage unit 51. The position alignment model is, for example, a model configured as follows: by using machine learning using the aforementioned teaching data, the first pattern image and the second pattern image are input, and the position alignment results (e.g., coordinates of three or more corresponding points in the two images) are output. As teaching data, for example, a combination of OBIC images, colored images (or blurred images), and matching results obtained by processing semiconductor devices previously designated as inspection targets can be used.

[0101] Furthermore, the image processing unit 54 can perform the following processing: using the positional alignment processing determined through the above learning, it performs positional alignment of the first pattern image (OBIC image P2) and the second pattern image (colored image P4 or blurred image P5), thereby obtaining matching information representing the relative relationship between the first pattern image (OBIC image P2) and the layout image P1. For example, the image processing unit 54 can obtain the result output from the positional alignment model by inputting the first pattern image and the second pattern image to the positional alignment model, as the result of positional alignment of these images. Moreover, the image processing unit 54 can obtain matching information based on the positional alignment result obtained as described above. The positional alignment model is, for example, a multi-layer neural network constructed by a neural network or deep learning. Examples of positional alignment models are CNN (Convolutional Neural Network), FCN (Fully Convolutional Networks), U-Net, ResNet (Residual Network), etc. However, the positional alignment model is not limited to a specific model. Furthermore, the number of nodes and layers in the alignment model can be arbitrarily set. Based on the above configuration, high-precision alignment of the first and second pattern images can be achieved through machine learning-based alignment processing. However, when using the colored image P4 as the second pattern image, the accuracy of alignment may decrease with operator visual inspection or previous pattern matching methods. On the other hand, by using the above-described alignment model, high-precision alignment of the first and second pattern images can be expected even when using the colored image P4 as the second pattern image. In other words, using the above-described alignment model ensures alignment accuracy and eliminates the need for processing the generation of a blurred image P5 from the colored image P4.

[0102] Reference Figures 12-15 Hereinafter, configuration examples (1st to 5th configuration examples) for obtaining OBIC signals will be described.

[0103] (Example 1)

[0104] Figure 12 To illustrate a schematic diagram of the first configuration example. In this example, the semiconductor device 10 is divided into multiple blocks BR with different power supply voltages. Block BR1 is configured such that it is powered by a power supply V... DD1 Applying the first voltage, block BR2 is powered by power supply V. DD2 Apply the second voltage. In this case, when obtaining the OBIC signal by scanning the laser L for the area of ​​block BR1, simply connect one terminal 4a of amplifier 4 (connected to ground V)SS Terminal 4b on the opposite side is connected to the power supply V. DD1 The corresponding terminal 12a of the packaging substrate 12 is sufficient. On the other hand, when scanning the area of ​​block BR2 with laser L to obtain the OBIC signal, it is only necessary to connect one terminal 4a of amplifier 4 to the power supply V. DD2 The corresponding terminal 12a of the packaging substrate 12 is sufficient.

[0105] (Example 2)

[0106] Figure 13 To show a schematic diagram of the second structural example. (As shown) Figure 13 As shown, the aforementioned semiconductor device 10 (semiconductor chip 11 and packaging substrate 12) can be mounted on a board 16 such as a printed circuit board via a bracket 15. In this case, the terminals 4a and 4b of the amplifier 4 can be connected to the power supply terminal and the ground terminal provided on the board 16.

[0107] (Example 3)

[0108] Figure 14 (A) is a schematic diagram showing the third constituent example. Figure 14 As shown in (A), when the power supply V DD and grounding V SS In the case where it is directly connected to the semiconductor chip 11, as long as, for example Figure 13 Connect terminals 4a and 4b of amplifier 4 to power supply V as shown. DD and grounding V SS Without applying a bias voltage, monitor the current I flowing in response to the irradiation of laser L. DD The change in the signal (i.e., the OBIC signal) can be observed. By not applying a bias voltage, the noise component can be minimized, making it easy to measure (identify) the OBIC signal.

[0109] (Example 4)

[0110] Figure 14 (B) is a schematic diagram showing the fourth constituent example. Figure 14 As shown in (B), when the MOS switch SW is set to ground V SS In this case, by setting the semiconductor device 10 to standby mode and grounding V... SS It is connected externally. In this state, current changes accompanied by an OBIC signal within a certain level of leakage current can be detected. Furthermore, Figure 14The diagram on the left of (B) is a simplified representation of the actual configuration. In reality, the circuit controls the switching of the MOS (transistor T) to turn on / off. Furthermore, amplifier 4 can be constructed using a differentiating circuit to detect minute currents. In this case, the change in current can be detected. That is, when the OBIC signal is greater than the noise component, the offset of the noise component, etc., can be ignored.

[0111] (Fifth example)

[0112] Figure 15 A schematic diagram of the fifth configuration example is shown. In this example, a power management circuit (PMC) C is provided in the semiconductor device 10. The power management circuit C is configured to regulate the power supply V. DD The supplied voltage will be the adjusted power supply voltage (V). DD1 V DD2 The supply to each block BR ​​of the semiconductor device 10 (refer to) Figure 12 In this situation, in order to obtain the power supply voltage (V) DD1 The OBIC signal generated when the corresponding block BR ​​is irradiated by laser L must be adjusted according to the supply power voltage (V). DD1 ) power cord W DD1 Access is performed. Therefore, in this example, a power line W is formed on the back side 11b of the semiconductor substrate 11A, extending from the back side 11b to the wiring layer 11B. DD1 The opening 11e. In the opening 11e, an insulating portion 17 made of an insulator, formed by FIB processing such as FIBCVD, and a pad 18 made of metal, also formed by FIB processing, are disposed. The front end of the inner side (wiring layer 11B side) of the pad 18 is connected to the power line W. DD1 The outer surface of pad 18 is exposed at the opening 11e. An insulating portion 17 is formed to cover the periphery of pad 18. A power supply line W for measuring power is connected to the outer surface of pad 18. DD1 The probe PR carries the current flowing through it. Thus, for the power line W after the branch of the power management circuit C... DD1 The power line W can be measured by detecting the pad 18 exposed on the back side 11b of the semiconductor substrate 11A. DD1 The current flowing through it. Furthermore, typically in block BR ​​(refer to...) Figure 12 A wider power line corresponding to the block BR ​​is provided on the outer edge of the BR. In this case, the opening 11e described above only needs to be formed on the outer edge.

[0113] Furthermore, the first pattern image is not limited to an OBIC image. As the first pattern image, any image obtained by imagerizing the characteristics of an electrical signal observed corresponding to light irradiation (light stimulation) from the back surface 11b of the semiconductor substrate 11A can be used.

[0114] [Symbol Explanation]

[0115] 1… Semiconductor inspection apparatus, 2… Laser light source (light source), 3… Laser scanning unit (scanning unit), 4… Amplifier (measuring unit), 10… Semiconductor device, 11A… Semiconductor substrate, 11a… Main surface, 11b… Back surface, 11c, 11c1, 11c2… Diffusion layer, 11d… Insulating layer, 11d1… Component separation layer, 52… First generation unit, 53… Second generation unit, 54… Image processing unit (processing unit), L… Laser (light), P1… Layout image, P2… OBIC image (first pattern image), P4… Colored image (second pattern image), P5… Blurred image (second pattern image), P6… Overlapping image, T… Transistor.

Claims

1. A semiconductor inspection method, comprising: By scanning light onto a semiconductor device, characteristic information representing the characteristics of the electrical signal of the semiconductor device corresponding to the illumination of the light is obtained at each illumination position of the light, and a first pattern image of the semiconductor device is generated based on the characteristic information at each illumination position. The step of generating a second pattern image of the semiconductor device based on a layout image representing the layout of the semiconductor device and current path information representing the current path of the semiconductor device; and Based on the positional alignment of the first pattern image and the second pattern image, matching information representing the relative relationship between the first pattern image and the layout image is obtained.

2. The semiconductor inspection method as described in claim 1, wherein, The steps for generating the second pattern image include: The first process involves classifying at least one of a diffusion layer and at least one of a component separation layer contained in the semiconductor device based on the current path information, and assigning a color corresponding to the classification to at least one of the diffusion layer and at least one of the component separation layer in the layout image; and The second process generates the second pattern image based on the color image produced by the first process.

3. The semiconductor inspection method as described in claim 2, wherein, The second process includes blurring the colored image.

4. The semiconductor inspection method as described in claim 2, wherein, The second process includes: Machine learning is used to learn the transformation process of the shading image by using teaching data, which includes the shading image for learning and the first pattern image corresponding to the shading image for learning; and The coloring image is transformed using the transformation process determined through the learning, thereby producing the second pattern image.

5. The semiconductor inspection method according to any one of claims 1 to 4, wherein, The steps for obtaining the matching information include: The user is prompted with the first pattern image and the second pattern image; and The matching information is obtained based on the information specified by the user that represents the correspondence between the first pattern image and the second pattern image.

6. The semiconductor inspection method according to any one of claims 1 to 4, wherein, The steps for obtaining the matching information include: Machine learning is used to learn the positional alignment process between the first pattern image and the second pattern image by using teaching data, which includes the first pattern image used for learning, the second pattern image corresponding to the first pattern image used for learning, and the matching results of these images; and Using the position alignment process determined through the learning, the first pattern image and the second pattern image are aligned in position to obtain the matching information.

7. The semiconductor inspection method according to any one of claims 1 to 4, further comprising: Based on the matching information, an overlapping image is generated that causes the layout image to overlap with the first pattern image.

8. The semiconductor inspection method as described in claim 5, further comprising: Based on the matching information, an overlapping image is generated that causes the layout image to overlap with the first pattern image.

9. The semiconductor inspection method of claim 6, further comprising: Based on the matching information, an overlapping image is generated that causes the layout image to overlap with the first pattern image.

10. The semiconductor inspection method according to any one of claims 1 to 4, 8, and 9, further comprising: Based on the matching information, the fault location determined by fault analysis of the semiconductor device is compared with its location on the layout image, or the detection location of the semiconductor device is set.

11. The semiconductor inspection method of claim 5, further comprising: Based on the matching information, the fault location determined by fault analysis of the semiconductor device is compared with its location on the layout image, or the detection location of the semiconductor device is set.

12. The semiconductor inspection method of claim 6, further comprising: Based on the matching information, the fault location determined by fault analysis of the semiconductor device is compared with its location on the layout image, or the detection location of the semiconductor device is set.

13. The semiconductor inspection method of claim 7, further comprising: Based on the matching information, the fault location determined by fault analysis of the semiconductor device is compared with its location on the layout image, or the detection location of the semiconductor device is set.

14. The semiconductor inspection method according to any one of claims 1 to 4, 8, 9, 11 to 13, wherein, In the step of generating the first pattern image, a measured value corresponding to the photovoltaic current generated by irradiating light onto the semiconductor device is obtained as the characteristic information.

15. The semiconductor inspection method as described in claim 5, wherein, In the step of generating the first pattern image, a measured value corresponding to the photovoltaic current generated by irradiating light onto the semiconductor device is obtained as the characteristic information.

16. The semiconductor inspection method as described in claim 6, wherein, In the step of generating the first pattern image, a measured value corresponding to the photovoltaic current generated by irradiating light onto the semiconductor device is obtained as the characteristic information.

17. The semiconductor inspection method as described in claim 7, wherein, In the step of generating the first pattern image, a measured value corresponding to the photovoltaic current generated by irradiating light onto the semiconductor device is obtained as the characteristic information.

18. The semiconductor inspection method as described in claim 10, wherein, In the step of generating the first pattern image, a measured value corresponding to the photovoltaic current generated by irradiating light onto the semiconductor device is obtained as the characteristic information.

19. The semiconductor inspection method as described in claim 14, wherein, The semiconductor device has a semiconductor substrate having a main surface on which transistors are formed and a back surface opposite to the main surface. In the step of generating the first pattern image, light transmitted from the back surface to the main surface side is irradiated onto the back surface of the semiconductor substrate. The light has a higher energy than the band gap of the semiconductor substrate material.

20. The semiconductor inspection method according to any one of claims 15 to 18, wherein, The semiconductor device has a semiconductor substrate having a main surface on which transistors are formed and a back surface opposite to the main surface. In the step of generating the first pattern image, light transmitted from the back surface to the main surface side is irradiated onto the back surface of the semiconductor substrate. The light has a higher energy than the band gap of the semiconductor substrate material.

21. The semiconductor inspection method as described in claim 14, wherein, The semiconductor device has a semiconductor substrate having a main surface on which transistors are formed and a back surface opposite to the main surface. In the step of generating the first pattern image, light, which is pulsed light, transmitted from the back surface to the main surface side, is irradiated onto the back surface of the semiconductor substrate. The light has a lower energy than the band gap of the semiconductor substrate material.

22. The semiconductor inspection method according to any one of claims 15 to 18, wherein, The semiconductor device has a semiconductor substrate having a main surface on which transistors are formed and a back surface opposite to the main surface. In the step of generating the first pattern image, light, which is pulsed light, transmitted from the back surface to the main surface side, is irradiated onto the back surface of the semiconductor substrate. The light has a lower energy than the band gap of the semiconductor substrate material.

23. A semiconductor inspection apparatus, comprising: light source; The scanning unit scans the light from the light source for the semiconductor device; The measuring unit is electrically connected to the semiconductor device and measures the characteristics of the electrical signal of the semiconductor device corresponding to the irradiation of the light at each irradiation position. The first generation unit generates a first pattern image of the semiconductor device based on characteristic information representing the characteristics of the electrical signal at each irradiation position measured by the measurement unit. The second generation unit generates a second pattern image of the semiconductor device based on a layout image representing the layout of the semiconductor device and current path information representing the current path of the semiconductor device. and The processing unit obtains matching information representing the relative relationship between the first pattern image and the layout image based on the result of the positional alignment between the first pattern image and the second pattern image.

24. The semiconductor inspection apparatus of claim 23, wherein, The second generation unit performs the following: The first process classifies at least one of the diffusion layer and at least one of the component separation layer contained in the semiconductor device based on the current path information, and sets a color corresponding to the classification for at least one of the diffusion layer and at least one of the component separation layer in the layout image. and The second process generates the second pattern image based on the color image produced by the first process.

25. The semiconductor inspection apparatus of claim 24, wherein, The second process includes blurring the colored image.

26. The semiconductor inspection apparatus of claim 24, wherein, The second process is executed as follows: The transformation process of the coloring image is learned by using machine learning with teaching data, which includes the coloring image for learning and the first pattern image corresponding to the coloring image for learning; and The coloring image is transformed using the transformation process determined through the learning, thereby producing the second pattern image.

27. The semiconductor inspection apparatus according to any one of claims 23 to 26, wherein, The processing unit performs: The user is prompted with the first pattern image and the second pattern image; and The matching information is obtained based on the information specified by the user that represents the correspondence between the first pattern image and the second pattern image.

28. The semiconductor inspection apparatus according to any one of claims 23 to 26, wherein, The processing unit performs: Machine learning is used to learn the positional alignment process of the first pattern image and the second pattern image by using teaching data, which includes the first pattern image for learning, the second pattern image corresponding to the first pattern image for learning, and the matching results of these images; and Using the position alignment process determined through the learning, the first pattern image and the second pattern image are aligned in position to obtain the matching information.

29. The semiconductor inspection apparatus according to any one of claims 23 to 26, wherein, Based on the matching information, the processing unit generates an overlapping image that causes the layout image to overlap with the first pattern image.

30. The semiconductor inspection apparatus of claim 27, wherein, Based on the matching information, the processing unit generates an overlapping image that causes the layout image to overlap with the first pattern image.

31. The semiconductor inspection apparatus of claim 28, wherein, Based on the matching information, the processing unit generates an overlapping image that causes the layout image to overlap with the first pattern image.

32. The semiconductor inspection apparatus according to any one of claims 23 to 26, 30, and 31, wherein, Based on the matching information, the processing unit determines the location of the fault, which is determined by fault analysis of the semiconductor device, and its location on the layout image, or sets the detection location of the semiconductor device.

33. The semiconductor inspection apparatus of claim 27, wherein, Based on the matching information, the processing unit determines the location of the fault, which is determined by fault analysis of the semiconductor device, and its location on the layout image, or sets the detection location of the semiconductor device.

34. The semiconductor inspection apparatus of claim 28, wherein, Based on the matching information, the processing unit determines the location of the fault, which is determined by fault analysis of the semiconductor device, and its location on the layout image, or sets the detection location of the semiconductor device.

35. The semiconductor inspection apparatus of claim 29, wherein, Based on the matching information, the processing unit determines the location of the fault, which is determined by fault analysis of the semiconductor device, and its location on the layout image, or sets the detection location of the semiconductor device.

36. The semiconductor inspection apparatus according to any one of claims 23 to 26, 30, 31, and 33 to 35, wherein, The measuring unit obtains the measured value of the photovoltaic current generated by irradiating the semiconductor device with light as the characteristic information.

37. The semiconductor inspection apparatus of claim 27, wherein, The measuring unit obtains the measured value of the photovoltaic current generated by irradiating the semiconductor device with light as the characteristic information.

38. The semiconductor inspection apparatus of claim 28, wherein, The measuring unit obtains the measured value of the photovoltaic current generated by irradiating the semiconductor device with light as the characteristic information.

39. The semiconductor inspection apparatus of claim 29, wherein, The measuring unit obtains the measured value of the photovoltaic current generated by irradiating the semiconductor device with light as the characteristic information.

40. The semiconductor inspection apparatus of claim 32, wherein, The measuring unit obtains the measured value of the photovoltaic current generated by irradiating the semiconductor device with light as the characteristic information.

41. The semiconductor inspection apparatus of claim 36, wherein, The semiconductor device has a semiconductor substrate having a main surface on which transistors are formed and a back surface opposite to the main surface. The scanning unit scans the light transmitted from the back side of the semiconductor substrate toward the main surface. The light has a higher energy than the band gap of the semiconductor substrate material.

42. The semiconductor inspection apparatus according to any one of claims 37 to 40, wherein, The semiconductor device has a semiconductor substrate having a main surface on which transistors are formed and a back surface opposite to the main surface. The scanning unit scans the light transmitted from the back side of the semiconductor substrate toward the main surface. The light has a higher energy than the band gap of the semiconductor substrate material.

43. The semiconductor inspection apparatus of claim 36, wherein, The semiconductor device has a semiconductor substrate having a main surface on which transistors are formed and a back surface opposite to the main surface. The scanning unit scans the back side of the semiconductor substrate for pulsed light that passes through from the back side toward the main surface. The light has energy with a lower band gap compared to the material of the semiconductor substrate.

44. The semiconductor inspection apparatus according to any one of claims 37 to 40, wherein, The semiconductor device has a semiconductor substrate having a main surface on which transistors are formed and a back surface opposite to the main surface. The scanning unit scans the back side of the semiconductor substrate for pulsed light that passes through from the back side toward the main surface. The light has energy with a lower band gap compared to the material of the semiconductor substrate.

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